-- Xilinx Vhdl netlist produced by netgen application (version G.37)
-- Command       : -rpw 100 -ar Structure -xon true -w -ofmt vhdl -sim logic.nga logic_timesim.vhd 
-- Input file    : logic.nga
-- Output file   : logic_timesim.vhd
-- Design name   : logic.nga
-- # of Entities : 1
-- Xilinx        : C:/Xilinx
-- Device        : XC9536-5-PC44 (Speed File: Version 3.0)

-- This vhdl netlist is a simulation model and uses simulation 
-- primitives which may not represent the true implementation of the 
-- device, however the netlist is functionally correct and should not 
-- be modified. This file cannot be synthesized and should only be used 
-- with supported simulation tools.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;

entity logic is
  port (
    SPARE3 : in STD_LOGIC := 'X'; 
    SPARE2 : in STD_LOGIC := 'X'; 
    SPARE1 : in STD_LOGIC := 'X'; 
    OVERRIDE : in STD_LOGIC := 'X'; 
    HORIZON_STOP : in STD_LOGIC := 'X'; 
    HA_STOP : in STD_LOGIC := 'X'; 
    HA_EMERG : in STD_LOGIC := 'X'; 
    DEC_STOP : in STD_LOGIC := 'X'; 
    DEC_EMERG : in STD_LOGIC := 'X'; 
    W_THERM_DIS : in STD_LOGIC := 'X'; 
    S_THERM_DIS : in STD_LOGIC := 'X'; 
    N_THERM_DIS : in STD_LOGIC := 'X'; 
    E_THERM_DIS : in STD_LOGIC := 'X'; 
    DM3_THERM_DIS : in STD_LOGIC := 'X'; 
    DM2_THERM_DIS : in STD_LOGIC := 'X'; 
    DM1_THERM_DIS : in STD_LOGIC := 'X'; 
    WATCHDOG_TIMER : in STD_LOGIC := 'X'; 
    SPARE6 : in STD_LOGIC := 'X'; 
    SPARE5 : in STD_LOGIC := 'X'; 
    SPARE4 : in STD_LOGIC := 'X'; 
    MOTOR_CNTR_ERROR : in STD_LOGIC := 'X'; 
    EMERG_STOP : in STD_LOGIC := 'X'; 
    TCS_LOCKOUT : in STD_LOGIC := 'X'; 
    SPARE9 : in STD_LOGIC := 'X'; 
    SPARE10 : in STD_LOGIC := 'X'; 
    LOCKOUT_KSWTCH : in STD_LOGIC := 'X'; 
    BRAKE_LOCKOUT : out STD_LOGIC; 
    EMERGENCY : out STD_LOGIC; 
    BRAKE_RESET : out STD_LOGIC 
  );
end logic;

architecture Structure of logic is
  signal SPARE3_IBUF : STD_LOGIC; 
  signal SPARE2_IBUF : STD_LOGIC; 
  signal SPARE1_IBUF : STD_LOGIC; 
  signal OVERRIDE_IBUF : STD_LOGIC; 
  signal HORIZON_STOP_IBUF : STD_LOGIC; 
  signal HA_STOP_IBUF : STD_LOGIC; 
  signal HA_EMERG_IBUF : STD_LOGIC; 
  signal DEC_STOP_IBUF : STD_LOGIC; 
  signal DEC_EMERG_IBUF : STD_LOGIC; 
  signal W_THERM_DIS_IBUF : STD_LOGIC; 
  signal S_THERM_DIS_IBUF : STD_LOGIC; 
  signal N_THERM_DIS_IBUF : STD_LOGIC; 
  signal E_THERM_DIS_IBUF : STD_LOGIC; 
  signal DM3_THERM_DIS_IBUF : STD_LOGIC; 
  signal DM2_THERM_DIS_IBUF : STD_LOGIC; 
  signal DM1_THERM_DIS_IBUF : STD_LOGIC; 
  signal WATCHDOG_TIMER_IBUF : STD_LOGIC; 
  signal SPARE6_IBUF : STD_LOGIC; 
  signal SPARE5_IBUF : STD_LOGIC; 
  signal SPARE4_IBUF : STD_LOGIC; 
  signal MOTOR_CNTR_ERROR_IBUF : STD_LOGIC; 
  signal EMERG_STOP_IBUF : STD_LOGIC; 
  signal TCS_LOCKOUT_IBUF : STD_LOGIC; 
  signal SPARE9_IBUF : STD_LOGIC; 
  signal SPARE10_IBUF : STD_LOGIC; 
  signal LOCKOUT_KSWTCH_IBUF : STD_LOGIC; 
  signal BRAKE_LOCKOUT_OBUF_Q : STD_LOGIC; 
  signal EMERGENCY_OBUF_Q : STD_LOGIC; 
  signal BRAKE_RESET_OBUF : STD_LOGIC; 
  signal BRAKE_LOCKOUT_OBUF_Q_0 : STD_LOGIC; 
  signal BRAKE_LOCKOUT_OBUF_D : STD_LOGIC; 
  signal BRAKE_LOCKOUT_OBUF_D1 : STD_LOGIC; 
  signal BRAKE_LOCKOUT_OBUF_D2 : STD_LOGIC; 
  signal EMERGENCY_OBUF_Q_1 : STD_LOGIC; 
  signal EMERGENCY_OBUF_D : STD_LOGIC; 
  signal EMERGENCY_OBUF_D1 : STD_LOGIC; 
  signal EMERGENCY_OBUF_D2 : STD_LOGIC; 
  signal EXP0_EXP : STD_LOGIC; 
  signal EMERGENCY_OBUF_D2_PT_0 : STD_LOGIC; 
  signal EXP1_EXP : STD_LOGIC; 
  signal EMERGENCY_OBUF_D2_PT_1 : STD_LOGIC; 
  signal Vcc : STD_LOGIC; 
  signal EMERGENCY_OBUF_D2_PT_2 : STD_LOGIC; 
  signal EMERGENCY_OBUF_D2_PT_3 : STD_LOGIC; 
  signal EMERGENCY_OBUF_D2_PT_4 : STD_LOGIC; 
  signal EMERGENCY_OBUF_D2_PT_5 : STD_LOGIC; 
  signal EMERGENCY_OBUF_D2_PT_6 : STD_LOGIC; 
  signal BRAKE_RESET_OBUF_Q : STD_LOGIC; 
  signal BRAKE_RESET_OBUF_D : STD_LOGIC; 
  signal BRAKE_RESET_OBUF_D1 : STD_LOGIC; 
  signal BRAKE_RESET_OBUF_D2 : STD_LOGIC; 
  signal EXP2_EXP : STD_LOGIC; 
  signal BRAKE_RESET_OBUF_D2_PT_0 : STD_LOGIC; 
  signal EXP3_EXP : STD_LOGIC; 
  signal BRAKE_RESET_OBUF_D2_PT_1 : STD_LOGIC; 
  signal BRAKE_RESET_OBUF_D2_PT_2 : STD_LOGIC; 
  signal BRAKE_RESET_OBUF_D2_PT_3 : STD_LOGIC; 
  signal BRAKE_RESET_OBUF_D2_PT_4 : STD_LOGIC; 
  signal BRAKE_RESET_OBUF_D2_PT_5 : STD_LOGIC; 
  signal BRAKE_RESET_OBUF_D2_PT_6 : STD_LOGIC; 
  signal EXP0_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal EXP0_EXP_PT_0 : STD_LOGIC; 
  signal EXP0_EXP_PT_1 : STD_LOGIC; 
  signal EXP1_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal EXP1_EXP_PT_0 : STD_LOGIC; 
  signal EXP1_EXP_PT_1 : STD_LOGIC; 
  signal EXP2_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal EXP2_EXP_PT_0 : STD_LOGIC; 
  signal EXP2_EXP_PT_1 : STD_LOGIC; 
  signal EXP2_EXP_PT_2 : STD_LOGIC; 
  signal EXP3_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal EXP3_EXP_PT_0 : STD_LOGIC; 
  signal EXP3_EXP_PT_1 : STD_LOGIC; 
  signal NlwInverterSignal_BRAKE_LOCKOUT_OBUF_D_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EMERGENCY_OBUF_D_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_BRAKE_RESET_OBUF_D_IN0 : STD_LOGIC; 
begin
  SPARE3_IBUF_2 : X_BUF
    port map (
      I => SPARE3,
      O => SPARE3_IBUF
    );
  SPARE2_IBUF_3 : X_BUF
    port map (
      I => SPARE2,
      O => SPARE2_IBUF
    );
  SPARE1_IBUF_4 : X_BUF
    port map (
      I => SPARE1,
      O => SPARE1_IBUF
    );
  OVERRIDE_IBUF_5 : X_BUF
    port map (
      I => OVERRIDE,
      O => OVERRIDE_IBUF
    );
  HORIZON_STOP_IBUF_6 : X_BUF
    port map (
      I => HORIZON_STOP,
      O => HORIZON_STOP_IBUF
    );
  HA_STOP_IBUF_7 : X_BUF
    port map (
      I => HA_STOP,
      O => HA_STOP_IBUF
    );
  HA_EMERG_IBUF_8 : X_BUF
    port map (
      I => HA_EMERG,
      O => HA_EMERG_IBUF
    );
  DEC_STOP_IBUF_9 : X_BUF
    port map (
      I => DEC_STOP,
      O => DEC_STOP_IBUF
    );
  DEC_EMERG_IBUF_10 : X_BUF
    port map (
      I => DEC_EMERG,
      O => DEC_EMERG_IBUF
    );
  W_THERM_DIS_IBUF_11 : X_BUF
    port map (
      I => W_THERM_DIS,
      O => W_THERM_DIS_IBUF
    );
  S_THERM_DIS_IBUF_12 : X_BUF
    port map (
      I => S_THERM_DIS,
      O => S_THERM_DIS_IBUF
    );
  N_THERM_DIS_IBUF_13 : X_BUF
    port map (
      I => N_THERM_DIS,
      O => N_THERM_DIS_IBUF
    );
  E_THERM_DIS_IBUF_14 : X_BUF
    port map (
      I => E_THERM_DIS,
      O => E_THERM_DIS_IBUF
    );
  DM3_THERM_DIS_IBUF_15 : X_BUF
    port map (
      I => DM3_THERM_DIS,
      O => DM3_THERM_DIS_IBUF
    );
  DM2_THERM_DIS_IBUF_16 : X_BUF
    port map (
      I => DM2_THERM_DIS,
      O => DM2_THERM_DIS_IBUF
    );
  DM1_THERM_DIS_IBUF_17 : X_BUF
    port map (
      I => DM1_THERM_DIS,
      O => DM1_THERM_DIS_IBUF
    );
  WATCHDOG_TIMER_IBUF_18 : X_BUF
    port map (
      I => WATCHDOG_TIMER,
      O => WATCHDOG_TIMER_IBUF
    );
  SPARE6_IBUF_19 : X_BUF
    port map (
      I => SPARE6,
      O => SPARE6_IBUF
    );
  SPARE5_IBUF_20 : X_BUF
    port map (
      I => SPARE5,
      O => SPARE5_IBUF
    );
  SPARE4_IBUF_21 : X_BUF
    port map (
      I => SPARE4,
      O => SPARE4_IBUF
    );
  MOTOR_CNTR_ERROR_IBUF_22 : X_BUF
    port map (
      I => MOTOR_CNTR_ERROR,
      O => MOTOR_CNTR_ERROR_IBUF
    );
  EMERG_STOP_IBUF_23 : X_BUF
    port map (
      I => EMERG_STOP,
      O => EMERG_STOP_IBUF
    );
  TCS_LOCKOUT_IBUF_24 : X_BUF
    port map (
      I => TCS_LOCKOUT,
      O => TCS_LOCKOUT_IBUF
    );
  SPARE9_IBUF_25 : X_BUF
    port map (
      I => SPARE9,
      O => SPARE9_IBUF
    );
  SPARE10_IBUF_26 : X_BUF
    port map (
      I => SPARE10,
      O => SPARE10_IBUF
    );
  LOCKOUT_KSWTCH_IBUF_27 : X_BUF
    port map (
      I => LOCKOUT_KSWTCH,
      O => LOCKOUT_KSWTCH_IBUF
    );
  BRAKE_LOCKOUT_28 : X_BUF
    port map (
      I => BRAKE_LOCKOUT_OBUF_Q,
      O => BRAKE_LOCKOUT
    );
  EMERGENCY_29 : X_BUF
    port map (
      I => EMERGENCY_OBUF_Q,
      O => EMERGENCY
    );
  BRAKE_RESET_30 : X_BUF
    port map (
      I => BRAKE_RESET_OBUF,
      O => BRAKE_RESET
    );
  BRAKE_LOCKOUT_OBUF_Q_31 : X_BUF
    port map (
      I => BRAKE_LOCKOUT_OBUF_Q_0,
      O => BRAKE_LOCKOUT_OBUF_Q
    );
  BRAKE_LOCKOUT_OBUF_Q_32 : X_BUF
    port map (
      I => BRAKE_LOCKOUT_OBUF_D,
      O => BRAKE_LOCKOUT_OBUF_Q_0
    );
  BRAKE_LOCKOUT_OBUF_D_33 : X_XOR2
    port map (
      I0 => NlwInverterSignal_BRAKE_LOCKOUT_OBUF_D_IN0,
      I1 => BRAKE_LOCKOUT_OBUF_D2,
      O => BRAKE_LOCKOUT_OBUF_D
    );
  BRAKE_LOCKOUT_OBUF_D1_34 : X_ZERO
    port map (
      O => BRAKE_LOCKOUT_OBUF_D1
    );
  BRAKE_LOCKOUT_OBUF_D2_35 : X_AND4
    port map (
      I0 => TCS_LOCKOUT_IBUF,
      I1 => SPARE9_IBUF,
      I2 => SPARE10_IBUF,
      I3 => LOCKOUT_KSWTCH_IBUF,
      O => BRAKE_LOCKOUT_OBUF_D2
    );
  EMERGENCY_OBUF_Q_36 : X_BUF
    port map (
      I => EMERGENCY_OBUF_Q_1,
      O => EMERGENCY_OBUF_Q
    );
  EMERGENCY_OBUF_Q_37 : X_BUF
    port map (
      I => EMERGENCY_OBUF_D,
      O => EMERGENCY_OBUF_Q_1
    );
  EMERGENCY_OBUF_D_38 : X_XOR2
    port map (
      I0 => NlwInverterSignal_EMERGENCY_OBUF_D_IN0,
      I1 => EMERGENCY_OBUF_D2,
      O => EMERGENCY_OBUF_D
    );
  EMERGENCY_OBUF_D1_39 : X_ZERO
    port map (
      O => EMERGENCY_OBUF_D1
    );
  EMERGENCY_OBUF_D2_PT_0_40 : X_AND2
    port map (
      I0 => EXP0_EXP,
      I1 => EXP0_EXP,
      O => EMERGENCY_OBUF_D2_PT_0
    );
  EMERGENCY_OBUF_D2_PT_1_41 : X_AND2
    port map (
      I0 => EXP1_EXP,
      I1 => EXP1_EXP,
      O => EMERGENCY_OBUF_D2_PT_1
    );
  EMERGENCY_OBUF_D2_PT_2_42 : X_AND16
    port map (
      I0 => SPARE3_IBUF,
      I1 => W_THERM_DIS_IBUF,
      I2 => S_THERM_DIS_IBUF,
      I3 => N_THERM_DIS_IBUF,
      I4 => E_THERM_DIS_IBUF,
      I5 => DM3_THERM_DIS_IBUF,
      I6 => DM2_THERM_DIS_IBUF,
      I7 => DM1_THERM_DIS_IBUF,
      I8 => WATCHDOG_TIMER_IBUF,
      I9 => SPARE6_IBUF,
      I10 => SPARE5_IBUF,
      I11 => SPARE4_IBUF,
      I12 => MOTOR_CNTR_ERROR_IBUF,
      I13 => EMERG_STOP_IBUF,
      I14 => Vcc,
      I15 => Vcc,
      O => EMERGENCY_OBUF_D2_PT_2
    );
  Vcc_43 : X_ONE
    port map (
      O => Vcc
    );
  EMERGENCY_OBUF_D2_PT_3_44 : X_AND16
    port map (
      I0 => SPARE2_IBUF,
      I1 => W_THERM_DIS_IBUF,
      I2 => S_THERM_DIS_IBUF,
      I3 => N_THERM_DIS_IBUF,
      I4 => E_THERM_DIS_IBUF,
      I5 => DM3_THERM_DIS_IBUF,
      I6 => DM2_THERM_DIS_IBUF,
      I7 => DM1_THERM_DIS_IBUF,
      I8 => WATCHDOG_TIMER_IBUF,
      I9 => SPARE6_IBUF,
      I10 => SPARE5_IBUF,
      I11 => SPARE4_IBUF,
      I12 => MOTOR_CNTR_ERROR_IBUF,
      I13 => EMERG_STOP_IBUF,
      I14 => Vcc,
      I15 => Vcc,
      O => EMERGENCY_OBUF_D2_PT_3
    );
  EMERGENCY_OBUF_D2_PT_4_45 : X_AND16
    port map (
      I0 => SPARE1_IBUF,
      I1 => W_THERM_DIS_IBUF,
      I2 => S_THERM_DIS_IBUF,
      I3 => N_THERM_DIS_IBUF,
      I4 => E_THERM_DIS_IBUF,
      I5 => DM3_THERM_DIS_IBUF,
      I6 => DM2_THERM_DIS_IBUF,
      I7 => DM1_THERM_DIS_IBUF,
      I8 => WATCHDOG_TIMER_IBUF,
      I9 => SPARE6_IBUF,
      I10 => SPARE5_IBUF,
      I11 => SPARE4_IBUF,
      I12 => MOTOR_CNTR_ERROR_IBUF,
      I13 => EMERG_STOP_IBUF,
      I14 => Vcc,
      I15 => Vcc,
      O => EMERGENCY_OBUF_D2_PT_4
    );
  EMERGENCY_OBUF_D2_PT_5_46 : X_AND16
    port map (
      I0 => OVERRIDE_IBUF,
      I1 => W_THERM_DIS_IBUF,
      I2 => S_THERM_DIS_IBUF,
      I3 => N_THERM_DIS_IBUF,
      I4 => E_THERM_DIS_IBUF,
      I5 => DM3_THERM_DIS_IBUF,
      I6 => DM2_THERM_DIS_IBUF,
      I7 => DM1_THERM_DIS_IBUF,
      I8 => WATCHDOG_TIMER_IBUF,
      I9 => SPARE6_IBUF,
      I10 => SPARE5_IBUF,
      I11 => SPARE4_IBUF,
      I12 => MOTOR_CNTR_ERROR_IBUF,
      I13 => EMERG_STOP_IBUF,
      I14 => Vcc,
      I15 => Vcc,
      O => EMERGENCY_OBUF_D2_PT_5
    );
  EMERGENCY_OBUF_D2_PT_6_47 : X_AND16
    port map (
      I0 => HORIZON_STOP_IBUF,
      I1 => W_THERM_DIS_IBUF,
      I2 => S_THERM_DIS_IBUF,
      I3 => N_THERM_DIS_IBUF,
      I4 => E_THERM_DIS_IBUF,
      I5 => DM3_THERM_DIS_IBUF,
      I6 => DM2_THERM_DIS_IBUF,
      I7 => DM1_THERM_DIS_IBUF,
      I8 => WATCHDOG_TIMER_IBUF,
      I9 => SPARE6_IBUF,
      I10 => SPARE5_IBUF,
      I11 => SPARE4_IBUF,
      I12 => MOTOR_CNTR_ERROR_IBUF,
      I13 => EMERG_STOP_IBUF,
      I14 => Vcc,
      I15 => Vcc,
      O => EMERGENCY_OBUF_D2_PT_6
    );
  EMERGENCY_OBUF_D2_48 : X_OR7
    port map (
      I0 => EMERGENCY_OBUF_D2_PT_0,
      I1 => EMERGENCY_OBUF_D2_PT_1,
      I2 => EMERGENCY_OBUF_D2_PT_2,
      I3 => EMERGENCY_OBUF_D2_PT_3,
      I4 => EMERGENCY_OBUF_D2_PT_4,
      I5 => EMERGENCY_OBUF_D2_PT_5,
      I6 => EMERGENCY_OBUF_D2_PT_6,
      O => EMERGENCY_OBUF_D2
    );
  BRAKE_RESET_OBUF_49 : X_BUF
    port map (
      I => BRAKE_RESET_OBUF_Q,
      O => BRAKE_RESET_OBUF
    );
  BRAKE_RESET_OBUF_Q_50 : X_BUF
    port map (
      I => BRAKE_RESET_OBUF_D,
      O => BRAKE_RESET_OBUF_Q
    );
  BRAKE_RESET_OBUF_D_51 : X_XOR2
    port map (
      I0 => NlwInverterSignal_BRAKE_RESET_OBUF_D_IN0,
      I1 => BRAKE_RESET_OBUF_D2,
      O => BRAKE_RESET_OBUF_D
    );
  BRAKE_RESET_OBUF_D1_52 : X_ZERO
    port map (
      O => BRAKE_RESET_OBUF_D1
    );
  BRAKE_RESET_OBUF_D2_PT_0_53 : X_AND2
    port map (
      I0 => EXP2_EXP,
      I1 => EXP2_EXP,
      O => BRAKE_RESET_OBUF_D2_PT_0
    );
  BRAKE_RESET_OBUF_D2_PT_1_54 : X_AND2
    port map (
      I0 => EXP3_EXP,
      I1 => EXP3_EXP,
      O => BRAKE_RESET_OBUF_D2_PT_1
    );
  BRAKE_RESET_OBUF_D2_PT_2_55 : X_AND4
    port map (
      I0 => TCS_LOCKOUT_IBUF,
      I1 => SPARE9_IBUF,
      I2 => SPARE10_IBUF,
      I3 => LOCKOUT_KSWTCH_IBUF,
      O => BRAKE_RESET_OBUF_D2_PT_2
    );
  BRAKE_RESET_OBUF_D2_PT_3_56 : X_AND16
    port map (
      I0 => SPARE3_IBUF,
      I1 => W_THERM_DIS_IBUF,
      I2 => S_THERM_DIS_IBUF,
      I3 => N_THERM_DIS_IBUF,
      I4 => E_THERM_DIS_IBUF,
      I5 => DM3_THERM_DIS_IBUF,
      I6 => DM2_THERM_DIS_IBUF,
      I7 => DM1_THERM_DIS_IBUF,
      I8 => WATCHDOG_TIMER_IBUF,
      I9 => SPARE6_IBUF,
      I10 => SPARE5_IBUF,
      I11 => SPARE4_IBUF,
      I12 => MOTOR_CNTR_ERROR_IBUF,
      I13 => EMERG_STOP_IBUF,
      I14 => Vcc,
      I15 => Vcc,
      O => BRAKE_RESET_OBUF_D2_PT_3
    );
  BRAKE_RESET_OBUF_D2_PT_4_57 : X_AND16
    port map (
      I0 => SPARE2_IBUF,
      I1 => W_THERM_DIS_IBUF,
      I2 => S_THERM_DIS_IBUF,
      I3 => N_THERM_DIS_IBUF,
      I4 => E_THERM_DIS_IBUF,
      I5 => DM3_THERM_DIS_IBUF,
      I6 => DM2_THERM_DIS_IBUF,
      I7 => DM1_THERM_DIS_IBUF,
      I8 => WATCHDOG_TIMER_IBUF,
      I9 => SPARE6_IBUF,
      I10 => SPARE5_IBUF,
      I11 => SPARE4_IBUF,
      I12 => MOTOR_CNTR_ERROR_IBUF,
      I13 => EMERG_STOP_IBUF,
      I14 => Vcc,
      I15 => Vcc,
      O => BRAKE_RESET_OBUF_D2_PT_4
    );
  BRAKE_RESET_OBUF_D2_PT_5_58 : X_AND16
    port map (
      I0 => SPARE1_IBUF,
      I1 => W_THERM_DIS_IBUF,
      I2 => S_THERM_DIS_IBUF,
      I3 => N_THERM_DIS_IBUF,
      I4 => E_THERM_DIS_IBUF,
      I5 => DM3_THERM_DIS_IBUF,
      I6 => DM2_THERM_DIS_IBUF,
      I7 => DM1_THERM_DIS_IBUF,
      I8 => WATCHDOG_TIMER_IBUF,
      I9 => SPARE6_IBUF,
      I10 => SPARE5_IBUF,
      I11 => SPARE4_IBUF,
      I12 => MOTOR_CNTR_ERROR_IBUF,
      I13 => EMERG_STOP_IBUF,
      I14 => Vcc,
      I15 => Vcc,
      O => BRAKE_RESET_OBUF_D2_PT_5
    );
  BRAKE_RESET_OBUF_D2_PT_6_59 : X_AND16
    port map (
      I0 => OVERRIDE_IBUF,
      I1 => W_THERM_DIS_IBUF,
      I2 => S_THERM_DIS_IBUF,
      I3 => N_THERM_DIS_IBUF,
      I4 => E_THERM_DIS_IBUF,
      I5 => DM3_THERM_DIS_IBUF,
      I6 => DM2_THERM_DIS_IBUF,
      I7 => DM1_THERM_DIS_IBUF,
      I8 => WATCHDOG_TIMER_IBUF,
      I9 => SPARE6_IBUF,
      I10 => SPARE5_IBUF,
      I11 => SPARE4_IBUF,
      I12 => MOTOR_CNTR_ERROR_IBUF,
      I13 => EMERG_STOP_IBUF,
      I14 => Vcc,
      I15 => Vcc,
      O => BRAKE_RESET_OBUF_D2_PT_6
    );
  BRAKE_RESET_OBUF_D2_60 : X_OR7
    port map (
      I0 => BRAKE_RESET_OBUF_D2_PT_0,
      I1 => BRAKE_RESET_OBUF_D2_PT_1,
      I2 => BRAKE_RESET_OBUF_D2_PT_2,
      I3 => BRAKE_RESET_OBUF_D2_PT_3,
      I4 => BRAKE_RESET_OBUF_D2_PT_4,
      I5 => BRAKE_RESET_OBUF_D2_PT_5,
      I6 => BRAKE_RESET_OBUF_D2_PT_6,
      O => BRAKE_RESET_OBUF_D2
    );
  EXP0_EXP_61 : X_BUF
    port map (
      I => EXP0_EXP_tsimrenamed_net_Q,
      O => EXP0_EXP
    );
  EXP0_EXP_PT_0_62 : X_AND16
    port map (
      I0 => HA_STOP_IBUF,
      I1 => W_THERM_DIS_IBUF,
      I2 => S_THERM_DIS_IBUF,
      I3 => N_THERM_DIS_IBUF,
      I4 => E_THERM_DIS_IBUF,
      I5 => DM3_THERM_DIS_IBUF,
      I6 => DM2_THERM_DIS_IBUF,
      I7 => DM1_THERM_DIS_IBUF,
      I8 => WATCHDOG_TIMER_IBUF,
      I9 => SPARE6_IBUF,
      I10 => SPARE5_IBUF,
      I11 => SPARE4_IBUF,
      I12 => MOTOR_CNTR_ERROR_IBUF,
      I13 => EMERG_STOP_IBUF,
      I14 => Vcc,
      I15 => Vcc,
      O => EXP0_EXP_PT_0
    );
  EXP0_EXP_PT_1_63 : X_AND16
    port map (
      I0 => HA_EMERG_IBUF,
      I1 => W_THERM_DIS_IBUF,
      I2 => S_THERM_DIS_IBUF,
      I3 => N_THERM_DIS_IBUF,
      I4 => E_THERM_DIS_IBUF,
      I5 => DM3_THERM_DIS_IBUF,
      I6 => DM2_THERM_DIS_IBUF,
      I7 => DM1_THERM_DIS_IBUF,
      I8 => WATCHDOG_TIMER_IBUF,
      I9 => SPARE6_IBUF,
      I10 => SPARE5_IBUF,
      I11 => SPARE4_IBUF,
      I12 => MOTOR_CNTR_ERROR_IBUF,
      I13 => EMERG_STOP_IBUF,
      I14 => Vcc,
      I15 => Vcc,
      O => EXP0_EXP_PT_1
    );
  EXP0_EXP_tsimrenamed_net_Q_64 : X_OR2
    port map (
      I0 => EXP0_EXP_PT_0,
      I1 => EXP0_EXP_PT_1,
      O => EXP0_EXP_tsimrenamed_net_Q
    );
  EXP1_EXP_65 : X_BUF
    port map (
      I => EXP1_EXP_tsimrenamed_net_Q,
      O => EXP1_EXP
    );
  EXP1_EXP_PT_0_66 : X_AND16
    port map (
      I0 => DEC_STOP_IBUF,
      I1 => W_THERM_DIS_IBUF,
      I2 => S_THERM_DIS_IBUF,
      I3 => N_THERM_DIS_IBUF,
      I4 => E_THERM_DIS_IBUF,
      I5 => DM3_THERM_DIS_IBUF,
      I6 => DM2_THERM_DIS_IBUF,
      I7 => DM1_THERM_DIS_IBUF,
      I8 => WATCHDOG_TIMER_IBUF,
      I9 => SPARE6_IBUF,
      I10 => SPARE5_IBUF,
      I11 => SPARE4_IBUF,
      I12 => MOTOR_CNTR_ERROR_IBUF,
      I13 => EMERG_STOP_IBUF,
      I14 => Vcc,
      I15 => Vcc,
      O => EXP1_EXP_PT_0
    );
  EXP1_EXP_PT_1_67 : X_AND16
    port map (
      I0 => DEC_EMERG_IBUF,
      I1 => W_THERM_DIS_IBUF,
      I2 => S_THERM_DIS_IBUF,
      I3 => N_THERM_DIS_IBUF,
      I4 => E_THERM_DIS_IBUF,
      I5 => DM3_THERM_DIS_IBUF,
      I6 => DM2_THERM_DIS_IBUF,
      I7 => DM1_THERM_DIS_IBUF,
      I8 => WATCHDOG_TIMER_IBUF,
      I9 => SPARE6_IBUF,
      I10 => SPARE5_IBUF,
      I11 => SPARE4_IBUF,
      I12 => MOTOR_CNTR_ERROR_IBUF,
      I13 => EMERG_STOP_IBUF,
      I14 => Vcc,
      I15 => Vcc,
      O => EXP1_EXP_PT_1
    );
  EXP1_EXP_tsimrenamed_net_Q_68 : X_OR2
    port map (
      I0 => EXP1_EXP_PT_0,
      I1 => EXP1_EXP_PT_1,
      O => EXP1_EXP_tsimrenamed_net_Q
    );
  EXP2_EXP_69 : X_BUF
    port map (
      I => EXP2_EXP_tsimrenamed_net_Q,
      O => EXP2_EXP
    );
  EXP2_EXP_PT_0_70 : X_AND16
    port map (
      I0 => HORIZON_STOP_IBUF,
      I1 => W_THERM_DIS_IBUF,
      I2 => S_THERM_DIS_IBUF,
      I3 => N_THERM_DIS_IBUF,
      I4 => E_THERM_DIS_IBUF,
      I5 => DM3_THERM_DIS_IBUF,
      I6 => DM2_THERM_DIS_IBUF,
      I7 => DM1_THERM_DIS_IBUF,
      I8 => WATCHDOG_TIMER_IBUF,
      I9 => SPARE6_IBUF,
      I10 => SPARE5_IBUF,
      I11 => SPARE4_IBUF,
      I12 => MOTOR_CNTR_ERROR_IBUF,
      I13 => EMERG_STOP_IBUF,
      I14 => Vcc,
      I15 => Vcc,
      O => EXP2_EXP_PT_0
    );
  EXP2_EXP_PT_1_71 : X_AND16
    port map (
      I0 => HA_STOP_IBUF,
      I1 => W_THERM_DIS_IBUF,
      I2 => S_THERM_DIS_IBUF,
      I3 => N_THERM_DIS_IBUF,
      I4 => E_THERM_DIS_IBUF,
      I5 => DM3_THERM_DIS_IBUF,
      I6 => DM2_THERM_DIS_IBUF,
      I7 => DM1_THERM_DIS_IBUF,
      I8 => WATCHDOG_TIMER_IBUF,
      I9 => SPARE6_IBUF,
      I10 => SPARE5_IBUF,
      I11 => SPARE4_IBUF,
      I12 => MOTOR_CNTR_ERROR_IBUF,
      I13 => EMERG_STOP_IBUF,
      I14 => Vcc,
      I15 => Vcc,
      O => EXP2_EXP_PT_1
    );
  EXP2_EXP_PT_2_72 : X_AND16
    port map (
      I0 => HA_EMERG_IBUF,
      I1 => W_THERM_DIS_IBUF,
      I2 => S_THERM_DIS_IBUF,
      I3 => N_THERM_DIS_IBUF,
      I4 => E_THERM_DIS_IBUF,
      I5 => DM3_THERM_DIS_IBUF,
      I6 => DM2_THERM_DIS_IBUF,
      I7 => DM1_THERM_DIS_IBUF,
      I8 => WATCHDOG_TIMER_IBUF,
      I9 => SPARE6_IBUF,
      I10 => SPARE5_IBUF,
      I11 => SPARE4_IBUF,
      I12 => MOTOR_CNTR_ERROR_IBUF,
      I13 => EMERG_STOP_IBUF,
      I14 => Vcc,
      I15 => Vcc,
      O => EXP2_EXP_PT_2
    );
  EXP2_EXP_tsimrenamed_net_Q_73 : X_OR3
    port map (
      I0 => EXP2_EXP_PT_0,
      I1 => EXP2_EXP_PT_1,
      I2 => EXP2_EXP_PT_2,
      O => EXP2_EXP_tsimrenamed_net_Q
    );
  EXP3_EXP_74 : X_BUF
    port map (
      I => EXP3_EXP_tsimrenamed_net_Q,
      O => EXP3_EXP
    );
  EXP3_EXP_PT_0_75 : X_AND16
    port map (
      I0 => DEC_STOP_IBUF,
      I1 => W_THERM_DIS_IBUF,
      I2 => S_THERM_DIS_IBUF,
      I3 => N_THERM_DIS_IBUF,
      I4 => E_THERM_DIS_IBUF,
      I5 => DM3_THERM_DIS_IBUF,
      I6 => DM2_THERM_DIS_IBUF,
      I7 => DM1_THERM_DIS_IBUF,
      I8 => WATCHDOG_TIMER_IBUF,
      I9 => SPARE6_IBUF,
      I10 => SPARE5_IBUF,
      I11 => SPARE4_IBUF,
      I12 => MOTOR_CNTR_ERROR_IBUF,
      I13 => EMERG_STOP_IBUF,
      I14 => Vcc,
      I15 => Vcc,
      O => EXP3_EXP_PT_0
    );
  EXP3_EXP_PT_1_76 : X_AND16
    port map (
      I0 => DEC_EMERG_IBUF,
      I1 => W_THERM_DIS_IBUF,
      I2 => S_THERM_DIS_IBUF,
      I3 => N_THERM_DIS_IBUF,
      I4 => E_THERM_DIS_IBUF,
      I5 => DM3_THERM_DIS_IBUF,
      I6 => DM2_THERM_DIS_IBUF,
      I7 => DM1_THERM_DIS_IBUF,
      I8 => WATCHDOG_TIMER_IBUF,
      I9 => SPARE6_IBUF,
      I10 => SPARE5_IBUF,
      I11 => SPARE4_IBUF,
      I12 => MOTOR_CNTR_ERROR_IBUF,
      I13 => EMERG_STOP_IBUF,
      I14 => Vcc,
      I15 => Vcc,
      O => EXP3_EXP_PT_1
    );
  EXP3_EXP_tsimrenamed_net_Q_77 : X_OR2
    port map (
      I0 => EXP3_EXP_PT_0,
      I1 => EXP3_EXP_PT_1,
      O => EXP3_EXP_tsimrenamed_net_Q
    );
  NlwInverterBlock_BRAKE_LOCKOUT_OBUF_D_IN0 : X_INV
    port map (
      I => BRAKE_LOCKOUT_OBUF_D1,
      O => NlwInverterSignal_BRAKE_LOCKOUT_OBUF_D_IN0
    );
  NlwInverterBlock_EMERGENCY_OBUF_D_IN0 : X_INV
    port map (
      I => EMERGENCY_OBUF_D1,
      O => NlwInverterSignal_EMERGENCY_OBUF_D_IN0
    );
  NlwInverterBlock_BRAKE_RESET_OBUF_D_IN0 : X_INV
    port map (
      I => BRAKE_RESET_OBUF_D1,
      O => NlwInverterSignal_BRAKE_RESET_OBUF_D_IN0
    );

end Structure;