Timing Report

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Design Name	Logic
Device, Speed (SpeedFile Version)	XC9572, -15 (3.0)
Date Created	Mon Jul 31 18:52:27 2006
Created By	Timing Report Generator: version I.32
Copyright	Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved.

Summary

Notes and Warnings
Note: This design contains no timing constraints.
Note: A default set of constraints using a delay of 0.000ns will be used for analysis.

Performance Summary
Min. Clock Period	18.000 ns.
Max. Clock Frequency (fSYSTEM)	55.556 MHz.
Limited by Cycle Time for CLK_IN
Clock to Setup (tCYC)	18.000 ns.
Pad to Pad Delay (tPD)	15.000 ns.
Setup to Clock at the Pad (tSU)	8.000 ns.
Clock Pad to Output Pad Delay (tCO)	25.000 ns.

Timing Constraints

Constraint Name	Delay (ns)	Paths	Paths Failing
TS1000	0.0	0	0
TS1001	0.0	0	0
TS1002	0.0	0	0
TS1003	0.0	0	0
TS1004	0.0	0	0
TS1005	0.0	0	0
TS1006	0.0	0	0
TS1007	0.0	0	0
TS1008	0.0	0	0
TS1009	0.0	0	0
TS1010	0.0	0	0
TS1011	0.0	0	0
TS1012	0.0	0	0
TS1013	0.0	0	0
TS1014	0.0	0	0
TS1015	0.0	0	0
TS1016	0.0	0	0
TS1017	0.0	0	0
TS1018	0.0	0	0
TS1019	0.0	0	0
TS1020	0.0	0	0
TS1021	0.0	0	0
TS1022	0.0	0	0
TS1023	0.0	0	0
TS1024	0.0	0	0
TS1025	0.0	0	0
TS1026	0.0	0	0
TS1027	0.0	0	0
TS1028	0.0	0	0
TS1029	0.0	0	0
AUTO_TS_F2F	18.0	1	1
AUTO_TS_P2P	25.0	14	14
AUTO_TS_P2F	11.0	2	2
AUTO_TS_F2P	22.0	8	8

Constraint: TS1000

**Description: PERIOD:PERIOD_WEST_OC_LATCH_OBUF.CLKF:0.000 nS**
Path	Requirement (ns)	Delay (ns)	Slack (ns)

Constraint: TS1001

**Description: PERIOD:PERIOD_WATCHDOG_TIMER_LATCH_OBUF.CLKF:0.000 nS**
Path	Requirement (ns)	Delay (ns)	Slack (ns)

Constraint: TS1002

**Description: PERIOD:PERIOD_SPARE6_LATCH_OBUF.CLKF:0.000 nS**
Path	Requirement (ns)	Delay (ns)	Slack (ns)

Constraint: TS1003

**Description: PERIOD:PERIOD_SPARE5_LATCH_OBUF.CLKF:0.000 nS**
Path	Requirement (ns)	Delay (ns)	Slack (ns)

Constraint: TS1004

**Description: PERIOD:PERIOD_SPARE4_LATCH_OBUF.CLKF:0.000 nS**
Path	Requirement (ns)	Delay (ns)	Slack (ns)

Constraint: TS1005

**Description: PERIOD:PERIOD_SPARE3_LATCH_OBUF.CLKF:0.000 nS**
Path	Requirement (ns)	Delay (ns)	Slack (ns)

Constraint: TS1006

**Description: PERIOD:PERIOD_SPARE2_LATCH_OBUF.CLKF:0.000 nS**
Path	Requirement (ns)	Delay (ns)	Slack (ns)

Constraint: TS1007

**Description: PERIOD:PERIOD_SPARE1_LATCH_OBUF.CLKF:0.000 nS**
Path	Requirement (ns)	Delay (ns)	Slack (ns)

Constraint: TS1008

**Description: PERIOD:PERIOD_SOUTH_OC_LATCH_OBUF.CLKF:0.000 nS**
Path	Requirement (ns)	Delay (ns)	Slack (ns)

Constraint: TS1009

**Description: PERIOD:PERIOD_NORTH_OC_LATCH_OBUF.CLKF:0.000 nS**
Path	Requirement (ns)	Delay (ns)	Slack (ns)

Constraint: TS1010

**Description: PERIOD:PERIOD_HA_OS_LATCH_OBUF.CLKF:0.000 nS**
Path	Requirement (ns)	Delay (ns)	Slack (ns)

Constraint: TS1011

**Description: PERIOD:PERIOD_EMERG_STOP_LATCH_OBUF.CLKF:0.000 nS**
Path	Requirement (ns)	Delay (ns)	Slack (ns)

Constraint: TS1012

**Description: PERIOD:PERIOD_EAST_OC_LATCH_OBUF.CLKF:0.000 nS**
Path	Requirement (ns)	Delay (ns)	Slack (ns)

Constraint: TS1013

**Description: PERIOD:PERIOD_DOME3_OC_LATCH_OBUF.CLKF:0.000 nS**
Path	Requirement (ns)	Delay (ns)	Slack (ns)

Constraint: TS1014

**Description: PERIOD:PERIOD_DOME2_OC_LATCH_OBUF.CLKF:0.000 nS**
Path	Requirement (ns)	Delay (ns)	Slack (ns)

Constraint: TS1015

**Description: PERIOD:PERIOD_DOME1_OC_LATCH_OBUF.CLKF:0.000 nS**
Path	Requirement (ns)	Delay (ns)	Slack (ns)

Constraint: TS1016

**Description: PERIOD:PERIOD_DEC_OS_LATCH_OBUF.CLKF:0.000 nS**
Path	Requirement (ns)	Delay (ns)	Slack (ns)

Constraint: TS1017

**Description: PERIOD:PERIOD_TCS_LOCKOUT_LATCH_OBUF.CLKF:0.000 nS**
Path	Requirement (ns)	Delay (ns)	Slack (ns)

Constraint: TS1018

**Description: PERIOD:PERIOD_MTR_CNTR_ERR_LATCH_OBUF.CLKF:0.000 nS**
Path	Requirement (ns)	Delay (ns)	Slack (ns)

Constraint: TS1019

**Description: PERIOD:PERIOD_HP_STOP_LATCH_OBUF.CLKF:0.000 nS**
Path	Requirement (ns)	Delay (ns)	Slack (ns)

Constraint: TS1020

**Description: PERIOD:PERIOD_HORIZON_STOP_LATCH_OBUF.CLKF:0.000 nS**
Path	Requirement (ns)	Delay (ns)	Slack (ns)

Constraint: TS1021

**Description: PERIOD:PERIOD_HA_STOP_W_LATCH_OBUF.CLKF:0.000 nS**
Path	Requirement (ns)	Delay (ns)	Slack (ns)

Constraint: TS1022

**Description: PERIOD:PERIOD_HA_STOP_E_LATCH_OBUF.CLKF:0.000 nS**
Path	Requirement (ns)	Delay (ns)	Slack (ns)

Constraint: TS1023

**Description: PERIOD:PERIOD_HA_EMERG_W_LATCH_OBUF.CLKF:0.000 nS**
Path	Requirement (ns)	Delay (ns)	Slack (ns)

Constraint: TS1024

**Description: PERIOD:PERIOD_HA_EMERG_E_LATCH_OBUF.CLKF:0.000 nS**
Path	Requirement (ns)	Delay (ns)	Slack (ns)

Constraint: TS1025

**Description: PERIOD:PERIOD_DEC_STOP_S_LATCH_OBUF.CLKF:0.000 nS**
Path	Requirement (ns)	Delay (ns)	Slack (ns)

Constraint: TS1026

**Description: PERIOD:PERIOD_DEC_STOP_N_LATCH_OBUF.CLKF:0.000 nS**
Path	Requirement (ns)	Delay (ns)	Slack (ns)

Constraint: TS1027

**Description: PERIOD:PERIOD_DEC_EMERG_S_LATCH_OBUF.CLKF:0.000 nS**
Path	Requirement (ns)	Delay (ns)	Slack (ns)

Constraint: TS1028

**Description: PERIOD:PERIOD_DEC_EMERG_N_LATCH_OBUF.CLKF:0.000 nS**
Path	Requirement (ns)	Delay (ns)	Slack (ns)

Constraint: TS1029

**Description: PERIOD:PERIOD_CLK_IN:0.000 nS**
Path	Requirement (ns)	Delay (ns)	Slack (ns)

Constraint: AUTO_TS_F2F

**Description: MAXDELAY:FROM:FFS(*):TO:FFS(*):0.000 nS**
Path	Requirement (ns)	Delay (ns)	Slack (ns)
PinSignal_U67_Q.Q to PinSignal_U68_Q.D	0.000	18.000	-18.000

Constraint: AUTO_TS_P2P

**Description: MAXDELAY:FROM:PADS(*):TO:PADS(*):0.000 nS**
Path	Delay (ns)	Slack (ns)
CLK_IN to DOME_ENABLE	25.000	-25.000
CLK_IN to TEL_ENABLE	25.000	-25.000
CLK_IN to TOP_BRAKE_ENABLE_OUT	25.000	-25.000

Constraint: AUTO_TS_P2F

**Description: MAXDELAY:FROM:PADS(*):TO:FFS(*):0.000 nS**
Path	Requirement (ns)	Delay (ns)	Slack (ns)
TOP_LM_OVERRIDE_SWITCH to PinSignal_U67_Q.D	0.000	11.000	-11.000
CLK_IN to FCLKIO_0	0.000	3.000	-3.000

Constraint: AUTO_TS_F2P

**Description: MAXDELAY:FROM:FFS(*):TO:PADS(*):0.000 nS**
Path	Delay (ns)	Slack (ns)
PinSignal_U67_Q.Q to DOME_ENABLE	22.000	-22.000
PinSignal_U67_Q.Q to TEL_ENABLE	22.000	-22.000
PinSignal_U67_Q.Q to TOP_BRAKE_ENABLE_OUT	22.000	-22.000

Number of constraints not met: 4

Data Sheet Report

Maximum External Clock Speeds

Clock	fEXT (MHz)	Reason
CLK_IN	55.556	Limited by Cycle Time for CLK_IN

Setup/Hold Times for Clocks

**Setup/Hold Times for Clock CLK_IN**
Source Pad	Setup to clk (edge)	Hold to clk (edge)
TOP_LM_OVERRIDE_SWITCH	8.000	0.000

Clock to Pad Timing

**Clock CLK_IN to Pad**
Destination Pad	Clock (edge) to Pad
DOME_ENABLE	25.000
TEL_ENABLE	25.000
TOP_BRAKE_ENABLE_OUT	25.000
TOP_TCS_ENABLE	25.000

Clock to Setup Times for Clocks

**Clock to Setup for clock CLK_IN**
Source	Destination	Delay
PinSignal_U67_Q.Q	PinSignal_U68_Q.D	18.000

Pad to Pad List

Source Pad	Destination Pad	Delay
BRAKE_EN_IN	TEL_ENABLE	15.000
BRAKE_EN_IN	TOP_BRAKE_ENABLE_OUT	15.000
RESET	DOME_ENABLE	15.000
RESET	TEL_ENABLE	15.000
RESET	TOP_BRAKE_ENABLE_OUT	15.000
RESET	TOP_TCS_ENABLE	15.000
TOP_DOMECNTL_HANDPADDLE	DOME_ENABLE	15.000
TOP_DOMECNTL_SOFTWARE	DOME_ENABLE	15.000
TOP_TEL_ENABLE_SWITCH	TEL_ENABLE	15.000
TOP_TEL_ENABLE_SWITCH	TOP_BRAKE_ENABLE_OUT	15.000

Number of paths analyzed: 25
Number of Timing errors: 25
Analysis Completed: Mon Jul 31 18:52:27 2006