| Signal Name | Total Pterms | Total Inputs | Function Block | Macrocell | Power Mode | Slew Rate | Pin Number | Pin Type | Pin Use | Reg Init State |
|---|---|---|---|---|---|---|---|---|---|---|
| DEC_STOP_N_LATCH | 2 | 2 | FB1 | MC1 | STD | FAST | 4* | I/O | I/O | RESET |
| TEL_ENABLE | 2 | 5 | FB1 | MC2 | STD | FAST | 1* | I/O | O | |
| DEC_EMERG_S_LATCH | 2 | 2 | FB1 | MC3 | STD | FAST | 6* | I/O | I/O | RESET |
| TOP_TCS_ENABLE | 2 | 3 | FB1 | MC4 | STD | FAST | 7* | I/O | O | |
| DOME1_OC_LATCH | 2 | 2 | FB1 | MC5 | STD | FAST | 2* | I/O | I/O | SET |
| DOME2_OC_LATCH | 2 | 2 | FB1 | MC7 | STD | FAST | 11* | I/O | I/O | SET |
| DOME3_OC_LATCH | 2 | 2 | FB1 | MC10 | STD | FAST | 13* | I/O | I/O | SET |
| EAST_OC_LATCH | 2 | 2 | FB1 | MC13 | STD | FAST | 20* | I/O | I/O | SET |
| EMERG_STOP_LATCH | 2 | 2 | FB1 | MC16 | STD | FAST | 23* | I/O | I/O | SET |
| TOP_BRAKE_ENABLE_OUT | 2 | 5 | FB1 | MC18 | STD | FAST | 24* | I/O | O | |
| HA_EMERG_E_LATCH | 2 | 2 | FB2 | MC1 | STD | FAST | 63* | I/O | O | RESET |
| HA_EMERG_W_LATCH | 2 | 2 | FB2 | MC4 | STD | FAST | 68* | I/O | O | RESET |
| HA_OS_LATCH | 2 | 2 | FB2 | MC8 | STD | FAST | 72* | I/O | O | SET |
| HA_STOP_E_LATCH | 2 | 2 | FB2 | MC13 | STD | FAST | 80* | I/O | O | RESET |
| HA_STOP_W_LATCH | 2 | 2 | FB2 | MC16 | STD | FAST | 82* | I/O | O | RESET |
| PinSignal_U67_Q | 2 | 29 | FB2 | MC18 | STD | (b) | (b) | RESET | ||
| MTR_CNTR_ERR_LATCH | 2 | 2 | FB3 | MC2 | STD | FAST | 17* | I/O | I/O | RESET |
| NORTH_OC_LATCH | 2 | 2 | FB3 | MC4 | STD | FAST | 32* | I/O | I/O | SET |
| SOUTH_OC_LATCH | 2 | 2 | FB3 | MC6 | STD | FAST | 34* | I/O | I/O | SET |
| SPARE1_LATCH | 2 | 2 | FB3 | MC8 | STD | FAST | 21* | I/O | I/O | SET |
| SPARE2_LATCH | 2 | 2 | FB3 | MC10 | STD | FAST | 40* | I/O | I/O | SET |
| SPARE3_LATCH | 2 | 2 | FB3 | MC12 | STD | FAST | 41* | I/O | I/O | SET |
| SPARE4_LATCH | 2 | 2 | FB3 | MC14 | STD | FAST | 36* | I/O | I/O | SET |
| SPARE5_LATCH | 2 | 2 | FB3 | MC16 | STD | FAST | 45* | I/O | I/O | SET |
| SPARE6_LATCH | 2 | 2 | FB3 | MC17 | STD | FAST | 39* | I/O | O | SET |
| DEC_EMERG_N_LATCH | 2 | 2 | FB4 | MC2 | STD | FAST | 44* | I/O | I/O | RESET |
| DEC_STOP_S_LATCH | 2 | 2 | FB4 | MC4 | STD | FAST | 52* | I/O | I/O | RESET |
| DEC_OS_LATCH | 2 | 2 | FB4 | MC6 | STD | FAST | 54* | I/O | I/O | SET |
| HORIZON_STOP_LATCH | 2 | 2 | FB4 | MC8 | STD | FAST | 48* | I/O | I/O | RESET |
| HP_STOP_LATCH | 2 | 2 | FB4 | MC10 | STD | FAST | 57* | I/O | I/O | RESET |
| TCS_LOCKOUT_LATCH | 2 | 2 | FB4 | MC12 | STD | FAST | 58* | I/O | I/O | RESET |
| WATCHDOG_TIMER_LATCH | 2 | 2 | FB4 | MC14 | STD | FAST | 56* | I/O | I/O | SET |
| PinSignal_U68_Q | 1 | 1 | FB4 | MC15 | STD | 65 | I/O | I | RESET | |
| WEST_OC_LATCH | 2 | 2 | FB4 | MC16 | STD | FAST | 62* | I/O | I/O | SET |
| DOME_ENABLE | 3 | 5 | FB4 | MC17 | STD | FAST | 66* | I/O | O | |
| $OpTx$$OpTx$FX_DC$120_INV$125 | 1 | 3 | FB4 | MC18 | STD | (b) | (b) |