Equations

********** Mapped Logic **********

$OpTx$$OpTx$FX_DC$120_INV$125 <= (RESET AND PinSignal_U67_Q AND PinSignal_U68_Q.LFBK);

FDCPE_DEC_EMERG_N_LATCH: FDCPE port map (DEC_EMERG_N_LATCH,'0','0',DEC_EMERG_N_LATCH_CLR,DEC_EMERG_N_LATCH_PRE);
DEC_EMERG_N_LATCH_CLR <= (NOT DEC_EMERG_N AND NOT $OpTx$$OpTx$FX_DC$120_INV$125.LFBK);
DEC_EMERG_N_LATCH_PRE <= (DEC_EMERG_N AND NOT $OpTx$$OpTx$FX_DC$120_INV$125.LFBK);

FDCPE_DEC_EMERG_S_LATCH: FDCPE port map (DEC_EMERG_S_LATCH,'0','0',DEC_EMERG_S_LATCH_CLR,DEC_EMERG_S_LATCH_PRE);
DEC_EMERG_S_LATCH_CLR <= (NOT DEC_EMERG_S AND NOT $OpTx$$OpTx$FX_DC$120_INV$125);
DEC_EMERG_S_LATCH_PRE <= (DEC_EMERG_S AND NOT $OpTx$$OpTx$FX_DC$120_INV$125);

FDCPE_DEC_OS_LATCH: FDCPE port map (DEC_OS_LATCH,'1','0',DEC_OS_LATCH_CLR,DEC_OS_LATCH_PRE);
DEC_OS_LATCH_CLR <= (DEC_OS AND NOT $OpTx$$OpTx$FX_DC$120_INV$125.LFBK);
DEC_OS_LATCH_PRE <= (NOT DEC_OS AND NOT $OpTx$$OpTx$FX_DC$120_INV$125.LFBK);

FDCPE_DEC_STOP_N_LATCH: FDCPE port map (DEC_STOP_N_LATCH,'0','0',DEC_STOP_N_LATCH_CLR,DEC_STOP_N_LATCH_PRE);
DEC_STOP_N_LATCH_CLR <= (NOT DEC_STOP_N AND NOT $OpTx$$OpTx$FX_DC$120_INV$125);
DEC_STOP_N_LATCH_PRE <= (DEC_STOP_N AND NOT $OpTx$$OpTx$FX_DC$120_INV$125);

FDCPE_DEC_STOP_S_LATCH: FDCPE port map (DEC_STOP_S_LATCH,'0','0',DEC_STOP_S_LATCH_CLR,DEC_STOP_S_LATCH_PRE);
DEC_STOP_S_LATCH_CLR <= (NOT DEC_STOP_S AND NOT $OpTx$$OpTx$FX_DC$120_INV$125.LFBK);
DEC_STOP_S_LATCH_PRE <= (DEC_STOP_S AND NOT $OpTx$$OpTx$FX_DC$120_INV$125.LFBK);

FDCPE_DOME1_OC_LATCH: FDCPE port map (DOME1_OC_LATCH,'1','0',DOME1_OC_LATCH_CLR,DOME1_OC_LATCH_PRE);
DOME1_OC_LATCH_CLR <= (DOME1_OC AND NOT $OpTx$$OpTx$FX_DC$120_INV$125);
DOME1_OC_LATCH_PRE <= (NOT DOME1_OC AND NOT $OpTx$$OpTx$FX_DC$120_INV$125);

FDCPE_DOME2_OC_LATCH: FDCPE port map (DOME2_OC_LATCH,'1','0',DOME2_OC_LATCH_CLR,DOME2_OC_LATCH_PRE);
DOME2_OC_LATCH_CLR <= (DOME2_OC AND NOT $OpTx$$OpTx$FX_DC$120_INV$125);
DOME2_OC_LATCH_PRE <= (NOT DOME2_OC AND NOT $OpTx$$OpTx$FX_DC$120_INV$125);

FDCPE_DOME3_OC_LATCH: FDCPE port map (DOME3_OC_LATCH,'1','0',DOME3_OC_LATCH_CLR,DOME3_OC_LATCH_PRE);
DOME3_OC_LATCH_CLR <= (DOME3_OC AND NOT $OpTx$$OpTx$FX_DC$120_INV$125);
DOME3_OC_LATCH_PRE <= (NOT DOME3_OC AND NOT $OpTx$$OpTx$FX_DC$120_INV$125);

DOME_ENABLE <= ((NOT RESET)
OR (PinSignal_U67_Q AND PinSignal_U68_Q.LFBK)
OR (NOT TOP_DOMECNTL_SOFTWARE AND NOT TOP_DOMECNTL_HANDPADDLE));

FDCPE_EAST_OC_LATCH: FDCPE port map (EAST_OC_LATCH,'1','0',EAST_OC_LATCH_CLR,EAST_OC_LATCH_PRE);
EAST_OC_LATCH_CLR <= (EAST_OC AND NOT $OpTx$$OpTx$FX_DC$120_INV$125);
EAST_OC_LATCH_PRE <= (NOT EAST_OC AND NOT $OpTx$$OpTx$FX_DC$120_INV$125);

FDCPE_EMERG_STOP_LATCH: FDCPE port map (EMERG_STOP_LATCH,'1','0',EMERG_STOP_LATCH_CLR,EMERG_STOP_LATCH_PRE);
EMERG_STOP_LATCH_CLR <= (EMERG_STOP AND NOT $OpTx$$OpTx$FX_DC$120_INV$125);
EMERG_STOP_LATCH_PRE <= (NOT EMERG_STOP AND NOT $OpTx$$OpTx$FX_DC$120_INV$125);

FDCPE_HA_EMERG_E_LATCH: FDCPE port map (HA_EMERG_E_LATCH,'0','0',HA_EMERG_E_LATCH_CLR,HA_EMERG_E_LATCH_PRE);
HA_EMERG_E_LATCH_CLR <= (NOT HA_EMERG_E AND NOT $OpTx$$OpTx$FX_DC$120_INV$125);
HA_EMERG_E_LATCH_PRE <= (HA_EMERG_E AND NOT $OpTx$$OpTx$FX_DC$120_INV$125);

FDCPE_HA_EMERG_W_LATCH: FDCPE port map (HA_EMERG_W_LATCH,'0','0',HA_EMERG_W_LATCH_CLR,HA_EMERG_W_LATCH_PRE);
HA_EMERG_W_LATCH_CLR <= (NOT HA_EMERG_W AND NOT $OpTx$$OpTx$FX_DC$120_INV$125);
HA_EMERG_W_LATCH_PRE <= (HA_EMERG_W AND NOT $OpTx$$OpTx$FX_DC$120_INV$125);

FDCPE_HA_OS_LATCH: FDCPE port map (HA_OS_LATCH,'1','0',HA_OS_LATCH_CLR,HA_OS_LATCH_PRE);
HA_OS_LATCH_CLR <= (HA_OS AND NOT $OpTx$$OpTx$FX_DC$120_INV$125);
HA_OS_LATCH_PRE <= (NOT HA_OS AND NOT $OpTx$$OpTx$FX_DC$120_INV$125);

FDCPE_HA_STOP_E_LATCH: FDCPE port map (HA_STOP_E_LATCH,'0','0',HA_STOP_E_LATCH_CLR,HA_STOP_E_LATCH_PRE);
HA_STOP_E_LATCH_CLR <= (NOT HA_STOP_E AND NOT $OpTx$$OpTx$FX_DC$120_INV$125);
HA_STOP_E_LATCH_PRE <= (HA_STOP_E AND NOT $OpTx$$OpTx$FX_DC$120_INV$125);

FDCPE_HA_STOP_W_LATCH: FDCPE port map (HA_STOP_W_LATCH,'0','0',HA_STOP_W_LATCH_CLR,HA_STOP_W_LATCH_PRE);
HA_STOP_W_LATCH_CLR <= (NOT HA_STOP_W AND NOT $OpTx$$OpTx$FX_DC$120_INV$125);
HA_STOP_W_LATCH_PRE <= (HA_STOP_W AND NOT $OpTx$$OpTx$FX_DC$120_INV$125);

FDCPE_HORIZON_STOP_LATCH: FDCPE port map (HORIZON_STOP_LATCH,'0','0',HORIZON_STOP_LATCH_CLR,HORIZON_STOP_LATCH_PRE);
HORIZON_STOP_LATCH_CLR <= (NOT HORIZON_STOP AND NOT $OpTx$$OpTx$FX_DC$120_INV$125.LFBK);
HORIZON_STOP_LATCH_PRE <= (HORIZON_STOP AND NOT $OpTx$$OpTx$FX_DC$120_INV$125.LFBK);

FDCPE_HP_STOP_LATCH: FDCPE port map (HP_STOP_LATCH,'0','0',HP_STOP_LATCH_CLR,HP_STOP_LATCH_PRE);
HP_STOP_LATCH_CLR <= (NOT HP_STOP AND NOT $OpTx$$OpTx$FX_DC$120_INV$125.LFBK);
HP_STOP_LATCH_PRE <= (HP_STOP AND NOT $OpTx$$OpTx$FX_DC$120_INV$125.LFBK);

FDCPE_MTR_CNTR_ERR_LATCH: FDCPE port map (MTR_CNTR_ERR_LATCH,'0','0',MTR_CNTR_ERR_LATCH_CLR,MTR_CNTR_ERR_LATCH_PRE);
MTR_CNTR_ERR_LATCH_CLR <= (NOT MTR_CNTR_ERR AND NOT $OpTx$$OpTx$FX_DC$120_INV$125);
MTR_CNTR_ERR_LATCH_PRE <= (MTR_CNTR_ERR AND NOT $OpTx$$OpTx$FX_DC$120_INV$125);

FDCPE_NORTH_OC_LATCH: FDCPE port map (NORTH_OC_LATCH,'1','0',NORTH_OC_LATCH_CLR,NORTH_OC_LATCH_PRE);
NORTH_OC_LATCH_CLR <= (NORTH_OC AND NOT $OpTx$$OpTx$FX_DC$120_INV$125);
NORTH_OC_LATCH_PRE <= (NOT NORTH_OC AND NOT $OpTx$$OpTx$FX_DC$120_INV$125);

FDCPE_PinSignal_U67_Q: FDCPE port map (PinSignal_U67_Q,PinSignal_U67_Q_D,CLK_IN,NOT RESET,'0');
     PinSignal_U67_Q_D <= ((TOP_LM_OVERRIDE_SWITCH AND NOT HA_OS_LATCH_OBUF.LFBK AND
      NOT HP_STOP_LATCH.PIN AND NOT MTR_CNTR_ERR_LATCH.PIN AND NOT TCS_LOCKOUT_LATCH.PIN AND
      NOT DEC_OS_LATCH.PIN AND NOT DOME1_OC_LATCH.PIN AND NOT DOME2_OC_LATCH.PIN AND
      NOT DOME3_OC_LATCH.PIN AND NOT EAST_OC_LATCH.PIN AND NOT EMERG_STOP_LATCH.PIN AND
      NOT NORTH_OC_LATCH.PIN AND NOT SOUTH_OC_LATCH.PIN AND NOT SPARE2_LATCH.PIN AND
      NOT SPARE3_LATCH.PIN AND NOT SPARE4_LATCH.PIN AND NOT SPARE5_LATCH.PIN AND
      NOT WATCHDOG_TIMER_LATCH.PIN AND NOT WEST_OC_LATCH.PIN)
      OR (NOT HA_OS_LATCH_OBUF.LFBK AND
      NOT HA_EMERG_E_LATCH_OBUF.LFBK AND NOT HA_EMERG_W_LATCH_OBUF.LFBK AND
      NOT HA_STOP_E_LATCH_OBUF.LFBK AND NOT HA_STOP_W_LATCH_OBUF.LFBK AND NOT DEC_EMERG_N_LATCH.PIN AND
      NOT DEC_EMERG_S_LATCH.PIN AND NOT DEC_STOP_N_LATCH.PIN AND NOT DEC_STOP_S_LATCH.PIN AND
      NOT HORIZON_STOP_LATCH.PIN AND NOT HP_STOP_LATCH.PIN AND NOT MTR_CNTR_ERR_LATCH.PIN AND
      NOT TCS_LOCKOUT_LATCH.PIN AND NOT DEC_OS_LATCH.PIN AND NOT DOME1_OC_LATCH.PIN AND
      NOT DOME2_OC_LATCH.PIN AND NOT DOME3_OC_LATCH.PIN AND NOT EAST_OC_LATCH.PIN AND
      NOT EMERG_STOP_LATCH.PIN AND NOT NORTH_OC_LATCH.PIN AND NOT SOUTH_OC_LATCH.PIN AND
      NOT SPARE1_LATCH.PIN AND NOT SPARE2_LATCH.PIN AND NOT SPARE3_LATCH.PIN AND
      NOT SPARE4_LATCH.PIN AND NOT SPARE5_LATCH.PIN AND NOT WATCHDOG_TIMER_LATCH.PIN AND
      NOT WEST_OC_LATCH.PIN));

FDCPE_PinSignal_U68_Q: FDCPE port map (PinSignal_U68_Q,PinSignal_U67_Q,CLK_IN,NOT RESET,'0');

FDCPE_SOUTH_OC_LATCH: FDCPE port map (SOUTH_OC_LATCH,'1','0',SOUTH_OC_LATCH_CLR,SOUTH_OC_LATCH_PRE);
SOUTH_OC_LATCH_CLR <= (SOUTH_OC AND NOT $OpTx$$OpTx$FX_DC$120_INV$125);
SOUTH_OC_LATCH_PRE <= (NOT SOUTH_OC AND NOT $OpTx$$OpTx$FX_DC$120_INV$125);

FDCPE_SPARE1_LATCH: FDCPE port map (SPARE1_LATCH,'1','0',SPARE1_LATCH_CLR,SPARE1_LATCH_PRE);
SPARE1_LATCH_CLR <= (SPARE1 AND NOT $OpTx$$OpTx$FX_DC$120_INV$125);
SPARE1_LATCH_PRE <= (NOT SPARE1 AND NOT $OpTx$$OpTx$FX_DC$120_INV$125);

FDCPE_SPARE2_LATCH: FDCPE port map (SPARE2_LATCH,'1','0',SPARE2_LATCH_CLR,SPARE2_LATCH_PRE);
SPARE2_LATCH_CLR <= (SPARE2 AND NOT $OpTx$$OpTx$FX_DC$120_INV$125);
SPARE2_LATCH_PRE <= (NOT SPARE2 AND NOT $OpTx$$OpTx$FX_DC$120_INV$125);

FDCPE_SPARE3_LATCH: FDCPE port map (SPARE3_LATCH,'1','0',SPARE3_LATCH_CLR,SPARE3_LATCH_PRE);
SPARE3_LATCH_CLR <= (SPARE3 AND NOT $OpTx$$OpTx$FX_DC$120_INV$125);
SPARE3_LATCH_PRE <= (NOT SPARE3 AND NOT $OpTx$$OpTx$FX_DC$120_INV$125);

FDCPE_SPARE4_LATCH: FDCPE port map (SPARE4_LATCH,'1','0',SPARE4_LATCH_CLR,SPARE4_LATCH_PRE);
SPARE4_LATCH_CLR <= (SPARE4 AND NOT $OpTx$$OpTx$FX_DC$120_INV$125);
SPARE4_LATCH_PRE <= (NOT SPARE4 AND NOT $OpTx$$OpTx$FX_DC$120_INV$125);

FDCPE_SPARE5_LATCH: FDCPE port map (SPARE5_LATCH,'1','0',SPARE5_LATCH_CLR,SPARE5_LATCH_PRE);
SPARE5_LATCH_CLR <= (SPARE5 AND NOT $OpTx$$OpTx$FX_DC$120_INV$125);
SPARE5_LATCH_PRE <= (NOT SPARE5 AND NOT $OpTx$$OpTx$FX_DC$120_INV$125);

FDCPE_SPARE6_LATCH: FDCPE port map (SPARE6_LATCH,'1','0',SPARE6_LATCH_CLR,SPARE6_LATCH_PRE);
SPARE6_LATCH_CLR <= (SPARE6 AND NOT $OpTx$$OpTx$FX_DC$120_INV$125);
SPARE6_LATCH_PRE <= (NOT SPARE6 AND NOT $OpTx$$OpTx$FX_DC$120_INV$125);

FDCPE_TCS_LOCKOUT_LATCH: FDCPE port map (TCS_LOCKOUT_LATCH,'0','0',TCS_LOCKOUT_LATCH_CLR,TCS_LOCKOUT_LATCH_PRE);
TCS_LOCKOUT_LATCH_CLR <= (NOT TCS_LOCKOUT AND NOT $OpTx$$OpTx$FX_DC$120_INV$125.LFBK);
TCS_LOCKOUT_LATCH_PRE <= (TCS_LOCKOUT AND NOT $OpTx$$OpTx$FX_DC$120_INV$125.LFBK);

TEL_ENABLE <= NOT (((TOP_TEL_ENABLE_SWITCH AND BRAKE_EN_IN AND RESET AND
      NOT PinSignal_U67_Q)
      OR (TOP_TEL_ENABLE_SWITCH AND BRAKE_EN_IN AND RESET AND
      NOT PinSignal_U68_Q)));

TOP_BRAKE_ENABLE_OUT <= NOT (((TOP_TEL_ENABLE_SWITCH AND BRAKE_EN_IN AND RESET AND
      NOT PinSignal_U67_Q)
      OR (TOP_TEL_ENABLE_SWITCH AND BRAKE_EN_IN AND RESET AND
      NOT PinSignal_U68_Q)));

TOP_TCS_ENABLE <= ((RESET AND NOT PinSignal_U67_Q)
OR (RESET AND NOT PinSignal_U68_Q));

FDCPE_WATCHDOG_TIMER_LATCH: FDCPE port map (WATCHDOG_TIMER_LATCH,'1','0',WATCHDOG_TIMER_LATCH_CLR,WATCHDOG_TIMER_LATCH_PRE);
     WATCHDOG_TIMER_LATCH_CLR <= (WATCHDOG_TIMER AND
      NOT $OpTx$$OpTx$FX_DC$120_INV$125.LFBK);
     WATCHDOG_TIMER_LATCH_PRE <= (NOT WATCHDOG_TIMER AND
      NOT $OpTx$$OpTx$FX_DC$120_INV$125.LFBK);

FDCPE_WEST_OC_LATCH: FDCPE port map (WEST_OC_LATCH,'1','0',WEST_OC_LATCH_CLR,WEST_OC_LATCH_PRE);
WEST_OC_LATCH_CLR <= (WEST_OC AND NOT $OpTx$$OpTx$FX_DC$120_INV$125.LFBK);
WEST_OC_LATCH_PRE <= (NOT WEST_OC AND NOT $OpTx$$OpTx$FX_DC$120_INV$125.LFBK);