cpldfit: version I.32 Xilinx Inc.
Fitter Report
Design Name: Logic Date: 7-31-2006, 6:52PM
Device Used: XC9572-15-PC84
Fitting Status: Successful
************************* Mapped Resource Summary **************************
Macrocells Product Terms Function Block Registers Pins
Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot
36 /72 ( 50%) 71 /360 ( 20%) 72 /144 ( 50%) 31 /72 ( 43%) 69 /69 (100%)
** Function Block Resources **
Function Mcells FB Inps Signals Pterms IO
Block Used/Tot Used/Tot Used Used/Tot Used/Tot
FB1 10/18 13/36 13 20/90 10/18
FB2 6/18 35/36 35 12/90 5/17
FB3 9/18 10/36 10 18/90 9/17
FB4 11/18 14/36 14 21/90 9/17
----- ----- ----- -----
36/72 72/144 71/360 33/69
* - Resource is exhausted
** Global Control Resources **
Signal 'CLK_IN' mapped onto global clock net GCK1.
Global output enable net(s) unused.
The complement of 'RESET' mapped onto global set/reset net GSR.
** Pin Resources **
Signal Type Required Mapped | Pin Type Used Total
------------------------------------|------------------------------------
Input : 34 34 | I/O : 63 63
Output : 10 10 | GCK/IO : 3 3
Bidirectional : 23 23 | GTS/IO : 2 2
GCK : 1 1 | GSR/IO : 1 1
GTS : 0 0 |
GSR : 1 1 |
---- ----
Total 69 69
** Power Data **
There are 36 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
End of Mapped Resource Summary
************************** Errors and Warnings ***************************
WARNING:Cpld:1260 - Invalid constraint 'INREG' found in netlist. The constaint
is not supported for targeted device and is ignored.
************************* Summary of Mapped Logic ************************
** 33 Outputs **
Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init
Name Pts Inps No. Type Use Mode Rate State
DEC_STOP_N_LATCH 2 2 FB1_1 4 I/O I/O STD FAST RESET
TEL_ENABLE 2 5 FB1_2 1 I/O O STD FAST
DEC_EMERG_S_LATCH 2 2 FB1_3 6 I/O I/O STD FAST RESET
TOP_TCS_ENABLE 2 3 FB1_4 7 I/O O STD FAST
DOME1_OC_LATCH 2 2 FB1_5 2 I/O I/O STD FAST SET
DOME2_OC_LATCH 2 2 FB1_7 11 I/O I/O STD FAST SET
DOME3_OC_LATCH 2 2 FB1_10 13 I/O I/O STD FAST SET
EAST_OC_LATCH 2 2 FB1_13 20 I/O I/O STD FAST SET
EMERG_STOP_LATCH 2 2 FB1_16 23 I/O I/O STD FAST SET
TOP_BRAKE_ENABLE_OUT 2 5 FB1_18 24 I/O O STD FAST
HA_EMERG_E_LATCH 2 2 FB2_1 63 I/O O STD FAST RESET
HA_EMERG_W_LATCH 2 2 FB2_4 68 I/O O STD FAST RESET
HA_OS_LATCH 2 2 FB2_8 72 I/O O STD FAST SET
HA_STOP_E_LATCH 2 2 FB2_13 80 I/O O STD FAST RESET
HA_STOP_W_LATCH 2 2 FB2_16 82 I/O O STD FAST RESET
MTR_CNTR_ERR_LATCH 2 2 FB3_2 17 I/O I/O STD FAST RESET
NORTH_OC_LATCH 2 2 FB3_4 32 I/O I/O STD FAST SET
SOUTH_OC_LATCH 2 2 FB3_6 34 I/O I/O STD FAST SET
SPARE1_LATCH 2 2 FB3_8 21 I/O I/O STD FAST SET
SPARE2_LATCH 2 2 FB3_10 40 I/O I/O STD FAST SET
SPARE3_LATCH 2 2 FB3_12 41 I/O I/O STD FAST SET
SPARE4_LATCH 2 2 FB3_14 36 I/O I/O STD FAST SET
SPARE5_LATCH 2 2 FB3_16 45 I/O I/O STD FAST SET
SPARE6_LATCH 2 2 FB3_17 39 I/O O STD FAST SET
DEC_EMERG_N_LATCH 2 2 FB4_2 44 I/O I/O STD FAST RESET
DEC_STOP_S_LATCH 2 2 FB4_4 52 I/O I/O STD FAST RESET
DEC_OS_LATCH 2 2 FB4_6 54 I/O I/O STD FAST SET
HORIZON_STOP_LATCH 2 2 FB4_8 48 I/O I/O STD FAST RESET
HP_STOP_LATCH 2 2 FB4_10 57 I/O I/O STD FAST RESET
TCS_LOCKOUT_LATCH 2 2 FB4_12 58 I/O I/O STD FAST RESET
WATCHDOG_TIMER_LATCH 2 2 FB4_14 56 I/O I/O STD FAST SET
WEST_OC_LATCH 2 2 FB4_16 62 I/O I/O STD FAST SET
DOME_ENABLE 3 5 FB4_17 66 I/O O STD FAST
** 3 Buried Nodes **
Signal Total Total Loc Pwr Reg Init
Name Pts Inps Mode State
PinSignal_U67_Q 2 29 FB2_18 STD RESET
PinSignal_U68_Q 1 1 FB4_15 STD RESET
$OpTx$$OpTx$FX_DC$120_INV$125 1 3 FB4_18 STD
** 36 Inputs **
Signal Loc Pin Pin Pin
Name No. Type Use
DEC_STOP_N FB1_6 3 I/O I
HA_OS FB1_8 5 I/O I
CLK_IN FB1_9 9 GCK/I/O GCK
MTR_CNTR_ERR FB1_11 10 GCK/I/O I
DOME1_OC FB1_12 18 I/O I
SPARE1 FB1_14 12 GCK/I/O I
TOP_LM_OVERRIDE_SWITCH FB1_15 14 I/O I
WEST_OC FB1_17 15 I/O I
TOP_TEL_ENABLE_SWITCH FB2_2 69 I/O I
DEC_STOP_S FB2_3 67 I/O I
HA_STOP_E FB2_5 70 I/O I
WATCHDOG_TIMER FB2_6 71 I/O I
SOUTH_OC FB2_7 76 GTS/I/O I
RESET FB2_9 74 GSR/I/O GSR/I
SPARE3 FB2_10 75 I/O I
NORTH_OC FB2_11 77 GTS/I/O I
SPARE4 FB2_12 79 I/O I
TOP_DOMECNTL_SOFTWARE FB2_14 81 I/O I
HA_EMERG_E FB2_15 83 I/O I
TCS_LOCKOUT FB2_17 84 I/O I
SPARE6 FB3_1 25 I/O I
DOME3_OC FB3_3 31 I/O I
HP_STOP FB3_5 19 I/O I
EMERG_STOP FB3_7 35 I/O I
DEC_EMERG_S FB3_9 26 I/O I
DEC_EMERG_N FB3_11 33 I/O I
DOME2_OC FB3_13 43 I/O I
HA_STOP_W FB3_15 37 I/O I
EAST_OC FB4_1 46 I/O I
SPARE5 FB4_3 51 I/O I
HORIZON_STOP FB4_5 47 I/O I
BRAKE_EN_IN FB4_7 55 I/O I
TOP_DOMECNTL_HANDPADDLE FB4_9 50 I/O I
HA_EMERG_W FB4_11 53 I/O I
SPARE2 FB4_13 61 I/O I
DEC_OS FB4_15 65 I/O I
Legend:
Pin No. - ~ - User Assigned
************************** Function Block Details ************************
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs
Used due to wire-ANDing in the switch matrix.
Pin No. - ~ - User Assigned
*********************************** FB1 ***********************************
Number of function block inputs used/remaining: 13/23
Number of signals used by logic mapping into function block: 13
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
DEC_STOP_N_LATCH 2 0 0 3 FB1_1 4 I/O I/O
TEL_ENABLE 2 0 0 3 FB1_2 1 I/O O
DEC_EMERG_S_LATCH 2 0 0 3 FB1_3 6 I/O I/O
TOP_TCS_ENABLE 2 0 0 3 FB1_4 7 I/O O
DOME1_OC_LATCH 2 0 0 3 FB1_5 2 I/O I/O
(unused) 0 0 0 5 FB1_6 3 I/O I
DOME2_OC_LATCH 2 0 0 3 FB1_7 11 I/O I/O
(unused) 0 0 0 5 FB1_8 5 I/O I
(unused) 0 0 0 5 FB1_9 9 GCK/I/O GCK
DOME3_OC_LATCH 2 0 0 3 FB1_10 13 I/O I/O
(unused) 0 0 0 5 FB1_11 10 GCK/I/O I
(unused) 0 0 0 5 FB1_12 18 I/O I
EAST_OC_LATCH 2 0 0 3 FB1_13 20 I/O I/O
(unused) 0 0 0 5 FB1_14 12 GCK/I/O I
(unused) 0 0 0 5 FB1_15 14 I/O I
EMERG_STOP_LATCH 2 0 0 3 FB1_16 23 I/O I/O
(unused) 0 0 0 5 FB1_17 15 I/O I
TOP_BRAKE_ENABLE_OUT
2 0 0 3 FB1_18 24 I/O O
Signals Used by Logic in Function Block
1: $OpTx$$OpTx$FX_DC$120_INV$125 6: TOP_TEL_ENABLE_SWITCH 10: DEC_STOP_N
2: BRAKE_EN_IN 7: EAST_OC 11: DOME3_OC
3: PinSignal_U67_Q 8: DOME1_OC 12: EMERG_STOP
4: PinSignal_U68_Q 9: DOME2_OC 13: DEC_EMERG_S
5: RESET
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
DEC_STOP_N_LATCH X........X.............................. 2 2
TEL_ENABLE .XXXXX.................................. 5 5
DEC_EMERG_S_LATCH X...........X........................... 2 2
TOP_TCS_ENABLE ..XXX................................... 3 3
DOME1_OC_LATCH X......X................................ 2 2
DOME2_OC_LATCH X.......X............................... 2 2
DOME3_OC_LATCH X.........X............................. 2 2
EAST_OC_LATCH X.....X................................. 2 2
EMERG_STOP_LATCH X..........X............................ 2 2
TOP_BRAKE_ENABLE_OUT
.XXXXX.................................. 5 5
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB2 ***********************************
Number of function block inputs used/remaining: 35/1
Number of signals used by logic mapping into function block: 35
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
HA_EMERG_E_LATCH 2 0 0 3 FB2_1 63 I/O O
(unused) 0 0 0 5 FB2_2 69 I/O I
(unused) 0 0 0 5 FB2_3 67 I/O I
HA_EMERG_W_LATCH 2 0 0 3 FB2_4 68 I/O O
(unused) 0 0 0 5 FB2_5 70 I/O I
(unused) 0 0 0 5 FB2_6 71 I/O I
(unused) 0 0 0 5 FB2_7 76 GTS/I/O I
HA_OS_LATCH 2 0 0 3 FB2_8 72 I/O O
(unused) 0 0 0 5 FB2_9 74 GSR/I/O GSR/I
(unused) 0 0 0 5 FB2_10 75 I/O I
(unused) 0 0 0 5 FB2_11 77 GTS/I/O I
(unused) 0 0 0 5 FB2_12 79 I/O I
HA_STOP_E_LATCH 2 0 0 3 FB2_13 80 I/O O
(unused) 0 0 0 5 FB2_14 81 I/O I
(unused) 0 0 0 5 FB2_15 83 I/O I
HA_STOP_W_LATCH 2 0 0 3 FB2_16 82 I/O O
(unused) 0 0 0 5 FB2_17 84 I/O I
PinSignal_U67_Q 2 0 0 3 FB2_18 (b) (b)
Signals Used by Logic in Function Block
1: $OpTx$$OpTx$FX_DC$120_INV$125 13: HA_EMERG_W_LATCH_OBUF.LFBK 25: SPARE4_LATCH.PIN
2: DEC_EMERG_N_LATCH.PIN 14: HA_OS_LATCH_OBUF.LFBK 26: SPARE5_LATCH.PIN
3: DEC_EMERG_S_LATCH.PIN 15: HA_STOP_E_LATCH_OBUF.LFBK 27: TCS_LOCKOUT_LATCH.PIN
4: DEC_OS_LATCH.PIN 16: HA_STOP_W_LATCH_OBUF.LFBK 28: TOP_LM_OVERRIDE_SWITCH
5: DEC_STOP_N_LATCH.PIN 17: HORIZON_STOP_LATCH.PIN 29: HA_STOP_W
6: DEC_STOP_S_LATCH.PIN 18: HP_STOP_LATCH.PIN 30: HA_OS
7: DOME1_OC_LATCH.PIN 19: MTR_CNTR_ERR_LATCH.PIN 31: HA_STOP_E
8: DOME2_OC_LATCH.PIN 20: NORTH_OC_LATCH.PIN 32: HA_EMERG_W
9: DOME3_OC_LATCH.PIN 21: SOUTH_OC_LATCH.PIN 33: HA_EMERG_E
10: EAST_OC_LATCH.PIN 22: SPARE1_LATCH.PIN 34: WATCHDOG_TIMER_LATCH.PIN
11: EMERG_STOP_LATCH.PIN 23: SPARE2_LATCH.PIN 35: WEST_OC_LATCH.PIN
12: HA_EMERG_E_LATCH_OBUF.LFBK 24: SPARE3_LATCH.PIN
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
HA_EMERG_E_LATCH X...............................X....... 2 2
HA_EMERG_W_LATCH X..............................X........ 2 2
HA_OS_LATCH X............................X.......... 2 2
HA_STOP_E_LATCH X.............................X......... 2 2
HA_STOP_W_LATCH X...........................X........... 2 2
PinSignal_U67_Q .XXXXXXXXXXXXXXXXXXXXXXXXXXX.....XX..... 29 29
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB3 ***********************************
Number of function block inputs used/remaining: 10/26
Number of signals used by logic mapping into function block: 10
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB3_1 25 I/O I
MTR_CNTR_ERR_LATCH 2 0 0 3 FB3_2 17 I/O I/O
(unused) 0 0 0 5 FB3_3 31 I/O I
NORTH_OC_LATCH 2 0 0 3 FB3_4 32 I/O I/O
(unused) 0 0 0 5 FB3_5 19 I/O I
SOUTH_OC_LATCH 2 0 0 3 FB3_6 34 I/O I/O
(unused) 0 0 0 5 FB3_7 35 I/O I
SPARE1_LATCH 2 0 0 3 FB3_8 21 I/O I/O
(unused) 0 0 0 5 FB3_9 26 I/O I
SPARE2_LATCH 2 0 0 3 FB3_10 40 I/O I/O
(unused) 0 0 0 5 FB3_11 33 I/O I
SPARE3_LATCH 2 0 0 3 FB3_12 41 I/O I/O
(unused) 0 0 0 5 FB3_13 43 I/O I
SPARE4_LATCH 2 0 0 3 FB3_14 36 I/O I/O
(unused) 0 0 0 5 FB3_15 37 I/O I
SPARE5_LATCH 2 0 0 3 FB3_16 45 I/O I/O
SPARE6_LATCH 2 0 0 3 FB3_17 39 I/O O
(unused) 0 0 0 5 FB3_18 (b)
Signals Used by Logic in Function Block
1: $OpTx$$OpTx$FX_DC$120_INV$125 5: SPARE1 8: MTR_CNTR_ERR
2: SPARE3 6: SPARE4 9: SPARE2
3: NORTH_OC 7: SPARE6 10: SPARE5
4: SOUTH_OC
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
MTR_CNTR_ERR_LATCH X......X................................ 2 2
NORTH_OC_LATCH X.X..................................... 2 2
SOUTH_OC_LATCH X..X.................................... 2 2
SPARE1_LATCH X...X................................... 2 2
SPARE2_LATCH X.......X............................... 2 2
SPARE3_LATCH XX...................................... 2 2
SPARE4_LATCH X....X.................................. 2 2
SPARE5_LATCH X........X.............................. 2 2
SPARE6_LATCH X.....X................................. 2 2
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB4 ***********************************
Number of function block inputs used/remaining: 14/22
Number of signals used by logic mapping into function block: 14
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB4_1 46 I/O I
DEC_EMERG_N_LATCH 2 0 0 3 FB4_2 44 I/O I/O
(unused) 0 0 0 5 FB4_3 51 I/O I
DEC_STOP_S_LATCH 2 0 0 3 FB4_4 52 I/O I/O
(unused) 0 0 0 5 FB4_5 47 I/O I
DEC_OS_LATCH 2 0 0 3 FB4_6 54 I/O I/O
(unused) 0 0 0 5 FB4_7 55 I/O I
HORIZON_STOP_LATCH 2 0 0 3 FB4_8 48 I/O I/O
(unused) 0 0 0 5 FB4_9 50 I/O I
HP_STOP_LATCH 2 0 0 3 FB4_10 57 I/O I/O
(unused) 0 0 0 5 FB4_11 53 I/O I
TCS_LOCKOUT_LATCH 2 0 0 3 FB4_12 58 I/O I/O
(unused) 0 0 0 5 FB4_13 61 I/O I
WATCHDOG_TIMER_LATCH
2 0 0 3 FB4_14 56 I/O I/O
PinSignal_U68_Q 1 0 0 4 FB4_15 65 I/O I
WEST_OC_LATCH 2 0 0 3 FB4_16 62 I/O I/O
DOME_ENABLE 3 0 0 2 FB4_17 66 I/O O
$OpTx$$OpTx$FX_DC$120_INV$125
1 0 0 4 FB4_18 (b) (b)
Signals Used by Logic in Function Block
1: $OpTx$$OpTx$FX_DC$120_INV$125.LFBK 6: TOP_DOMECNTL_SOFTWARE 11: HP_STOP
2: PinSignal_U67_Q 7: WEST_OC 12: HORIZON_STOP
3: PinSignal_U68_Q.LFBK 8: DEC_STOP_S 13: TCS_LOCKOUT
4: RESET 9: WATCHDOG_TIMER 14: DEC_OS
5: TOP_DOMECNTL_HANDPADDLE 10: DEC_EMERG_N
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
DEC_EMERG_N_LATCH X........X.............................. 2 2
DEC_STOP_S_LATCH X......X................................ 2 2
DEC_OS_LATCH X............X.......................... 2 2
HORIZON_STOP_LATCH X..........X............................ 2 2
HP_STOP_LATCH X.........X............................. 2 2
TCS_LOCKOUT_LATCH X...........X........................... 2 2
WATCHDOG_TIMER_LATCH
X.......X............................... 2 2
PinSignal_U68_Q .X...................................... 1 1
WEST_OC_LATCH X.....X................................. 2 2
DOME_ENABLE .XXXXX.................................. 5 5
$OpTx$$OpTx$FX_DC$120_INV$125
.XXX.................................... 3 3
0----+----1----+----2----+----3----+----4
0 0 0 0
******************************* Equations ********************************
********** Mapped Logic **********
$OpTx$$OpTx$FX_DC$120_INV$125 <= (RESET AND PinSignal_U67_Q AND PinSignal_U68_Q.LFBK);
FDCPE_DEC_EMERG_N_LATCH: FDCPE port map (DEC_EMERG_N_LATCH,'0','0',DEC_EMERG_N_LATCH_CLR,DEC_EMERG_N_LATCH_PRE);
DEC_EMERG_N_LATCH_CLR <= (NOT DEC_EMERG_N AND NOT $OpTx$$OpTx$FX_DC$120_INV$125.LFBK);
DEC_EMERG_N_LATCH_PRE <= (DEC_EMERG_N AND NOT $OpTx$$OpTx$FX_DC$120_INV$125.LFBK);
FDCPE_DEC_EMERG_S_LATCH: FDCPE port map (DEC_EMERG_S_LATCH,'0','0',DEC_EMERG_S_LATCH_CLR,DEC_EMERG_S_LATCH_PRE);
DEC_EMERG_S_LATCH_CLR <= (NOT DEC_EMERG_S AND NOT $OpTx$$OpTx$FX_DC$120_INV$125);
DEC_EMERG_S_LATCH_PRE <= (DEC_EMERG_S AND NOT $OpTx$$OpTx$FX_DC$120_INV$125);
FDCPE_DEC_OS_LATCH: FDCPE port map (DEC_OS_LATCH,'1','0',DEC_OS_LATCH_CLR,DEC_OS_LATCH_PRE);
DEC_OS_LATCH_CLR <= (DEC_OS AND NOT $OpTx$$OpTx$FX_DC$120_INV$125.LFBK);
DEC_OS_LATCH_PRE <= (NOT DEC_OS AND NOT $OpTx$$OpTx$FX_DC$120_INV$125.LFBK);
FDCPE_DEC_STOP_N_LATCH: FDCPE port map (DEC_STOP_N_LATCH,'0','0',DEC_STOP_N_LATCH_CLR,DEC_STOP_N_LATCH_PRE);
DEC_STOP_N_LATCH_CLR <= (NOT DEC_STOP_N AND NOT $OpTx$$OpTx$FX_DC$120_INV$125);
DEC_STOP_N_LATCH_PRE <= (DEC_STOP_N AND NOT $OpTx$$OpTx$FX_DC$120_INV$125);
FDCPE_DEC_STOP_S_LATCH: FDCPE port map (DEC_STOP_S_LATCH,'0','0',DEC_STOP_S_LATCH_CLR,DEC_STOP_S_LATCH_PRE);
DEC_STOP_S_LATCH_CLR <= (NOT DEC_STOP_S AND NOT $OpTx$$OpTx$FX_DC$120_INV$125.LFBK);
DEC_STOP_S_LATCH_PRE <= (DEC_STOP_S AND NOT $OpTx$$OpTx$FX_DC$120_INV$125.LFBK);
FDCPE_DOME1_OC_LATCH: FDCPE port map (DOME1_OC_LATCH,'1','0',DOME1_OC_LATCH_CLR,DOME1_OC_LATCH_PRE);
DOME1_OC_LATCH_CLR <= (DOME1_OC AND NOT $OpTx$$OpTx$FX_DC$120_INV$125);
DOME1_OC_LATCH_PRE <= (NOT DOME1_OC AND NOT $OpTx$$OpTx$FX_DC$120_INV$125);
FDCPE_DOME2_OC_LATCH: FDCPE port map (DOME2_OC_LATCH,'1','0',DOME2_OC_LATCH_CLR,DOME2_OC_LATCH_PRE);
DOME2_OC_LATCH_CLR <= (DOME2_OC AND NOT $OpTx$$OpTx$FX_DC$120_INV$125);
DOME2_OC_LATCH_PRE <= (NOT DOME2_OC AND NOT $OpTx$$OpTx$FX_DC$120_INV$125);
FDCPE_DOME3_OC_LATCH: FDCPE port map (DOME3_OC_LATCH,'1','0',DOME3_OC_LATCH_CLR,DOME3_OC_LATCH_PRE);
DOME3_OC_LATCH_CLR <= (DOME3_OC AND NOT $OpTx$$OpTx$FX_DC$120_INV$125);
DOME3_OC_LATCH_PRE <= (NOT DOME3_OC AND NOT $OpTx$$OpTx$FX_DC$120_INV$125);
DOME_ENABLE <= ((NOT RESET)
OR (PinSignal_U67_Q AND PinSignal_U68_Q.LFBK)
OR (NOT TOP_DOMECNTL_SOFTWARE AND NOT TOP_DOMECNTL_HANDPADDLE));
FDCPE_EAST_OC_LATCH: FDCPE port map (EAST_OC_LATCH,'1','0',EAST_OC_LATCH_CLR,EAST_OC_LATCH_PRE);
EAST_OC_LATCH_CLR <= (EAST_OC AND NOT $OpTx$$OpTx$FX_DC$120_INV$125);
EAST_OC_LATCH_PRE <= (NOT EAST_OC AND NOT $OpTx$$OpTx$FX_DC$120_INV$125);
FDCPE_EMERG_STOP_LATCH: FDCPE port map (EMERG_STOP_LATCH,'1','0',EMERG_STOP_LATCH_CLR,EMERG_STOP_LATCH_PRE);
EMERG_STOP_LATCH_CLR <= (EMERG_STOP AND NOT $OpTx$$OpTx$FX_DC$120_INV$125);
EMERG_STOP_LATCH_PRE <= (NOT EMERG_STOP AND NOT $OpTx$$OpTx$FX_DC$120_INV$125);
FDCPE_HA_EMERG_E_LATCH: FDCPE port map (HA_EMERG_E_LATCH,'0','0',HA_EMERG_E_LATCH_CLR,HA_EMERG_E_LATCH_PRE);
HA_EMERG_E_LATCH_CLR <= (NOT HA_EMERG_E AND NOT $OpTx$$OpTx$FX_DC$120_INV$125);
HA_EMERG_E_LATCH_PRE <= (HA_EMERG_E AND NOT $OpTx$$OpTx$FX_DC$120_INV$125);
FDCPE_HA_EMERG_W_LATCH: FDCPE port map (HA_EMERG_W_LATCH,'0','0',HA_EMERG_W_LATCH_CLR,HA_EMERG_W_LATCH_PRE);
HA_EMERG_W_LATCH_CLR <= (NOT HA_EMERG_W AND NOT $OpTx$$OpTx$FX_DC$120_INV$125);
HA_EMERG_W_LATCH_PRE <= (HA_EMERG_W AND NOT $OpTx$$OpTx$FX_DC$120_INV$125);
FDCPE_HA_OS_LATCH: FDCPE port map (HA_OS_LATCH,'1','0',HA_OS_LATCH_CLR,HA_OS_LATCH_PRE);
HA_OS_LATCH_CLR <= (HA_OS AND NOT $OpTx$$OpTx$FX_DC$120_INV$125);
HA_OS_LATCH_PRE <= (NOT HA_OS AND NOT $OpTx$$OpTx$FX_DC$120_INV$125);
FDCPE_HA_STOP_E_LATCH: FDCPE port map (HA_STOP_E_LATCH,'0','0',HA_STOP_E_LATCH_CLR,HA_STOP_E_LATCH_PRE);
HA_STOP_E_LATCH_CLR <= (NOT HA_STOP_E AND NOT $OpTx$$OpTx$FX_DC$120_INV$125);
HA_STOP_E_LATCH_PRE <= (HA_STOP_E AND NOT $OpTx$$OpTx$FX_DC$120_INV$125);
FDCPE_HA_STOP_W_LATCH: FDCPE port map (HA_STOP_W_LATCH,'0','0',HA_STOP_W_LATCH_CLR,HA_STOP_W_LATCH_PRE);
HA_STOP_W_LATCH_CLR <= (NOT HA_STOP_W AND NOT $OpTx$$OpTx$FX_DC$120_INV$125);
HA_STOP_W_LATCH_PRE <= (HA_STOP_W AND NOT $OpTx$$OpTx$FX_DC$120_INV$125);
FDCPE_HORIZON_STOP_LATCH: FDCPE port map (HORIZON_STOP_LATCH,'0','0',HORIZON_STOP_LATCH_CLR,HORIZON_STOP_LATCH_PRE);
HORIZON_STOP_LATCH_CLR <= (NOT HORIZON_STOP AND NOT $OpTx$$OpTx$FX_DC$120_INV$125.LFBK);
HORIZON_STOP_LATCH_PRE <= (HORIZON_STOP AND NOT $OpTx$$OpTx$FX_DC$120_INV$125.LFBK);
FDCPE_HP_STOP_LATCH: FDCPE port map (HP_STOP_LATCH,'0','0',HP_STOP_LATCH_CLR,HP_STOP_LATCH_PRE);
HP_STOP_LATCH_CLR <= (NOT HP_STOP AND NOT $OpTx$$OpTx$FX_DC$120_INV$125.LFBK);
HP_STOP_LATCH_PRE <= (HP_STOP AND NOT $OpTx$$OpTx$FX_DC$120_INV$125.LFBK);
FDCPE_MTR_CNTR_ERR_LATCH: FDCPE port map (MTR_CNTR_ERR_LATCH,'0','0',MTR_CNTR_ERR_LATCH_CLR,MTR_CNTR_ERR_LATCH_PRE);
MTR_CNTR_ERR_LATCH_CLR <= (NOT MTR_CNTR_ERR AND NOT $OpTx$$OpTx$FX_DC$120_INV$125);
MTR_CNTR_ERR_LATCH_PRE <= (MTR_CNTR_ERR AND NOT $OpTx$$OpTx$FX_DC$120_INV$125);
FDCPE_NORTH_OC_LATCH: FDCPE port map (NORTH_OC_LATCH,'1','0',NORTH_OC_LATCH_CLR,NORTH_OC_LATCH_PRE);
NORTH_OC_LATCH_CLR <= (NORTH_OC AND NOT $OpTx$$OpTx$FX_DC$120_INV$125);
NORTH_OC_LATCH_PRE <= (NOT NORTH_OC AND NOT $OpTx$$OpTx$FX_DC$120_INV$125);
FDCPE_PinSignal_U67_Q: FDCPE port map (PinSignal_U67_Q,PinSignal_U67_Q_D,CLK_IN,NOT RESET,'0');
PinSignal_U67_Q_D <= ((TOP_LM_OVERRIDE_SWITCH AND NOT HA_OS_LATCH_OBUF.LFBK AND
NOT HP_STOP_LATCH.PIN AND NOT MTR_CNTR_ERR_LATCH.PIN AND NOT TCS_LOCKOUT_LATCH.PIN AND
NOT DEC_OS_LATCH.PIN AND NOT DOME1_OC_LATCH.PIN AND NOT DOME2_OC_LATCH.PIN AND
NOT DOME3_OC_LATCH.PIN AND NOT EAST_OC_LATCH.PIN AND NOT EMERG_STOP_LATCH.PIN AND
NOT NORTH_OC_LATCH.PIN AND NOT SOUTH_OC_LATCH.PIN AND NOT SPARE2_LATCH.PIN AND
NOT SPARE3_LATCH.PIN AND NOT SPARE4_LATCH.PIN AND NOT SPARE5_LATCH.PIN AND
NOT WATCHDOG_TIMER_LATCH.PIN AND NOT WEST_OC_LATCH.PIN)
OR (NOT HA_OS_LATCH_OBUF.LFBK AND
NOT HA_EMERG_E_LATCH_OBUF.LFBK AND NOT HA_EMERG_W_LATCH_OBUF.LFBK AND
NOT HA_STOP_E_LATCH_OBUF.LFBK AND NOT HA_STOP_W_LATCH_OBUF.LFBK AND NOT DEC_EMERG_N_LATCH.PIN AND
NOT DEC_EMERG_S_LATCH.PIN AND NOT DEC_STOP_N_LATCH.PIN AND NOT DEC_STOP_S_LATCH.PIN AND
NOT HORIZON_STOP_LATCH.PIN AND NOT HP_STOP_LATCH.PIN AND NOT MTR_CNTR_ERR_LATCH.PIN AND
NOT TCS_LOCKOUT_LATCH.PIN AND NOT DEC_OS_LATCH.PIN AND NOT DOME1_OC_LATCH.PIN AND
NOT DOME2_OC_LATCH.PIN AND NOT DOME3_OC_LATCH.PIN AND NOT EAST_OC_LATCH.PIN AND
NOT EMERG_STOP_LATCH.PIN AND NOT NORTH_OC_LATCH.PIN AND NOT SOUTH_OC_LATCH.PIN AND
NOT SPARE1_LATCH.PIN AND NOT SPARE2_LATCH.PIN AND NOT SPARE3_LATCH.PIN AND
NOT SPARE4_LATCH.PIN AND NOT SPARE5_LATCH.PIN AND NOT WATCHDOG_TIMER_LATCH.PIN AND
NOT WEST_OC_LATCH.PIN));
FDCPE_PinSignal_U68_Q: FDCPE port map (PinSignal_U68_Q,PinSignal_U67_Q,CLK_IN,NOT RESET,'0');
FDCPE_SOUTH_OC_LATCH: FDCPE port map (SOUTH_OC_LATCH,'1','0',SOUTH_OC_LATCH_CLR,SOUTH_OC_LATCH_PRE);
SOUTH_OC_LATCH_CLR <= (SOUTH_OC AND NOT $OpTx$$OpTx$FX_DC$120_INV$125);
SOUTH_OC_LATCH_PRE <= (NOT SOUTH_OC AND NOT $OpTx$$OpTx$FX_DC$120_INV$125);
FDCPE_SPARE1_LATCH: FDCPE port map (SPARE1_LATCH,'1','0',SPARE1_LATCH_CLR,SPARE1_LATCH_PRE);
SPARE1_LATCH_CLR <= (SPARE1 AND NOT $OpTx$$OpTx$FX_DC$120_INV$125);
SPARE1_LATCH_PRE <= (NOT SPARE1 AND NOT $OpTx$$OpTx$FX_DC$120_INV$125);
FDCPE_SPARE2_LATCH: FDCPE port map (SPARE2_LATCH,'1','0',SPARE2_LATCH_CLR,SPARE2_LATCH_PRE);
SPARE2_LATCH_CLR <= (SPARE2 AND NOT $OpTx$$OpTx$FX_DC$120_INV$125);
SPARE2_LATCH_PRE <= (NOT SPARE2 AND NOT $OpTx$$OpTx$FX_DC$120_INV$125);
FDCPE_SPARE3_LATCH: FDCPE port map (SPARE3_LATCH,'1','0',SPARE3_LATCH_CLR,SPARE3_LATCH_PRE);
SPARE3_LATCH_CLR <= (SPARE3 AND NOT $OpTx$$OpTx$FX_DC$120_INV$125);
SPARE3_LATCH_PRE <= (NOT SPARE3 AND NOT $OpTx$$OpTx$FX_DC$120_INV$125);
FDCPE_SPARE4_LATCH: FDCPE port map (SPARE4_LATCH,'1','0',SPARE4_LATCH_CLR,SPARE4_LATCH_PRE);
SPARE4_LATCH_CLR <= (SPARE4 AND NOT $OpTx$$OpTx$FX_DC$120_INV$125);
SPARE4_LATCH_PRE <= (NOT SPARE4 AND NOT $OpTx$$OpTx$FX_DC$120_INV$125);
FDCPE_SPARE5_LATCH: FDCPE port map (SPARE5_LATCH,'1','0',SPARE5_LATCH_CLR,SPARE5_LATCH_PRE);
SPARE5_LATCH_CLR <= (SPARE5 AND NOT $OpTx$$OpTx$FX_DC$120_INV$125);
SPARE5_LATCH_PRE <= (NOT SPARE5 AND NOT $OpTx$$OpTx$FX_DC$120_INV$125);
FDCPE_SPARE6_LATCH: FDCPE port map (SPARE6_LATCH,'1','0',SPARE6_LATCH_CLR,SPARE6_LATCH_PRE);
SPARE6_LATCH_CLR <= (SPARE6 AND NOT $OpTx$$OpTx$FX_DC$120_INV$125);
SPARE6_LATCH_PRE <= (NOT SPARE6 AND NOT $OpTx$$OpTx$FX_DC$120_INV$125);
FDCPE_TCS_LOCKOUT_LATCH: FDCPE port map (TCS_LOCKOUT_LATCH,'0','0',TCS_LOCKOUT_LATCH_CLR,TCS_LOCKOUT_LATCH_PRE);
TCS_LOCKOUT_LATCH_CLR <= (NOT TCS_LOCKOUT AND NOT $OpTx$$OpTx$FX_DC$120_INV$125.LFBK);
TCS_LOCKOUT_LATCH_PRE <= (TCS_LOCKOUT AND NOT $OpTx$$OpTx$FX_DC$120_INV$125.LFBK);
TEL_ENABLE <= NOT (((TOP_TEL_ENABLE_SWITCH AND BRAKE_EN_IN AND RESET AND
NOT PinSignal_U67_Q)
OR (TOP_TEL_ENABLE_SWITCH AND BRAKE_EN_IN AND RESET AND
NOT PinSignal_U68_Q)));
TOP_BRAKE_ENABLE_OUT <= NOT (((TOP_TEL_ENABLE_SWITCH AND BRAKE_EN_IN AND RESET AND
NOT PinSignal_U67_Q)
OR (TOP_TEL_ENABLE_SWITCH AND BRAKE_EN_IN AND RESET AND
NOT PinSignal_U68_Q)));
TOP_TCS_ENABLE <= ((RESET AND NOT PinSignal_U67_Q)
OR (RESET AND NOT PinSignal_U68_Q));
FDCPE_WATCHDOG_TIMER_LATCH: FDCPE port map (WATCHDOG_TIMER_LATCH,'1','0',WATCHDOG_TIMER_LATCH_CLR,WATCHDOG_TIMER_LATCH_PRE);
WATCHDOG_TIMER_LATCH_CLR <= (WATCHDOG_TIMER AND
NOT $OpTx$$OpTx$FX_DC$120_INV$125.LFBK);
WATCHDOG_TIMER_LATCH_PRE <= (NOT WATCHDOG_TIMER AND
NOT $OpTx$$OpTx$FX_DC$120_INV$125.LFBK);
FDCPE_WEST_OC_LATCH: FDCPE port map (WEST_OC_LATCH,'1','0',WEST_OC_LATCH_CLR,WEST_OC_LATCH_PRE);
WEST_OC_LATCH_CLR <= (WEST_OC AND NOT $OpTx$$OpTx$FX_DC$120_INV$125.LFBK);
WEST_OC_LATCH_PRE <= (NOT WEST_OC AND NOT $OpTx$$OpTx$FX_DC$120_INV$125.LFBK);
Register Legend:
FDCPE (Q,D,C,CLR,PRE);
FTCPE (Q,D,C,CLR,PRE);
LDCP (Q,D,G,CLR,PRE);
****************************** Device Pin Out *****************************
Device : XC9572-15-PC84
--------------------------------------------------------------
/11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 \
| 12 74 |
| 13 73 |
| 14 72 |
| 15 71 |
| 16 70 |
| 17 69 |
| 18 68 |
| 19 67 |
| 20 66 |
| 21 XC9572-15-PC84 65 |
| 22 64 |
| 23 63 |
| 24 62 |
| 25 61 |
| 26 60 |
| 27 59 |
| 28 58 |
| 29 57 |
| 30 56 |
| 31 55 |
| 32 54 |
\ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 /
--------------------------------------------------------------
Pin Signal Pin Signal
No. Name No. Name
1 TEL_ENABLE 43 DOME2_OC
2 DOME1_OC_LATCH 44 DEC_EMERG_N_LATCH
3 DEC_STOP_N 45 SPARE5_LATCH
4 DEC_STOP_N_LATCH 46 EAST_OC
5 HA_OS 47 HORIZON_STOP
6 DEC_EMERG_S_LATCH 48 HORIZON_STOP_LATCH
7 TOP_TCS_ENABLE 49 GND
8 GND 50 TOP_DOMECNTL_HANDPADDLE
9 CLK_IN 51 SPARE5
10 MTR_CNTR_ERR 52 DEC_STOP_S_LATCH
11 DOME2_OC_LATCH 53 HA_EMERG_W
12 SPARE1 54 DEC_OS_LATCH
13 DOME3_OC_LATCH 55 BRAKE_EN_IN
14 TOP_LM_OVERRIDE_SWITCH 56 WATCHDOG_TIMER_LATCH
15 WEST_OC 57 HP_STOP_LATCH
16 GND 58 TCS_LOCKOUT_LATCH
17 MTR_CNTR_ERR_LATCH 59 TDO
18 DOME1_OC 60 GND
19 HP_STOP 61 SPARE2
20 EAST_OC_LATCH 62 WEST_OC_LATCH
21 SPARE1_LATCH 63 HA_EMERG_E_LATCH
22 VCC 64 VCC
23 EMERG_STOP_LATCH 65 DEC_OS
24 TOP_BRAKE_ENABLE_OUT 66 DOME_ENABLE
25 SPARE6 67 DEC_STOP_S
26 DEC_EMERG_S 68 HA_EMERG_W_LATCH
27 GND 69 TOP_TEL_ENABLE_SWITCH
28 TDI 70 HA_STOP_E
29 TMS 71 WATCHDOG_TIMER
30 TCK 72 HA_OS_LATCH
31 DOME3_OC 73 VCC
32 NORTH_OC_LATCH 74 RESET
33 DEC_EMERG_N 75 SPARE3
34 SOUTH_OC_LATCH 76 SOUTH_OC
35 EMERG_STOP 77 NORTH_OC
36 SPARE4_LATCH 78 VCC
37 HA_STOP_W 79 SPARE4
38 VCC 80 HA_STOP_E_LATCH
39 SPARE6_LATCH 81 TOP_DOMECNTL_SOFTWARE
40 SPARE2_LATCH 82 HA_STOP_W_LATCH
41 SPARE3_LATCH 83 HA_EMERG_E
42 GND 84 TCS_LOCKOUT
Legend : NC = Not Connected, unbonded pin
PGND = Unused I/O configured as additional Ground pin
TIE = Unused I/O floating -- must tie to VCC, GND or other signal
VCC = Dedicated Power Pin
GND = Dedicated Ground Pin
TDI = Test Data In, JTAG pin
TDO = Test Data Out, JTAG pin
TCK = Test Clock, JTAG pin
TMS = Test Mode Select, JTAG pin
PROHIBITED = User reserved pin
**************************** Compiler Options ****************************
Following is a list of all global compiler options used by the fitter run.
Device(s) Specified : xc9572-15-PC84
Optimization Method : SPEED
Multi-Level Logic Optimization : ON
Ignore Timing Specifications : OFF
Default Register Power Up Value : LOW
Keep User Location Constraints : ON
What-You-See-Is-What-You-Get : OFF
Exhaustive Fitting : OFF
Keep Unused Inputs : OFF
Slew Rate : FAST
Power Mode : STD
Ground on Unused IOs : OFF
Global Clock Optimization : ON
Global Set/Reset Optimization : ON
Global Ouput Enable Optimization : ON
FASTConnect/UIM optimzation : ON
Local Feedback : ON
Pin Feedback : ON
Input Limit : 36
Pterm Limit : 25