Project Navigator Auto-Make Log File ------------------------------------- deleting __projnav/Safety.gfl Finished cleaning up project Project Navigator Auto-Make Log File ------------------------------------- deleting __projnav/Safety.gfl Finished cleaning up project Project Navigator Auto-Make Log File ------------------------------------- deleting __projnav/Safety.gfl Finished cleaning up project Project Navigator Auto-Make Log File ------------------------------------- Started process "Compile HDL Simulation Libraries". Release 6.3.01i - compxlib XILINX = 'C:\Xilinx' SIMULATOR = MODELSIM SE/EE Source Tools => [null] ERROR:cxl[env]:11- unable to find simulator (mti_se) executables : If you are compiling simulation libraries in ISE-GUI then, specify the simulator executable path in the "Simulator Path" property under "Compile HDL Simulation Libraries" properties. If you are compiling simulation libraries using compxlib in command line then, use the -p option to specify the executable path or set the COMPXLIB_SIM_PATH environment variable. For example :- -p \modeltech_5.7\win32 or COMPXLIB_SIM_PATH = \modeltech_5.7\win32 IMPORTANT: Make sure that the license file/other environment variable for mti_se are properly set compxlib.log generated. Completed process "Compile HDL Simulation Libraries". Project Navigator Auto-Make Log File ------------------------------------- Started process "Compile HDL Simulation Libraries". Release 6.3.01i - compxlib XILINX = 'C:\Xilinx' SIMULATOR = MODELSIM SE/EE Source Tools => [null] ERROR:cxl[env]:11- unable to find simulator (mti_se) executables : If you are compiling simulation libraries in ISE-GUI then, specify the simulator executable path in the "Simulator Path" property under "Compile HDL Simulation Libraries" properties. If you are compiling simulation libraries using compxlib in command line then, use the -p option to specify the executable path or set the COMPXLIB_SIM_PATH environment variable. For example :- -p \modeltech_5.7\win32 or COMPXLIB_SIM_PATH = \modeltech_5.7\win32 IMPORTANT: Make sure that the license file/other environment variable for mti_se are properly set compxlib.log generated. Completed process "Compile HDL Simulation Libraries". Project Navigator Auto-Make Log File ------------------------------------- Started process "HDL Converter". ERROR: No input file specified for the "HDL Converter" process. Please select an input file (ABEL or AHDL) from the property menu. (Right click on the "HDL Converter" process name and select 'Properties') Process "HDL Converter" did not complete due to error(s) reported by internal script. Project Navigator Auto-Make Log File ------------------------------------- ERROR : Please specify a 'TDO Input File' in the 'TDO Converter' process properties window. Project Navigator Auto-Make Log File ------------------------------------- deleting compxlib.log deleting Safety.cxl deleting compxlib.log deleting Safety.cxl deleting __projnav/TOvhd_tcl.rsp deleting __projnav/TOver_tcl.rsp deleting __projnav/TO_tcf_tcl.rsp deleting __projnav/Safety.gfl Finished cleaning up project Project Navigator Auto-Make Log File ------------------------------------- Started process "Compile HDL Simulation Libraries". Release 6.3.01i - compxlib XILINX = 'C:\Xilinx' SIMULATOR = MODELSIM SE/EE Source Tools => [null] ERROR:cxl[env]:11- unable to find simulator (mti_se) executables : If you are compiling simulation libraries in ISE-GUI then, specify the simulator executable path in the "Simulator Path" property under "Compile HDL Simulation Libraries" properties. If you are compiling simulation libraries using compxlib in command line then, use the -p option to specify the executable path or set the COMPXLIB_SIM_PATH environment variable. For example :- -p \modeltech_5.7\win32 or COMPXLIB_SIM_PATH = \modeltech_5.7\win32 IMPORTANT: Make sure that the license file/other environment variable for mti_se are properly set compxlib.log generated. Completed process "Compile HDL Simulation Libraries". Project Navigator Auto-Make Log File ------------------------------------- Started process "HDL Converter". ERROR: No input file specified for the "HDL Converter" process. Please select an input file (ABEL or AHDL) from the property menu. (Right click on the "HDL Converter" process name and select 'Properties') Process "HDL Converter" did not complete due to error(s) reported by internal script. Project Navigator Auto-Make Log File ------------------------------------- An error occured while executing C:/Xilinx/data/projnav/scripts/_tdoconvert.tcl Project Navigator Auto-Make Log File ------------------------------------- Started process "Translate". Extracting independent architecture files... Release 6.3.02i - ngdbuild G.37 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -i -p xc9500 Logic.EDF Logic.ngd Launcher: Executing edif2ngd "Logic.EDF" "_ngo\Logic.ngo" INFO:NgdBuild - Release 6.3.02i - edif2ngd G.37 INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. ERROR:NgdBuild:196 - On or above line 219 in file "Logic.EDF": Problem parsing "?". This likely means that the EDIF netlist was improperly written. Please contact the vendor of the program that produced this EDIF. ERROR:NgdBuild:276 - edif2ngd exited with errors (return code 2). ERROR:NgdBuild:28 - Top-level input design file "Logic.EDF" cannot be found or created. Please make sure the source file exists and is of a recognized netlist format (e.g., ngo, ngc, edif, edn, or edf). Writing NGDBUILD log file "Logic.bld"... Error: Process "Translate" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Translate". Release 6.3.02i - ngdbuild G.37 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -i -p xc9500 Logic.EDF Logic.ngd Launcher: Executing edif2ngd "Logic.EDF" "_ngo\Logic.ngo" INFO:NgdBuild - Release 6.3.02i - edif2ngd G.37 INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. ERROR:NgdBuild:196 - On or above line 219 in file "Logic.EDF": Problem parsing "?". This likely means that the EDIF netlist was improperly written. Please contact the vendor of the program that produced this EDIF. ERROR:NgdBuild:276 - edif2ngd exited with errors (return code 2). ERROR:NgdBuild:28 - Top-level input design file "Logic.EDF" cannot be found or created. Please make sure the source file exists and is of a recognized netlist format (e.g., ngo, ngc, edif, edn, or edf). Writing NGDBUILD log file "Logic.bld"... Error: Process "Translate" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Translate". Release 6.3.02i - ngdbuild G.37 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -i -p xc9500 Logic.EDF Logic.ngd Launcher: Executing edif2ngd "Logic.EDF" "_ngo\Logic.ngo" INFO:NgdBuild - Release 6.3.02i - edif2ngd G.37 INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. ERROR:NgdBuild:196 - On or above line 219 in file "Logic.EDF": Problem parsing "?". This likely means that the EDIF netlist was improperly written. Please contact the vendor of the program that produced this EDIF. ERROR:NgdBuild:276 - edif2ngd exited with errors (return code 2). ERROR:NgdBuild:28 - Top-level input design file "Logic.EDF" cannot be found or created. Please make sure the source file exists and is of a recognized netlist format (e.g., ngo, ngc, edif, edn, or edf). Writing NGDBUILD log file "Logic.bld"... Error: Process "Translate" did not complete. Project Navigator Auto-Make Log File ------------------------------------- deleting compxlib.log deleting Safety.cxl deleting __projnav/Logic_edfTOngd_tcl.rsp deleting Logic.ngd deleting Logic.bld deleting Logic_ngdbuild.nav deleting _ngo/netlist.lst deleting .untf deleting Logic_html deleting Logic.cmd_log deleting __projnav/Logic_edfTOngd_tcl.rsp deleting Logic.ngd deleting Logic.bld deleting Logic_ngdbuild.nav deleting _ngo/netlist.lst deleting .untf deleting Logic_html deleting Logic.cmd_log deleting __projnav/Logic_edfTOngd_tcl.rsp deleting Logic.ngd deleting Logic.bld deleting Logic_ngdbuild.nav deleting _ngo/netlist.lst deleting .untf deleting Logic_html deleting Logic.cmd_log deleting __projnav/Safety.gfl Finished cleaning up project Project Navigator Auto-Make Log File ------------------------------------- Started process "Check Syntax". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/Xilinx/bin/Safety/Logic.vhd in Library work. ERROR:HDLParsers:164 - C:/Xilinx/bin/Safety/Logic.vhd Line 10. parse error, unexpected LT, expecting BODY or IDENTIFIER WARNING:HDLParsers:3465 - Library as no units. Did not save reference file xst/work/hdllib.ref for it. ERROR: XST failed Process "Check Syntax" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/Xilinx/bin/Safety/Logic.vhd in Library work. ERROR:HDLParsers:3312 - C:/Xilinx/bin/Safety/Logic.vhd Line 133. Undefined symbol 'TCS'. ERROR:HDLParsers:1209 - C:/Xilinx/bin/Safety/Logic.vhd Line 133. TCS: Undefined symbol (last report in this block) ERROR:HDLParsers:164 - C:/Xilinx/bin/Safety/Logic.vhd Line 133. parse error, unexpected IDENTIFIER, expecting COMMA or CLOSEPAR ERROR:HDLParsers:3312 - C:/Xilinx/bin/Safety/Logic.vhd Line 152. Undefined symbol 'E'. ERROR:HDLParsers:1209 - C:/Xilinx/bin/Safety/Logic.vhd Line 152. E: Undefined symbol (last report in this block) ERROR:HDLParsers:164 - C:/Xilinx/bin/Safety/Logic.vhd Line 152. parse error, unexpected IDENTIFIER, expecting COMMA or CLOSEPAR ERROR:HDLParsers:3312 - C:/Xilinx/bin/Safety/Logic.vhd Line 174. Undefined symbol 'HORIZON'. ERROR:HDLParsers:1209 - C:/Xilinx/bin/Safety/Logic.vhd Line 174. HORIZON: Undefined symbol (last report in this block) ERROR:HDLParsers:164 - C:/Xilinx/bin/Safety/Logic.vhd Line 174. parse error, unexpected IDENTIFIER, expecting COMMA or CLOSEPAR ERROR:HDLParsers:3312 - C:/Xilinx/bin/Safety/Logic.vhd Line 187. Undefined symbol 'BRAKE'. ERROR:HDLParsers:1209 - C:/Xilinx/bin/Safety/Logic.vhd Line 187. BRAKE: Undefined symbol (last report in this block) --> Total memory usage is 48116 kilobytes ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file c:/xilinx/bin/safety/Logic.vhd in Library work. ERROR:HDLParsers:3312 - c:/xilinx/bin/safety/Logic.vhd Line 133. Undefined symbol 'TCS'. ERROR:HDLParsers:1209 - c:/xilinx/bin/safety/Logic.vhd Line 133. TCS: Undefined symbol (last report in this block) ERROR:HDLParsers:164 - c:/xilinx/bin/safety/Logic.vhd Line 133. parse error, unexpected IDENTIFIER, expecting COMMA or CLOSEPAR ERROR:HDLParsers:3312 - c:/xilinx/bin/safety/Logic.vhd Line 152. Undefined symbol 'E'. ERROR:HDLParsers:1209 - c:/xilinx/bin/safety/Logic.vhd Line 152. E: Undefined symbol (last report in this block) ERROR:HDLParsers:164 - c:/xilinx/bin/safety/Logic.vhd Line 152. parse error, unexpected IDENTIFIER, expecting COMMA or CLOSEPAR ERROR:HDLParsers:3312 - c:/xilinx/bin/safety/Logic.vhd Line 174. Undefined symbol 'HORIZON'. ERROR:HDLParsers:1209 - c:/xilinx/bin/safety/Logic.vhd Line 174. HORIZON: Undefined symbol (last report in this block) ERROR:HDLParsers:164 - c:/xilinx/bin/safety/Logic.vhd Line 174. parse error, unexpected IDENTIFIER, expecting COMMA or CLOSEPAR ERROR:HDLParsers:3312 - c:/xilinx/bin/safety/Logic.vhd Line 187. Undefined symbol 'BRAKE'. ERROR:HDLParsers:1209 - c:/xilinx/bin/safety/Logic.vhd Line 187. BRAKE: Undefined symbol (last report in this block) --> Total memory usage is 48116 kilobytes ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file c:/xilinx/bin/safety/Logic.vhd in Library work. ERROR:HDLParsers:3312 - c:/xilinx/bin/safety/Logic.vhd Line 155. Undefined symbol 'STHERM_DIS'. ERROR:HDLParsers:1209 - c:/xilinx/bin/safety/Logic.vhd Line 155. STHERM_DIS: Undefined symbol (last report in this block) ERROR:HDLParsers:3312 - c:/xilinx/bin/safety/Logic.vhd Line 156. Undefined symbol 'DM_1_THERM'. ERROR:HDLParsers:1209 - c:/xilinx/bin/safety/Logic.vhd Line 156. DM_1_THERM: Undefined symbol (last report in this block) ERROR:HDLParsers:164 - c:/xilinx/bin/safety/Logic.vhd Line 156. parse error, unexpected IDENTIFIER, expecting COMMA or CLOSEPAR --> Total memory usage is 48116 kilobytes ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file c:/xilinx/bin/safety/Logic.vhd in Library work. Entity (Architecture ) compiled. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). WARNING:Xst:37 - Unknown property "VHDLIB_SIM". WARNING:Xst:766 - c:/xilinx/bin/safety/Logic.vhd line 130: Generating a Black Box for component . WARNING:Xst:37 - Unknown property "VHDLIB_SIM". WARNING:Xst:766 - c:/xilinx/bin/safety/Logic.vhd line 140: Generating a Black Box for component . WARNING:Xst:37 - Unknown property "VHDLIB_SIM". WARNING:Xst:766 - c:/xilinx/bin/safety/Logic.vhd line 148: Generating a Black Box for component . WARNING:Xst:37 - Unknown property "VHDLIB_SIM". WARNING:Xst:766 - c:/xilinx/bin/safety/Logic.vhd line 170: Generating a Black Box for component . Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is c:/xilinx/bin/safety/Logic.vhd. WARNING:Xst:1306 - Output is never assigned. WARNING:Xst:646 - Signal is assigned but never used. Unit synthesized. ========================================================================= * Advanced HDL Synthesis * ========================================================================= Advanced RAM inference ... Advanced multiplier inference ... Advanced Registered AddSub inference ... Dynamic shift register inference ... ========================================================================= HDL Synthesis Report Found no macro ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Completed process "Synthesize". Started process "Translate". Extracting independent architecture files... Release 6.3.02i - ngdbuild G.37 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -i -p xc9500 logic.ngc logic.ngd Reading NGO file "c:/xilinx/bin/safety/logic.ngc" ... Reading component libraries for design expansion... Checking timing specifications ... Checking expanded design ... ERROR:NgdBuild:604 - logical block 'U1' with type 'OR9S' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, or the misspelling of a type name. Symbol 'OR9S' is not supported in target 'xc9500'. ERROR:NgdBuild:604 - logical block 'U2' with type 'NAND16S' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, or the misspelling of a type name. Symbol 'NAND16S' is not supported in target 'xc9500'. ERROR:NgdBuild:604 - logical block 'U4' with type 'NAND4S' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, or the misspelling of a type name. Symbol 'NAND4S' is not supported in target 'xc9500'. ERROR:NgdBuild:604 - logical block 'U3' with type 'AND2N2S' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, or the misspelling of a type name. Symbol 'AND2N2S' is not supported in target 'xc9500'. NGDBUILD Design Results Summary: Number of errors: 4 Number of warnings: 0 Total memory usage is 37752 kilobytes One or more errors were found during NGDBUILD. No NGD file will be written. Writing NGDBUILD log file "logic.bld"... Error: Process "Translate" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file c:/xilinx/bin/safety/Logic.vhd in Library work. ERROR:HDLParsers:163 - c:/xilinx/bin/safety/Logic.vhd Line 115. Unexpected symbol read: ?. ERROR:HDLParsers:163 - c:/xilinx/bin/safety/Logic.vhd Line 115. Unexpected symbol read: _. ERROR:HDLParsers:164 - c:/xilinx/bin/safety/Logic.vhd Line 115. parse error, unexpected IDENTIFIER, expecting COMMA or COLON ERROR:HDLParsers:163 - c:/xilinx/bin/safety/Logic.vhd Line 116. Unexpected symbol read: ?. ERROR:HDLParsers:163 - c:/xilinx/bin/safety/Logic.vhd Line 116. Unexpected symbol read: _. ERROR:HDLParsers:164 - c:/xilinx/bin/safety/Logic.vhd Line 116. parse error, unexpected IDENTIFIER, expecting COMMA or COLON ERROR:HDLParsers:163 - c:/xilinx/bin/safety/Logic.vhd Line 117. Unexpected symbol read: ?. ERROR:HDLParsers:163 - c:/xilinx/bin/safety/Logic.vhd Line 117. Unexpected symbol read: _. ERROR:HDLParsers:164 - c:/xilinx/bin/safety/Logic.vhd Line 117. parse error, unexpected IDENTIFIER, expecting COMMA or COLON ERROR:HDLParsers:163 - c:/xilinx/bin/safety/Logic.vhd Line 118. Unexpected symbol read: ?. ERROR:HDLParsers:163 - c:/xilinx/bin/safety/Logic.vhd Line 118. Unexpected symbol read: _. ERROR:HDLParsers:164 - c:/xilinx/bin/safety/Logic.vhd Line 118. parse error, unexpected IDENTIFIER, expecting COMMA or COLON ERROR:HDLParsers:163 - c:/xilinx/bin/safety/Logic.vhd Line 141. Unexpected symbol read: ?. ERROR:HDLParsers:163 - c:/xilinx/bin/safety/Logic.vhd Line 141. Unexpected symbol read: _. ERROR:HDLParsers:3312 - c:/xilinx/bin/safety/Logic.vhd Line 141. Undefined symbol 'PinSignal_U'. ERROR:HDLParsers:1209 - c:/xilinx/bin/safety/Logic.vhd Line 141. PinSignal_U: Undefined symbol (last report in this block) ERROR:HDLParsers:164 - c:/xilinx/bin/safety/Logic.vhd Line 141. parse error, unexpected IDENTIFIER, expecting COMMA or CLOSEPAR ERROR:HDLParsers:163 - c:/xilinx/bin/safety/Logic.vhd Line 147. Unexpected symbol read: ?. ERROR:HDLParsers:163 - c:/xilinx/bin/safety/Logic.vhd Line 147. Unexpected symbol read: _. ERROR:HDLParsers:164 - c:/xilinx/bin/safety/Logic.vhd Line 147. parse error, unexpected IDENTIFIER, expecting COMMA or CLOSEPAR ERROR:HDLParsers:163 - c:/xilinx/bin/safety/Logic.vhd Line 148. Unexpected symbol read: ?. ERROR:HDLParsers:163 - c:/xilinx/bin/safety/Logic.vhd Line 148. Unexpected symbol read: _. ERROR:HDLParsers:163 - c:/xilinx/bin/safety/Logic.vhd Line 149. Unexpected symbol read: ?. ERROR:HDLParsers:163 - c:/xilinx/bin/safety/Logic.vhd Line 149. Unexpected symbol read: _. ERROR:HDLParsers:163 - c:/xilinx/bin/safety/Logic.vhd Line 161. Unexpected symbol read: ?. ERROR:HDLParsers:163 - c:/xilinx/bin/safety/Logic.vhd Line 161. Unexpected symbol read: _. ERROR:HDLParsers:164 - c:/xilinx/bin/safety/Logic.vhd Line 161. parse error, unexpected IDENTIFIER, expecting COMMA or CLOSEPAR ERROR:HDLParsers:163 - c:/xilinx/bin/safety/Logic.vhd Line 162. Unexpected symbol read: ?. ERROR:HDLParsers:163 - c:/xilinx/bin/safety/Logic.vhd Line 162. Unexpected symbol read: _. ERROR:HDLParsers:163 - c:/xilinx/bin/safety/Logic.vhd Line 175. Unexpected symbol read: ?. ERROR:HDLParsers:163 - c:/xilinx/bin/safety/Logic.vhd Line 175. Unexpected symbol read: _. ERROR:HDLParsers:164 - c:/xilinx/bin/safety/Logic.vhd Line 175. parse error, unexpected IDENTIFIER, expecting COMMA or CLOSEPAR ERROR:HDLParsers:163 - c:/xilinx/bin/safety/Logic.vhd Line 185. Unexpected symbol read: ?. ERROR:HDLParsers:163 - c:/xilinx/bin/safety/Logic.vhd Line 185. Unexpected symbol read: _. ERROR:HDLParsers:164 - c:/xilinx/bin/safety/Logic.vhd Line 185. parse error, unexpected IDENTIFIER, expecting COMMA or CLOSEPAR ERROR:HDLParsers:163 - c:/xilinx/bin/safety/Logic.vhd Line 191. Unexpected symbol read: ?. ERROR:HDLParsers:163 - c:/xilinx/bin/safety/Logic.vhd Line 191. Unexpected symbol read: _. ERROR:HDLParsers:164 - c:/xilinx/bin/safety/Logic.vhd Line 191. parse error, unexpected IDENTIFIER, expecting COMMA or CLOSEPAR ERROR:HDLParsers:163 - c:/xilinx/bin/safety/Logic.vhd Line 192. Unexpected symbol read: ?. ERROR:HDLParsers:163 - c:/xilinx/bin/safety/Logic.vhd Line 192. Unexpected symbol read: _. ERROR:HDLParsers:163 - c:/xilinx/bin/safety/Logic.vhd Line 193. Unexpected symbol read: ?. ERROR:HDLParsers:163 - c:/xilinx/bin/safety/Logic.vhd Line 193. Unexpected symbol read: _. ERROR:HDLParsers:163 - c:/xilinx/bin/safety/Logic.vhd Line 198. Unexpected symbol read: ?. ERROR:HDLParsers:163 - c:/xilinx/bin/safety/Logic.vhd Line 198. Unexpected symbol read: _. ERROR:HDLParsers:164 - c:/xilinx/bin/safety/Logic.vhd Line 198. parse error, unexpected IDENTIFIER, expecting SEMICOLON ERROR:HDLParsers:163 - c:/xilinx/bin/safety/Logic.vhd Line 199. Unexpected symbol read: ?. ERROR:HDLParsers:163 - c:/xilinx/bin/safety/Logic.vhd Line 199. Unexpected symbol read: _. ERROR:HDLParsers:164 - c:/xilinx/bin/safety/Logic.vhd Line 199. parse error, unexpected IDENTIFIER, expecting SEMICOLON ERROR:HDLParsers:163 - c:/xilinx/bin/safety/Logic.vhd Line 200. Unexpected symbol read: ?. ERROR:HDLParsers:163 - c:/xilinx/bin/safety/Logic.vhd Line 200. Unexpected symbol read: _. ERROR:HDLParsers:164 - c:/xilinx/bin/safety/Logic.vhd Line 200. parse error, unexpected IDENTIFIER, expecting SEMICOLON --> Total memory usage is 48116 kilobytes ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file c:/xilinx/bin/safety/Logic.vhd in Library work. Entity (Architecture ) compiled. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). WARNING:Xst:37 - Unknown property "Datasheet". WARNING:Xst:766 - c:/xilinx/bin/safety/Logic.vhd line 131: Generating a Black Box for component . WARNING:Xst:37 - Unknown property "Datasheet". WARNING:Xst:766 - c:/xilinx/bin/safety/Logic.vhd line 141: Generating a Black Box for component . WARNING:Xst:37 - Unknown property "Datasheet". WARNING:Xst:766 - c:/xilinx/bin/safety/Logic.vhd line 149: Generating a Black Box for component . WARNING:Xst:37 - Unknown property "Datasheet". WARNING:Xst:766 - c:/xilinx/bin/safety/Logic.vhd line 164: Generating a Black Box for component . WARNING:Xst:37 - Unknown property "Datasheet". WARNING:Xst:766 - c:/xilinx/bin/safety/Logic.vhd line 172: Generating a Black Box for component . WARNING:Xst:37 - Unknown property "Datasheet". WARNING:Xst:766 - c:/xilinx/bin/safety/Logic.vhd line 185: Generating a Black Box for component . Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is c:/xilinx/bin/safety/Logic.vhd. Unit synthesized. ========================================================================= * Advanced HDL Synthesis * ========================================================================= Advanced RAM inference ... Advanced multiplier inference ... Advanced Registered AddSub inference ... Dynamic shift register inference ... ========================================================================= HDL Synthesis Report Found no macro ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Completed process "Synthesize". Started process "Translate". Release 6.3.02i - ngdbuild G.37 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -i -p xc9500 logic.ngc logic.ngd Reading NGO file "c:/xilinx/bin/safety/logic.ngc" ... Reading component libraries for design expansion... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 37752 kilobytes Writing NGD file "logic.ngd" ... Writing NGDBUILD log file "logic.bld"... NGDBUILD done. Completed process "Translate". Started process "Fit". Release 6.3.02i - CPLD Optimizer/Partitioner G.37 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Considering device XC9536-5-PC44. Flattening design.. Timing optimization Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 3 equations into 2 function blocks.... Design logic has been optimized and fit into device XC9536-5-PC44. Completed process "Fit". Started process "Generate Programming File". Release 6.3.02i - Programming File Generator G.37 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Completed process "Generate Programming File". Started process "Generate HTML report". Release 6.3.02i - CPLD HTML Report Processor G.37 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Project Navigator Auto-Make Log File ------------------------------------- Project Navigator Auto-Make Log File ------------------------------------- Project Navigator Auto-Make Log File ------------------------------------- Started process "Generate Timing". Release 6.3.02i - Timing Report Generator G.37 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Path tracing ..... The number of paths traced: 52. The number of paths traced: 105. Generating TA GUI report ... Generating detailed paths report ... Generating asynchronous checking report ... c:\xilinx\bin\safety/logic_html/tim/timing_report.htm has been created. c:\xilinx\bin\safety/logic_html/tim/timing_report.htm has been created. Completed process "Generate Timing". Started process "Generate HTML report". Release 6.3.02i - CPLD HTML Report Processor G.37 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Project Navigator Auto-Make Log File ------------------------------------- Started process "Generate Post-Fit Simulation Model". Release 6.3.02i - CPLD Timing Simulation Interface G.37 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Creating NGA for simulation. Speed File: Version 3.0 Completed process "Generate Post-Fit Simulation Model". Release 6.3.02i - netgen G.37 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Reading design logic.nga ... Flattening design ... Flattening design completed. Specializing design ... Specializing design completed. Preping physical only global signals ... Preping design's networks ... Preping design's macros ... Writing VHDL netlist logic_timesim.vhd ... Writing VHDL SDF file logic_timesim.sdf ... Total memory usage is 35540 kilobytes Created netgen log file 'logic_timesim.nlf'. Completed process "Generate Post-Fit Simulation Model". Project Navigator Auto-Make Log File ------------------------------------- Started process "Generate IBIS Model". Completed process "Generate IBIS Model". Project Navigator Auto-Make Log File ------------------------------------- Project Navigator Auto-Make Log File ------------------------------------- Started process "Lock Pins". pin2ucf: Xilinx Pin Locker G.35.Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Pin Locking constraints file generated in : logic_locked.ucf Completed process "Lock Pins". Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= WARNING:HDLParsers:3215 - Unit work/LOGIC is now defined in a different file: was c:/xilinx/bin/safety/Logic.vhd, now is C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD WARNING:HDLParsers:3215 - Unit work/LOGIC/STRUCTURE is now defined in a different file: was c:/xilinx/bin/safety/Logic.vhd, now is C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD Compiling vhdl file C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD in Library work. Entity (Architecture ) compiled. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 176: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 184: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 192: Generating a Black Box for component . WARNING:Xst:37 - Unknown property "Datasheet". WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 202: Generating a Black Box for component . WARNING:Xst:37 - Unknown property "Datasheet". WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 211: Generating a Black Box for component . WARNING:Xst:37 - Unknown property "Datasheet". WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 219: Generating a Black Box for component . WARNING:Xst:37 - Unknown property "Datasheet". WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 227: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 235: Generating a Black Box for component . WARNING:Xst:37 - Unknown property "Datasheet". WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 243: Generating a Black Box for component . WARNING:Xst:37 - Unknown property "Datasheet". WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 258: Generating a Black Box for component . WARNING:Xst:37 - Unknown property "Datasheet". WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 273: Generating a Black Box for component . Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD. Unit synthesized. ========================================================================= * Advanced HDL Synthesis * ========================================================================= Advanced RAM inference ... Advanced multiplier inference ... Advanced Registered AddSub inference ... Dynamic shift register inference ... ========================================================================= HDL Synthesis Report Found no macro ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Completed process "Synthesize". Started process "Translate". Release 6.3.03i - ngdbuild G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -i -p xc9500 logic.ngc logic.ngd Reading NGO file "C:/Xilinx/bin/Safety/logic.ngc" ... Reading component libraries for design expansion... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 37728 kilobytes Writing NGD file "logic.ngd" ... Writing NGDBUILD log file "logic.bld"... NGDBUILD done. Completed process "Translate". Started process "Fit". Release 6.3.03i - CPLD Optimizer/Partitioner G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Considering device XC9536-5-PC44. Insufficient number of input pins. This design needs at least 36 but only 31 left after allocating other resources. Device XC9536-5-PC44 was disqualified. Considering device XC9536-5-VQ44. Insufficient number of input pins. This design needs at least 36 but only 31 left after allocating other resources. Device XC9536-5-VQ44 was disqualified. Considering device XC9536-5-CS48. Insufficient number of input pins. This design needs at least 36 but only 31 left after allocating other resources. Device XC9536-5-CS48 was disqualified. Considering device XC9572-7-PC44. Insufficient number of input pins. This design needs at least 36 but only 31 left after allocating other resources. Device XC9572-7-PC44 was disqualified. Considering device XC9572-7-PC84. Flattening design.. Multi-level logic optimization... Timing optimization.. Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 3 equations into 4 function blocks......... Design logic has been optimized and fit into device XC9572-7-PC84. Completed process "Fit". Started process "Generate Programming File". Release 6.3.03i - Programming File Generator G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Completed process "Generate Programming File". Started process "Generate HTML report". Release 6.3.03i - CPLD HTML Report Processor G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Project Navigator Auto-Make Log File ------------------------------------- Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD in Library work. Entity (Architecture ) compiled. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 207: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 216: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 224: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 233: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 239: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 247: Generating a Black Box for component . WARNING:Xst:37 - Unknown property "Datasheet". WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 257: Generating a Black Box for component . WARNING:Xst:37 - Unknown property "Datasheet". WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 266: Generating a Black Box for component . WARNING:Xst:37 - Unknown property "Datasheet". WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 274: Generating a Black Box for component . WARNING:Xst:37 - Unknown property "Datasheet". WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 282: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 290: Generating a Black Box for component . WARNING:Xst:37 - Unknown property "Datasheet". WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 298: Generating a Black Box for component . WARNING:Xst:37 - Unknown property "Datasheet". WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 313: Generating a Black Box for component . WARNING:Xst:37 - Unknown property "Datasheet". WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 328: Generating a Black Box for component . Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD. Unit synthesized. ========================================================================= * Advanced HDL Synthesis * ========================================================================= Advanced RAM inference ... Advanced multiplier inference ... Advanced Registered AddSub inference ... Dynamic shift register inference ... ========================================================================= HDL Synthesis Report Found no macro ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Completed process "Synthesize". Started process "Translate". Release 6.3.03i - ngdbuild G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -i -p xc9500 logic.ngc logic.ngd Reading NGO file "C:/Xilinx/bin/Safety/logic.ngc" ... Reading component libraries for design expansion... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 37728 kilobytes Writing NGD file "logic.ngd" ... Writing NGDBUILD log file "logic.bld"... NGDBUILD done. Completed process "Translate". Started process "Fit". Release 6.3.03i - CPLD Optimizer/Partitioner G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Considering device XC9536-5-PC44. Insufficient number of input pins. This design needs at least 37 but only 31 left after allocating other resources. Device XC9536-5-PC44 was disqualified. Considering device XC9536-5-VQ44. Insufficient number of input pins. This design needs at least 37 but only 31 left after allocating other resources. Device XC9536-5-VQ44 was disqualified. Considering device XC9536-5-CS48. Insufficient number of input pins. This design needs at least 37 but only 31 left after allocating other resources. Device XC9536-5-CS48 was disqualified. Considering device XC9572-7-PC44. Insufficient number of input pins. This design needs at least 37 but only 31 left after allocating other resources. Device XC9572-7-PC44 was disqualified. Considering device XC9572-7-PC84. Flattening design.. Timing optimization........... Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 5 equations into 4 function blocks............... Design logic has been optimized and fit into device XC9572-7-PC84. Completed process "Fit". Started process "Generate Programming File". Release 6.3.03i - Programming File Generator G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Completed process "Generate Programming File". Started process "Generate HTML report". Release 6.3.03i - CPLD HTML Report Processor G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD in Library work. Entity (Architecture ) compiled. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 251: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 259: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 267: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 282: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 290: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 298: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 311: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 320: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 326: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 334: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 342: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 350: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 358: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 371: Generating a Black Box for component . WARNING:Xst:37 - Unknown property "Datasheet". WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 379: Generating a Black Box for component . WARNING:Xst:37 - Unknown property "Datasheet". WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 387: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 402: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 411: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 419: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 427: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 435: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 443: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 451: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 459: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 467: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 475: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 483: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 491: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 499: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 507: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 515: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 523: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 531: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 539: Generating a Black Box for component . Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD. Unit synthesized. ========================================================================= * Advanced HDL Synthesis * ========================================================================= Advanced RAM inference ... Advanced multiplier inference ... Advanced Registered AddSub inference ... Dynamic shift register inference ... ========================================================================= HDL Synthesis Report Found no macro ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Completed process "Synthesize". Started process "Translate". Release 6.3.03i - ngdbuild G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -i -p xc9500 logic.ngc logic.ngd Reading NGO file "C:/Xilinx/bin/Safety/logic.ngc" ... Reading component libraries for design expansion... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 37728 kilobytes Writing NGD file "logic.ngd" ... Writing NGDBUILD log file "logic.bld"... NGDBUILD done. Completed process "Translate". Started process "Fit". Release 6.3.03i - CPLD Optimizer/Partitioner G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Considering device XC9536-5-PC44. Insufficient number of input pins. This design needs at least 36 but only 8 left after allocating other resources. Device XC9536-5-PC44 was disqualified. Considering device XC9536-5-VQ44. Insufficient number of input pins. This design needs at least 36 but only 8 left after allocating other resources. Device XC9536-5-VQ44 was disqualified. Considering device XC9536-5-CS48. Insufficient number of input pins. This design needs at least 36 but only 8 left after allocating other resources. Device XC9536-5-CS48 was disqualified. Considering device XC9572-7-PC44. Insufficient number of input pins. This design needs at least 36 but only 8 left after allocating other resources. Device XC9572-7-PC44 was disqualified. Considering device XC9572-7-PC84. Flattening design.. Multi-level logic optimization... Timing optimization........... Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 28 equations into 4 function blocks......................... Design logic has been optimized and fit into device XC9572-7-PC84. Completed process "Fit". Started process "Generate HTML report". Release 6.3.03i - CPLD HTML Report Processor G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Project Navigator Auto-Make Log File ------------------------------------- Project Navigator Auto-Make Log File ------------------------------------- Started process "Generate Programming File". Release 6.3.03i - Programming File Generator G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Completed process "Generate Programming File". Project Navigator Auto-Make Log File ------------------------------------- Started process "Lock Pins". pin2ucf: Xilinx Pin Locker G.35.Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. ERROR:Pin2Ucf - pin2ucf found that the UCF file for this design already have some pin locking constraints. Since pin2ucf will not overwrite user constraints, please check the UCF file and remove those constraints before trying pin2ucf again. You could also delete the UCF file before trying again. To get a listing of all possible conflicts among constraints for this design please check the pin2ucf report file: logic.lck Process "Lock Pins" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD in Library work. Architecture structure of Entity logic is up to date. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 251: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 259: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 267: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 282: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 290: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 298: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 311: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 320: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 326: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 334: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 342: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 350: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 358: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 371: Generating a Black Box for component . WARNING:Xst:37 - Unknown property "Datasheet". WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 379: Generating a Black Box for component . WARNING:Xst:37 - Unknown property "Datasheet". WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 387: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 402: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 411: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 419: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 427: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 435: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 443: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 451: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 459: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 467: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 475: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 483: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 491: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 499: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 507: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 515: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 523: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 531: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 539: Generating a Black Box for component . Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD. Unit synthesized. ========================================================================= * Advanced HDL Synthesis * ========================================================================= Advanced RAM inference ... Advanced multiplier inference ... Advanced Registered AddSub inference ... Dynamic shift register inference ... ========================================================================= HDL Synthesis Report Found no macro ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Completed process "Synthesize". Started process "Translate". Release 6.3.03i - ngdbuild G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -i -p xc9500 logic.ngc logic.ngd Reading NGO file "c:/xilinx/bin/safety/logic.ngc" ... Reading component libraries for design expansion... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 37728 kilobytes Writing NGD file "logic.ngd" ... Writing NGDBUILD log file "logic.bld"... NGDBUILD done. Completed process "Translate". Started process "Fit". Release 6.3.03i - CPLD Optimizer/Partitioner G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Considering device XC9536-5-PC44. Insufficient number of input pins. This design needs at least 36 but only 8 left after allocating other resources. Device XC9536-5-PC44 was disqualified. Considering device XC9536-5-VQ44. Insufficient number of input pins. This design needs at least 36 but only 8 left after allocating other resources. Device XC9536-5-VQ44 was disqualified. Considering device XC9536-5-CS48. Insufficient number of input pins. This design needs at least 36 but only 8 left after allocating other resources. Device XC9536-5-CS48 was disqualified. Considering device XC9572-7-PC44. Insufficient number of input pins. This design needs at least 36 but only 8 left after allocating other resources. Device XC9572-7-PC44 was disqualified. Considering device XC9572-7-PC84. Flattening design.. Multi-level logic optimization... Timing optimization........... Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 28 equations into 4 function blocks......................... Design logic has been optimized and fit into device XC9572-7-PC84. Completed process "Fit". Started process "Generate Programming File". Release 6.3.03i - Programming File Generator G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Completed process "Generate Programming File". Project Navigator Auto-Make Log File ------------------------------------- Started process "Lock Pins". pin2ucf: Xilinx Pin Locker G.35.Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. ERROR:Pin2Ucf - pin2ucf found that the UCF file for this design already have some pin locking constraints. Since pin2ucf will not overwrite user constraints, please check the UCF file and remove those constraints before trying pin2ucf again. You could also delete the UCF file before trying again. To get a listing of all possible conflicts among constraints for this design please check the pin2ucf report file: logic.lck Process "Lock Pins" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Lock Pins". pin2ucf: Xilinx Pin Locker G.35.Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Pin Locking constraints file generated in : logic_locked.ucf Completed process "Lock Pins". Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD in Library work. Entity (Architecture ) compiled. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 275: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 283: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 294: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 302: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 313: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 321: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 329: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 338: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 349: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 355: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 363: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 371: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 381: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 389: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 397: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 407: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 419: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 427: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 438: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 446: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 456: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 464: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 472: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 480: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 488: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 496: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 504: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 512: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 520: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 528: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 536: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 544: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 552: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 560: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 568: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 576: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 584: Generating a Black Box for component . Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD. Unit synthesized. ========================================================================= * Advanced HDL Synthesis * ========================================================================= Advanced RAM inference ... Advanced multiplier inference ... Advanced Registered AddSub inference ... Dynamic shift register inference ... ========================================================================= HDL Synthesis Report Found no macro ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Completed process "Synthesize". Started process "Translate". Release 6.3.03i - ngdbuild G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -i -p xc9500 logic.ngc logic.ngd Reading NGO file "C:/Xilinx/bin/Safety/logic.ngc" ... Reading component libraries for design expansion... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 37728 kilobytes Writing NGD file "logic.ngd" ... Writing NGDBUILD log file "logic.bld"... NGDBUILD done. Completed process "Translate". Started process "Fit". Release 6.3.03i - CPLD Optimizer/Partitioner G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Considering device XC9536-5-PC44. Insufficient number of input pins. This design needs at least 36 but only 8 left after allocating other resources. Device XC9536-5-PC44 was disqualified. Considering device XC9536-5-VQ44. Insufficient number of input pins. This design needs at least 36 but only 8 left after allocating other resources. Device XC9536-5-VQ44 was disqualified. Considering device XC9536-5-CS48. Insufficient number of input pins. This design needs at least 36 but only 8 left after allocating other resources. Device XC9536-5-CS48 was disqualified. Considering device XC9572-7-PC44. Insufficient number of input pins. This design needs at least 36 but only 8 left after allocating other resources. Device XC9572-7-PC44 was disqualified. Considering device XC9572-7-PC84. Flattening design.. Multi-level logic optimization... Timing optimization.............. Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 28 equations into 4 function blocks......................... Design logic has been optimized and fit into device XC9572-7-PC84. Completed process "Fit". Started process "Generate Programming File". Release 6.3.03i - Programming File Generator G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Completed process "Generate Programming File". Started process "Generate HTML report". Release 6.3.03i - CPLD HTML Report Processor G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Project Navigator Auto-Make Log File ------------------------------------- Started process "Lock Pins". pin2ucf: Xilinx Pin Locker G.35.Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Pin Locking constraints file generated in : logic_locked.ucf Completed process "Lock Pins". Project Navigator Auto-Make Log File ------------------------------------- Started process "Compile HDL Simulation Libraries". Release 6.3.01i - compxlib XILINX = 'C:\Xilinx' SIMULATOR = MODELSIM SE/EE Source Tools => [null] ERROR:cxl[env]:11- unable to find simulator (mti_se) executables : If you are compiling simulation libraries in ISE-GUI then, specify the simulator executable path in the "Simulator Path" property under "Compile HDL Simulation Libraries" properties. If you are compiling simulation libraries using compxlib in command line then, use the -p option to specify the executable path or set the COMPXLIB_SIM_PATH environment variable. For example :- -p \modeltech_5.7\win32 or COMPXLIB_SIM_PATH = \modeltech_5.7\win32 IMPORTANT: Make sure that the license file/other environment variable for mti_se are properly set compxlib.log generated. Completed process "Compile HDL Simulation Libraries". Project Navigator Auto-Make Log File ------------------------------------- Started process "HDL Converter". ERROR: No input file specified for the "HDL Converter" process. Please select an input file (ABEL or AHDL) from the property menu. (Right click on the "HDL Converter" process name and select 'Properties') Process "HDL Converter" did not complete due to error(s) reported by internal script. Project Navigator Auto-Make Log File ------------------------------------- ERROR : Please specify a 'TDO Input File' in the 'TDO Converter' process properties window. Project Navigator Auto-Make Log File ------------------------------------- Started process "Compile HDL Simulation Libraries". Release 6.3.01i - compxlib XILINX = 'C:\Xilinx' SIMULATOR = MODELSIM SE/EE Source Tools => [null] ERROR:cxl[env]:11- unable to find simulator (mti_se) executables : If you are compiling simulation libraries in ISE-GUI then, specify the simulator executable path in the "Simulator Path" property under "Compile HDL Simulation Libraries" properties. If you are compiling simulation libraries using compxlib in command line then, use the -p option to specify the executable path or set the COMPXLIB_SIM_PATH environment variable. For example :- -p \modeltech_5.7\win32 or COMPXLIB_SIM_PATH = \modeltech_5.7\win32 IMPORTANT: Make sure that the license file/other environment variable for mti_se are properly set compxlib.log generated. Completed process "Compile HDL Simulation Libraries". Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD in Library work. Entity (Architecture ) compiled. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 279: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 287: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 296: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 304: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 315: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 323: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 331: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 339: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 346: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 355: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 364: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 370: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 378: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 386: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 394: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 404: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 412: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 420: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 428: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 440: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 448: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 456: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 464: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 472: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 483: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 491: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 499: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 507: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 515: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 526: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 534: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 542: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 550: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 558: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 566: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 574: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 582: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 590: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 598: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 606: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 614: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 622: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 630: Generating a Black Box for component . Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD. Unit synthesized. ========================================================================= * Advanced HDL Synthesis * ========================================================================= Advanced RAM inference ... Advanced multiplier inference ... Advanced Registered AddSub inference ... Dynamic shift register inference ... ========================================================================= HDL Synthesis Report Found no macro ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Completed process "Synthesize". Started process "Translate". Release 6.3.03i - ngdbuild G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -i -p xc9500 logic.ngc logic.ngd Reading NGO file "C:/Xilinx/bin/Safety/logic.ngc" ... Reading component libraries for design expansion... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 37728 kilobytes Writing NGD file "logic.ngd" ... Writing NGDBUILD log file "logic.bld"... NGDBUILD done. Completed process "Translate". Started process "Fit". Release 6.3.03i - CPLD Optimizer/Partitioner G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Considering device XC9536-5-PC44. Insufficient number of input pins. This design needs at least 31 but only 3 left after allocating other resources. Device XC9536-5-PC44 was disqualified. Considering device XC9536-5-VQ44. Insufficient number of input pins. This design needs at least 31 but only 3 left after allocating other resources. Device XC9536-5-VQ44 was disqualified. Considering device XC9536-5-CS48. Insufficient number of input pins. This design needs at least 31 but only 3 left after allocating other resources. Device XC9536-5-CS48 was disqualified. Considering device XC9572-7-PC44. Insufficient number of input pins. This design needs at least 31 but only 3 left after allocating other resources. Device XC9572-7-PC44 was disqualified. Considering device XC9572-7-PC84. Flattening design.. Multi-level logic optimization... Timing optimization.............. Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 33 equations into 4 function blocks......................... Design logic has been optimized and fit into device XC9572-7-PC84. Completed process "Fit". Started process "Generate Programming File". Release 6.3.03i - Programming File Generator G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Completed process "Generate Programming File". Project Navigator Auto-Make Log File ------------------------------------- Started process "Generate HTML report". Release 6.3.03i - CPLD HTML Report Processor G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Project Navigator Auto-Make Log File ------------------------------------- Started process "Lock Pins". pin2ucf: Xilinx Pin Locker G.35.Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. ERROR:Pin2Ucf - pin2ucf found that the UCF file for this design already have some pin locking constraints. Since pin2ucf will not overwrite user constraints, please check the UCF file and remove those constraints before trying pin2ucf again. You could also delete the UCF file before trying again. To get a listing of all possible conflicts among constraints for this design please check the pin2ucf report file: logic.lck Process "Lock Pins" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Fit". Release 6.3.03i - CPLD Optimizer/Partitioner G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Considering device XC9536-5-PC44. Insufficient number of input pins. This design needs at least 31 but only 3 left after allocating other resources. Device XC9536-5-PC44 was disqualified. Considering device XC9536-5-VQ44. Insufficient number of input pins. This design needs at least 31 but only 3 left after allocating other resources. Device XC9536-5-VQ44 was disqualified. Considering device XC9536-5-CS48. Insufficient number of input pins. This design needs at least 31 but only 3 left after allocating other resources. Device XC9536-5-CS48 was disqualified. Considering device XC9572-7-PC44. Insufficient number of input pins. This design needs at least 31 but only 3 left after allocating other resources. Device XC9572-7-PC44 was disqualified. Considering device XC9572-7-PC84. Flattening design.. Multi-level logic optimization... Timing optimization.............. Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 33 equations into 4 function blocks......................... Design logic has been optimized and fit into device XC9572-7-PC84. Completed process "Fit". Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD in Library work. Architecture structure of Entity logic is up to date. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 279: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 287: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 296: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 304: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 315: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 323: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 331: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 339: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 346: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 355: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 364: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 370: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 378: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 386: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 394: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 404: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 412: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 420: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 428: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 440: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 448: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 456: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 464: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 472: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 483: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 491: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 499: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 507: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 515: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 526: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 534: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 542: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 550: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 558: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 566: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 574: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 582: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 590: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 598: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 606: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 614: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 622: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 630: Generating a Black Box for component . Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD. Unit synthesized. ========================================================================= * Advanced HDL Synthesis * ========================================================================= Advanced RAM inference ... Advanced multiplier inference ... Advanced Registered AddSub inference ... Dynamic shift register inference ... ========================================================================= HDL Synthesis Report Found no macro ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Completed process "Synthesize". Started process "Translate". Release 6.3.03i - ngdbuild G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -uc logic.ucf -p xc9500 logic.ngc logic.ngd Reading NGO file "C:/Xilinx/bin/Safety/logic.ngc" ... Reading component libraries for design expansion... Annotating constraints to design from file "logic.ucf" ... ERROR:NgdBuild:755 - Line 61 in 'logic.ucf': Could not find net(s) 'DEC_ STOP_S_LATCH' in the design. To suppress this error specify the correct net name or remove the constraint. The 'Ignore I\O constraints on Invalid Object Names' property can also be set ( -aul switch for command line users). ERROR:Parsers:11 - Encountered unrecognized constraint while parsing. ERROR:NgdBuild:19 - Errors found while parsing constraint file "logic.ucf". Writing NGDBUILD log file "logic.bld"... Error: Process "Translate" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD in Library work. Architecture structure of Entity logic is up to date. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 279: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 287: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 296: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 304: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 315: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 323: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 331: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 339: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 346: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 355: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 364: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 370: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 378: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 386: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 394: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 404: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 412: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 420: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 428: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 440: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 448: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 456: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 464: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 472: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 483: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 491: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 499: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 507: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 515: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 526: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 534: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 542: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 550: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 558: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 566: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 574: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 582: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 590: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 598: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 606: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 614: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 622: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 630: Generating a Black Box for component . Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD. Unit synthesized. ========================================================================= * Advanced HDL Synthesis * ========================================================================= Advanced RAM inference ... Advanced multiplier inference ... Advanced Registered AddSub inference ... Dynamic shift register inference ... ========================================================================= HDL Synthesis Report Found no macro ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Completed process "Synthesize". Started process "Translate". Release 6.3.03i - ngdbuild G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -i -p xc9500 logic.ngc logic.ngd Reading NGO file "C:/Xilinx/bin/Safety/logic.ngc" ... Reading component libraries for design expansion... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 37728 kilobytes Writing NGD file "logic.ngd" ... Writing NGDBUILD log file "logic.bld"... NGDBUILD done. Completed process "Translate". Started process "Fit". Release 6.3.03i - CPLD Optimizer/Partitioner G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Considering device XC9536-5-PC44. Insufficient number of input pins. This design needs at least 31 but only 3 left after allocating other resources. Device XC9536-5-PC44 was disqualified. Considering device XC9536-5-VQ44. Insufficient number of input pins. This design needs at least 31 but only 3 left after allocating other resources. Device XC9536-5-VQ44 was disqualified. Considering device XC9536-5-CS48. Insufficient number of input pins. This design needs at least 31 but only 3 left after allocating other resources. Device XC9536-5-CS48 was disqualified. Considering device XC9572-7-PC44. Insufficient number of input pins. This design needs at least 31 but only 3 left after allocating other resources. Device XC9572-7-PC44 was disqualified. Considering device XC9572-7-PC84. Flattening design.. Multi-level logic optimization... Timing optimization.............. Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 33 equations into 4 function blocks......................... Design logic has been optimized and fit into device XC9572-7-PC84. Completed process "Fit". Project Navigator Auto-Make Log File ------------------------------------- Started process "Translate". Release 6.3.03i - ngdbuild G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -i -p xc9500 logic.ngc logic.ngd Reading NGO file "C:/Xilinx/bin/Safety/logic.ngc" ... Reading component libraries for design expansion... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 37728 kilobytes Writing NGD file "logic.ngd" ... Writing NGDBUILD log file "logic.bld"... NGDBUILD done. Completed process "Translate". Started process "Fit". Release 6.3.03i - CPLD Optimizer/Partitioner G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Considering device XC9536-5-PC44. Insufficient number of input pins. This design needs at least 31 but only 3 left after allocating other resources. Device XC9536-5-PC44 was disqualified. Considering device XC9536-5-VQ44. Insufficient number of input pins. This design needs at least 31 but only 3 left after allocating other resources. Device XC9536-5-VQ44 was disqualified. Considering device XC9536-5-CS48. Insufficient number of input pins. This design needs at least 31 but only 3 left after allocating other resources. Device XC9536-5-CS48 was disqualified. Considering device XC9572-7-PC44. Insufficient number of input pins. This design needs at least 31 but only 3 left after allocating other resources. Device XC9572-7-PC44 was disqualified. Considering device XC9572-7-PC84. Flattening design.. Multi-level logic optimization... Timing optimization.............. Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 33 equations into 4 function blocks......................... Design logic has been optimized and fit into device XC9572-7-PC84. Completed process "Fit". Project Navigator Auto-Make Log File ------------------------------------- Started process "Translate". Release 6.3.03i - ngdbuild G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -i -p xc9500 logic.ngc logic.ngd Reading NGO file "C:/Xilinx/bin/Safety/logic.ngc" ... Reading component libraries for design expansion... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 37728 kilobytes Writing NGD file "logic.ngd" ... Writing NGDBUILD log file "logic.bld"... NGDBUILD done. Completed process "Translate". Started process "Fit". Release 6.3.03i - CPLD Optimizer/Partitioner G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Considering device XC9536-5-PC44. Insufficient number of input pins. This design needs at least 31 but only 3 left after allocating other resources. Device XC9536-5-PC44 was disqualified. Considering device XC9536-5-VQ44. Insufficient number of input pins. This design needs at least 31 but only 3 left after allocating other resources. Device XC9536-5-VQ44 was disqualified. Considering device XC9536-5-CS48. Insufficient number of input pins. This design needs at least 31 but only 3 left after allocating other resources. Device XC9536-5-CS48 was disqualified. Considering device XC9572-7-PC44. Insufficient number of input pins. This design needs at least 31 but only 3 left after allocating other resources. Device XC9572-7-PC44 was disqualified. Considering device XC9572-7-PC84. Flattening design.. Multi-level logic optimization... Timing optimization.............. Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 33 equations into 4 function blocks......................... Design logic has been optimized and fit into device XC9572-7-PC84. Completed process "Fit". Started process "Generate HTML report". Release 6.3.03i - CPLD HTML Report Processor G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Project Navigator Auto-Make Log File ------------------------------------- Started process "Translate". Release 6.3.03i - ngdbuild G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -i -p xc9500 logic.ngc logic.ngd Reading NGO file "C:/Xilinx/bin/Safety/logic.ngc" ... Reading component libraries for design expansion... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 37728 kilobytes Writing NGD file "logic.ngd" ... Writing NGDBUILD log file "logic.bld"... NGDBUILD done. Completed process "Translate". Started process "Fit". Release 6.3.03i - CPLD Optimizer/Partitioner G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Considering device XC9536-5-PC44. Insufficient number of input pins. This design needs at least 31 but only 3 left after allocating other resources. Device XC9536-5-PC44 was disqualified. Considering device XC9536-5-VQ44. Insufficient number of input pins. This design needs at least 31 but only 3 left after allocating other resources. Device XC9536-5-VQ44 was disqualified. Considering device XC9536-5-CS48. Insufficient number of input pins. This design needs at least 31 but only 3 left after allocating other resources. Device XC9536-5-CS48 was disqualified. Considering device XC9572-7-PC44. Insufficient number of input pins. This design needs at least 31 but only 3 left after allocating other resources. Device XC9572-7-PC44 was disqualified. Considering device XC9572-7-PC84. Flattening design.. Multi-level logic optimization... Timing optimization.............. Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 33 equations into 4 function blocks......................... Design logic has been optimized and fit into device XC9572-7-PC84. Completed process "Fit". Project Navigator Auto-Make Log File ------------------------------------- Started process "Translate". Release 6.3.03i - ngdbuild G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -i -p xc9500 logic.ngc logic.ngd Reading NGO file "C:/Xilinx/bin/Safety/logic.ngc" ... Reading component libraries for design expansion... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 37728 kilobytes Writing NGD file "logic.ngd" ... Writing NGDBUILD log file "logic.bld"... NGDBUILD done. Completed process "Translate". Started process "Fit". Release 6.3.03i - CPLD Optimizer/Partitioner G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Considering device XC9536-5-PC44. Insufficient number of input pins. This design needs at least 31 but only 3 left after allocating other resources. Device XC9536-5-PC44 was disqualified. Considering device XC9536-5-VQ44. Insufficient number of input pins. This design needs at least 31 but only 3 left after allocating other resources. Device XC9536-5-VQ44 was disqualified. Considering device XC9536-5-CS48. Insufficient number of input pins. This design needs at least 31 but only 3 left after allocating other resources. Device XC9536-5-CS48 was disqualified. Considering device XC9572-7-PC44. Insufficient number of input pins. This design needs at least 31 but only 3 left after allocating other resources. Device XC9572-7-PC44 was disqualified. Considering device XC9572-7-PC84. Flattening design.. Multi-level logic optimization... Timing optimization.............. Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 33 equations into 4 function blocks......................... Design logic has been optimized and fit into device XC9572-7-PC84. Completed process "Fit". Started process "Generate Programming File". Release 6.3.03i - Programming File Generator G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Completed process "Generate Programming File". Started process "Generate HTML report". Release 6.3.03i - CPLD HTML Report Processor G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Project Navigator Auto-Make Log File ------------------------------------- Started process "Translate". Release 6.3.03i - ngdbuild G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -i -p xc9500 logic.ngc logic.ngd Reading NGO file "C:/Xilinx/bin/Safety/logic.ngc" ... Reading component libraries for design expansion... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 37728 kilobytes Writing NGD file "logic.ngd" ... Writing NGDBUILD log file "logic.bld"... NGDBUILD done. Completed process "Translate". Started process "Fit". Release 6.3.03i - CPLD Optimizer/Partitioner G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Considering device XC9536-5-PC44. Insufficient number of input pins. This design needs at least 31 but only 3 left after allocating other resources. Device XC9536-5-PC44 was disqualified. Considering device XC9536-5-VQ44. Insufficient number of input pins. This design needs at least 31 but only 3 left after allocating other resources. Device XC9536-5-VQ44 was disqualified. Considering device XC9536-5-CS48. Insufficient number of input pins. This design needs at least 31 but only 3 left after allocating other resources. Device XC9536-5-CS48 was disqualified. Considering device XC9572-7-PC44. Insufficient number of input pins. This design needs at least 31 but only 3 left after allocating other resources. Device XC9572-7-PC44 was disqualified. Considering device XC9572-7-PC84. Flattening design.. Multi-level logic optimization... Timing optimization.............. Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 33 equations into 4 function blocks......................... Design logic has been optimized and fit into device XC9572-7-PC84. Completed process "Fit". Started process "Generate Programming File". Release 6.3.03i - Programming File Generator G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Completed process "Generate Programming File". Project Navigator Auto-Make Log File ------------------------------------- Started process "Translate". Release 6.3.03i - ngdbuild G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -i -p xc9500 logic.ngc logic.ngd Reading NGO file "C:/Xilinx/bin/Safety/logic.ngc" ... Reading component libraries for design expansion... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 37728 kilobytes Writing NGD file "logic.ngd" ... Writing NGDBUILD log file "logic.bld"... NGDBUILD done. Completed process "Translate". Started process "Fit". Release 6.3.03i - CPLD Optimizer/Partitioner G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Considering device XC9536-5-PC44. Insufficient number of input pins. This design needs at least 31 but only 3 left after allocating other resources. Device XC9536-5-PC44 was disqualified. Considering device XC9536-5-VQ44. Insufficient number of input pins. This design needs at least 31 but only 3 left after allocating other resources. Device XC9536-5-VQ44 was disqualified. Considering device XC9536-5-CS48. Insufficient number of input pins. This design needs at least 31 but only 3 left after allocating other resources. Device XC9536-5-CS48 was disqualified. Considering device XC9572-7-PC44. Insufficient number of input pins. This design needs at least 31 but only 3 left after allocating other resources. Device XC9572-7-PC44 was disqualified. Considering device XC9572-7-PC84. Flattening design.. Multi-level logic optimization... Timing optimization.............. Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 33 equations into 4 function blocks......................... Design logic has been optimized and fit into device XC9572-7-PC84. Completed process "Fit". Project Navigator Auto-Make Log File ------------------------------------- Started process "Translate". Release 6.3.03i - ngdbuild G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -i -p xc9500 logic.ngc logic.ngd Reading NGO file "C:/Xilinx/bin/Safety/logic.ngc" ... Reading component libraries for design expansion... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 37728 kilobytes Writing NGD file "logic.ngd" ... Writing NGDBUILD log file "logic.bld"... NGDBUILD done. Completed process "Translate". Project Navigator Auto-Make Log File ------------------------------------- Started process "Translate". Release 6.3.03i - ngdbuild G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -i -p xc9500 logic.ngc logic.ngd Reading NGO file "C:/Xilinx/bin/Safety/logic.ngc" ... Reading component libraries for design expansion... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 37728 kilobytes Writing NGD file "logic.ngd" ... Writing NGDBUILD log file "logic.bld"... NGDBUILD done. Completed process "Translate". Project Navigator Auto-Make Log File ------------------------------------- Started process "Fit". Release 6.3.03i - CPLD Optimizer/Partitioner G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Considering device XC9536-5-PC44. Insufficient number of input pins. This design needs at least 31 but only 3 left after allocating other resources. Device XC9536-5-PC44 was disqualified. Considering device XC9536-5-VQ44. Insufficient number of input pins. This design needs at least 31 but only 3 left after allocating other resources. Device XC9536-5-VQ44 was disqualified. Considering device XC9536-5-CS48. Insufficient number of input pins. This design needs at least 31 but only 3 left after allocating other resources. Device XC9536-5-CS48 was disqualified. Considering device XC9572-7-PC44. Insufficient number of input pins. This design needs at least 31 but only 3 left after allocating other resources. Device XC9572-7-PC44 was disqualified. Considering device XC9572-7-PC84. Flattening design.. Multi-level logic optimization... Timing optimization.............. Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 33 equations into 4 function blocks......................... Design logic has been optimized and fit into device XC9572-7-PC84. Completed process "Fit". Project Navigator Auto-Make Log File ------------------------------------- Started process "Lock Pins". pin2ucf: Xilinx Pin Locker G.35.Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. ERROR:Pin2Ucf - pin2ucf found that the UCF file for this design already have some pin locking constraints. Since pin2ucf will not overwrite user constraints, please check the UCF file and remove those constraints before trying pin2ucf again. You could also delete the UCF file before trying again. To get a listing of all possible conflicts among constraints for this design please check the pin2ucf report file: logic.lck Process "Lock Pins" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Fit". Release 6.3.03i - CPLD Optimizer/Partitioner G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Considering device XC9572-15-PC84. Flattening design.. Multi-level logic optimization... Timing optimization.............. Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 33 equations into 4 function blocks......................... Design logic has been optimized and fit into device XC9572-15-PC84. Completed process "Fit". Started process "Generate Programming File". Release 6.3.03i - Programming File Generator G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Completed process "Generate Programming File". Started process "Generate HTML report". Release 6.3.03i - CPLD HTML Report Processor G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Project Navigator Auto-Make Log File ------------------------------------- Started process "Fit". Release 6.3.03i - CPLD Optimizer/Partitioner G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Considering device XC9572-15-PC84. Flattening design.. Multi-level logic optimization... Timing optimization.............. Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 33 equations into 4 function blocks......................... Design logic has been optimized and fit into device XC9572-15-PC84. Completed process "Fit". Project Navigator Auto-Make Log File ------------------------------------- Started process "Fit". Release 6.3.03i - CPLD Optimizer/Partitioner G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Considering device XC9572-15-PC84. Flattening design.. Multi-level logic optimization... Timing optimization.............. Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 33 equations into 4 function blocks......................... Design logic has been optimized and fit into device XC9572-15-PC84. Completed process "Fit". Project Navigator Auto-Make Log File ------------------------------------- Started process "Lock Pins". pin2ucf: Xilinx Pin Locker G.35.Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Pin Locking constraints file generated in : logic_locked.ucf Completed process "Lock Pins". Project Navigator Auto-Make Log File ------------------------------------- Started process "Fit". Release 6.3.03i - CPLD Optimizer/Partitioner G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Considering device XC9572-15-PC84. Flattening design.. Multi-level logic optimization... Timing optimization.............. Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 33 equations into 4 function blocks......................... Design logic has been optimized and fit into device XC9572-15-PC84. Completed process "Fit". Project Navigator Auto-Make Log File ------------------------------------- Started process "Fit". Release 6.3.03i - CPLD Optimizer/Partitioner G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Considering device XC9572-15-PC84. Flattening design.. Multi-level logic optimization... Timing optimization.............. Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 33 equations into 4 function blocks......................... Design logic has been optimized and fit into device XC9572-15-PC84. Completed process "Fit". Project Navigator Auto-Make Log File ------------------------------------- Started process "Generate Programming File". Release 6.3.03i - Programming File Generator G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Completed process "Generate Programming File". Started process "Generate HTML report". Release 6.3.03i - CPLD HTML Report Processor G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Project Navigator Auto-Make Log File ------------------------------------- Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD in Library work. Architecture structure of Entity logic is up to date. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 279: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 287: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 296: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 304: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 315: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 323: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 331: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 339: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 346: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 355: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 364: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 370: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 378: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 386: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 394: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 404: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 412: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 420: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 428: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 440: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 448: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 456: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 464: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 472: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 483: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 491: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 499: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 507: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 515: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 526: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 534: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 542: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 550: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 558: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 566: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 574: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 582: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 590: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 598: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 606: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 614: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 622: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 630: Generating a Black Box for component . Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD. Unit synthesized. ========================================================================= * Advanced HDL Synthesis * ========================================================================= Advanced RAM inference ... Advanced multiplier inference ... Advanced Registered AddSub inference ... Dynamic shift register inference ... ========================================================================= HDL Synthesis Report Found no macro ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Completed process "Synthesize". Started process "Translate". Release 6.3.03i - ngdbuild G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -i -p xc9500 logic.ngc logic.ngd Reading NGO file "C:/Xilinx/bin/Safety/logic.ngc" ... Reading component libraries for design expansion... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 37728 kilobytes Writing NGD file "logic.ngd" ... Writing NGDBUILD log file "logic.bld"... NGDBUILD done. Completed process "Translate". Started process "Fit". Release 6.3.03i - CPLD Optimizer/Partitioner G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Considering device XC9572-15-PC84. Flattening design.. Multi-level logic optimization... Timing optimization.............. Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 33 equations into 4 function blocks......................... Design logic has been optimized and fit into device XC9572-15-PC84. Completed process "Fit". Started process "Generate Programming File". Release 6.3.03i - Programming File Generator G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Completed process "Generate Programming File". Started process "Generate HTML report". Release 6.3.03i - CPLD HTML Report Processor G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Project Navigator Auto-Make Log File ------------------------------------- Started process "Translate". Release 6.3.03i - ngdbuild G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -uc logic_locked.ucf -p xc9500 logic.ngc logic.ngd Reading NGO file "C:/Xilinx/bin/Safety/logic.ngc" ... Reading component libraries for design expansion... Annotating constraints to design from file "logic_locked.ucf" ... ERROR:NgdBuild:755 - Line 61 in 'logic_locked.ucf': Could not find net(s) 'DEC_ STOP_S_LATCH' in the design. To suppress this error specify the correct net name or remove the constraint. The 'Ignore I\O constraints on Invalid Object Names' property can also be set ( -aul switch for command line users). ERROR:Parsers:11 - Encountered unrecognized constraint while parsing. ERROR:NgdBuild:19 - Errors found while parsing constraint file "logic_locked.ucf". Writing NGDBUILD log file "logic.bld"... Error: Process "Translate" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Translate". Release 6.3.03i - ngdbuild G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -uc logic_locked.ucf -p xc9500 logic.ngc logic.ngd Reading NGO file "C:/Xilinx/bin/Safety/logic.ngc" ... Reading component libraries for design expansion... Annotating constraints to design from file "logic_locked.ucf" ... ERROR:NgdBuild:755 - Line 61 in 'logic_locked.ucf': Could not find net(s) 'DEC_ STOP_S_LATCH' in the design. To suppress this error specify the correct net name or remove the constraint. The 'Ignore I\O constraints on Invalid Object Names' property can also be set ( -aul switch for command line users). ERROR:Parsers:11 - Encountered unrecognized constraint while parsing. ERROR:NgdBuild:19 - Errors found while parsing constraint file "logic_locked.ucf". Writing NGDBUILD log file "logic.bld"... Error: Process "Translate" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD in Library work. Architecture structure of Entity logic is up to date. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 279: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 287: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 296: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 304: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 315: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 323: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 331: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 339: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 346: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 355: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 364: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 370: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 378: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 386: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 394: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 404: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 412: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 420: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 428: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 440: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 448: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 456: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 464: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 472: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 483: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 491: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 499: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 507: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 515: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 526: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 534: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 542: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 550: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 558: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 566: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 574: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 582: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 590: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 598: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 606: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 614: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 622: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 630: Generating a Black Box for component . Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD. Unit synthesized. ========================================================================= * Advanced HDL Synthesis * ========================================================================= Advanced RAM inference ... Advanced multiplier inference ... Advanced Registered AddSub inference ... Dynamic shift register inference ... ========================================================================= HDL Synthesis Report Found no macro ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Completed process "Synthesize". Started process "Translate". Release 6.3.03i - ngdbuild G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -uc logic_locked.ucf -p xc9500 logic.ngc logic.ngd Reading NGO file "C:/Xilinx/bin/Safety/logic.ngc" ... Reading component libraries for design expansion... Annotating constraints to design from file "logic_locked.ucf" ... ERROR:NgdBuild:755 - Line 61 in 'logic_locked.ucf': Could not find net(s) 'DEC_ STOP_S_LATCH' in the design. To suppress this error specify the correct net name or remove the constraint. The 'Ignore I\O constraints on Invalid Object Names' property can also be set ( -aul switch for command line users). ERROR:Parsers:11 - Encountered unrecognized constraint while parsing. ERROR:NgdBuild:19 - Errors found while parsing constraint file "logic_locked.ucf". Writing NGDBUILD log file "logic.bld"... Error: Process "Translate" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Translate". Release 6.3.03i - ngdbuild G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -uc logic_locked.ucf -p xc9500 logic.ngc logic.ngd Reading NGO file "C:/Xilinx/bin/Safety/logic.ngc" ... Reading component libraries for design expansion... Annotating constraints to design from file "logic_locked.ucf" ... ERROR:NgdBuild:755 - Line 61 in 'logic_locked.ucf': Could not find net(s) 'DEC_ STOP_S_LATCH' in the design. To suppress this error specify the correct net name or remove the constraint. The 'Ignore I\O constraints on Invalid Object Names' property can also be set ( -aul switch for command line users). ERROR:Parsers:11 - Encountered unrecognized constraint while parsing. ERROR:NgdBuild:19 - Errors found while parsing constraint file "logic_locked.ucf". Writing NGDBUILD log file "logic.bld"... Error: Process "Translate" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Translate". Release 6.3.03i - ngdbuild G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -uc logic_locked.ucf -p xc9500 logic.ngc logic.ngd Reading NGO file "C:/Xilinx/bin/Safety/logic.ngc" ... Reading component libraries for design expansion... Annotating constraints to design from file "logic_locked.ucf" ... ERROR:NgdBuild:755 - Line 61 in 'logic_locked.ucf': Could not find net(s) 'DEC_ STOP_S_LATCH' in the design. To suppress this error specify the correct net name or remove the constraint. The 'Ignore I\O constraints on Invalid Object Names' property can also be set ( -aul switch for command line users). ERROR:Parsers:11 - Encountered unrecognized constraint while parsing. ERROR:NgdBuild:19 - Errors found while parsing constraint file "logic_locked.ucf". Writing NGDBUILD log file "logic.bld"... Error: Process "Translate" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Translate". Release 6.3.03i - ngdbuild G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -uc logic_locked.ucf -p xc9500 logic.ngc logic.ngd Reading NGO file "C:/Xilinx/bin/Safety/logic.ngc" ... Reading component libraries for design expansion... Annotating constraints to design from file "logic_locked.ucf" ... ERROR:NgdBuild:755 - Line 61 in 'logic_locked.ucf': Could not find net(s) 'DEC_ STOP_S_LATCH' in the design. To suppress this error specify the correct net name or remove the constraint. The 'Ignore I\O constraints on Invalid Object Names' property can also be set ( -aul switch for command line users). ERROR:Parsers:11 - Encountered unrecognized constraint while parsing. ERROR:NgdBuild:19 - Errors found while parsing constraint file "logic_locked.ucf". Writing NGDBUILD log file "logic.bld"... Error: Process "Translate" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD in Library work. Architecture structure of Entity logic is up to date. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 279: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 287: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 296: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 304: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 315: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 323: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 331: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 339: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 346: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 355: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 364: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 370: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 378: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 386: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 394: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 404: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 412: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 420: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 428: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 440: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 448: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 456: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 464: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 472: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 483: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 491: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 499: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 507: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 515: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 526: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 534: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 542: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 550: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 558: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 566: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 574: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 582: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 590: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 598: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 606: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 614: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 622: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 630: Generating a Black Box for component . Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD. Unit synthesized. ========================================================================= * Advanced HDL Synthesis * ========================================================================= Advanced RAM inference ... Advanced multiplier inference ... Advanced Registered AddSub inference ... Dynamic shift register inference ... ========================================================================= HDL Synthesis Report Found no macro ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Completed process "Synthesize". Started process "Translate". Release 6.3.03i - ngdbuild G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -uc logic_locked.ucf -p xc9500 logic.ngc logic.ngd Reading NGO file "C:/Xilinx/bin/Safety/logic.ngc" ... Reading component libraries for design expansion... Annotating constraints to design from file "logic_locked.ucf" ... ERROR:NgdBuild:755 - Line 61 in 'logic_locked.ucf': Could not find net(s) 'DEC_ STOP_S_LATCH' in the design. To suppress this error specify the correct net name or remove the constraint. The 'Ignore I\O constraints on Invalid Object Names' property can also be set ( -aul switch for command line users). ERROR:Parsers:11 - Encountered unrecognized constraint while parsing. ERROR:NgdBuild:19 - Errors found while parsing constraint file "logic_locked.ucf". Writing NGDBUILD log file "logic.bld"... Error: Process "Translate" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD in Library work. Architecture structure of Entity logic is up to date. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 279: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 287: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 296: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 304: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 315: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 323: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 331: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 339: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 346: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 355: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 364: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 370: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 378: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 386: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 394: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 404: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 412: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 420: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 428: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 440: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 448: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 456: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 464: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 472: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 483: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 491: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 499: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 507: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 515: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 526: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 534: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 542: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 550: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 558: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 566: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 574: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 582: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 590: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 598: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 606: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 614: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 622: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 630: Generating a Black Box for component . Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD. Unit synthesized. ========================================================================= * Advanced HDL Synthesis * ========================================================================= Advanced RAM inference ... Advanced multiplier inference ... Advanced Registered AddSub inference ... Dynamic shift register inference ... ========================================================================= HDL Synthesis Report Found no macro ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Completed process "Synthesize". Started process "Translate". Release 6.3.03i - ngdbuild G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -uc logic_locked.ucf -p xc9500 logic.ngc logic.ngd Reading NGO file "C:/Xilinx/bin/Safety/logic.ngc" ... Reading component libraries for design expansion... Annotating constraints to design from file "logic_locked.ucf" ... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 39776 kilobytes Writing NGD file "logic.ngd" ... Writing NGDBUILD log file "logic.bld"... NGDBUILD done. Completed process "Translate". Started process "Fit". Release 6.3.03i - CPLD Optimizer/Partitioner G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Considering device XC9572-15-PC84. Flattening design.. Multi-level logic optimization... Timing optimization.............. Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 33 equations into 4 function blocks.... Design logic has been optimized and fit into device XC9572-15-PC84. Completed process "Fit". Started process "Generate Programming File". Release 6.3.03i - Programming File Generator G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Completed process "Generate Programming File". Started process "Generate HTML report". Release 6.3.03i - CPLD HTML Report Processor G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD in Library work. Architecture structure of Entity logic is up to date. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 279: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 287: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 296: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 304: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 315: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 323: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 331: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 339: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 346: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 355: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 364: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 370: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 378: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 386: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 394: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 404: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 412: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 420: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 428: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 440: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 448: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 456: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 464: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 472: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 483: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 491: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 499: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 507: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 515: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 526: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 534: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 542: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 550: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 558: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 566: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 574: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 582: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 590: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 598: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 606: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 614: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 622: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 630: Generating a Black Box for component . Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD. Unit synthesized. ========================================================================= * Advanced HDL Synthesis * ========================================================================= Advanced RAM inference ... Advanced multiplier inference ... Advanced Registered AddSub inference ... Dynamic shift register inference ... ========================================================================= HDL Synthesis Report Found no macro ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Completed process "Synthesize". Started process "Translate". Release 6.3.03i - ngdbuild G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -uc logic_locked.ucf -p xc9500 logic.ngc logic.ngd Reading NGO file "C:/Xilinx/bin/Safety/logic.ngc" ... Reading component libraries for design expansion... Annotating constraints to design from file "logic_locked.ucf" ... INFO:NgdBuild:738 - A case sensitive search for the INST, PAD, or NET element referred to by a constraint entry in 'logic_locked.ucf' that accompanies this design has failed, while a case insensitive search is in progress. The result of the case insensitive search will be used, but messages will accompany each and every use of a case insensitive result. Constraints are case sensitive with respect to user-specified identifiers, which includes names of logic elements in a design. INFO:NgdBuild:740 - Line 29 in 'logic_locked.ucf': Found case insensitive match for NET name 'Horizon_Stop_LATCH'. NET is 'HORIZON_STOP_LATCH'. ERROR:NgdBuild:755 - Line 35 in 'logic_locked.ucf': Could not find net(s) 'Watchdog_LATCH' in the design. To suppress this error specify the correct net name or remove the constraint. The 'Ignore I\O constraints on Invalid Object Names' property can also be set ( -aul switch for command line users). ERROR:Parsers:11 - Encountered unrecognized constraint while parsing. ERROR:NgdBuild:19 - Errors found while parsing constraint file "logic_locked.ucf". Writing NGDBUILD log file "logic.bld"... Error: Process "Translate" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD in Library work. Architecture structure of Entity logic is up to date. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 279: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 287: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 296: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 304: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 315: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 323: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 331: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 339: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 346: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 355: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 364: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 370: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 378: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 386: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 394: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 404: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 412: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 420: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 428: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 440: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 448: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 456: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 464: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 472: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 483: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 491: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 499: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 507: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 515: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 526: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 534: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 542: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 550: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 558: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 566: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 574: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 582: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 590: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 598: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 606: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 614: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 622: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 630: Generating a Black Box for component . Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD. Unit synthesized. ========================================================================= * Advanced HDL Synthesis * ========================================================================= Advanced RAM inference ... Advanced multiplier inference ... Advanced Registered AddSub inference ... Dynamic shift register inference ... ========================================================================= HDL Synthesis Report Found no macro ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Completed process "Synthesize". Started process "Translate". Release 6.3.03i - ngdbuild G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -uc logic_locked.ucf -p xc9500 logic.ngc logic.ngd Reading NGO file "C:/Xilinx/bin/Safety/logic.ngc" ... Reading component libraries for design expansion... Annotating constraints to design from file "logic_locked.ucf" ... INFO:NgdBuild:738 - A case sensitive search for the INST, PAD, or NET element referred to by a constraint entry in 'logic_locked.ucf' that accompanies this design has failed, while a case insensitive search is in progress. The result of the case insensitive search will be used, but messages will accompany each and every use of a case insensitive result. Constraints are case sensitive with respect to user-specified identifiers, which includes names of logic elements in a design. INFO:NgdBuild:740 - Line 29 in 'logic_locked.ucf': Found case insensitive match for NET name 'Horizon_Stop_LATCH'. NET is 'HORIZON_STOP_LATCH'. INFO:NgdBuild:740 - Line 35 in 'logic_locked.ucf': Found case insensitive match for NET name 'Watchdog_Timer_LATCH'. NET is 'WATCHDOG_TIMER_LATCH'. Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 39776 kilobytes Writing NGD file "logic.ngd" ... Writing NGDBUILD log file "logic.bld"... NGDBUILD done. Completed process "Translate". Started process "Fit". Release 6.3.03i - CPLD Optimizer/Partitioner G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Considering device XC9572-15-PC84. Flattening design.. Multi-level logic optimization... Timing optimization.............. Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 33 equations into 4 function blocks.... Design logic has been optimized and fit into device XC9572-15-PC84. Completed process "Fit". Started process "Generate Programming File". Release 6.3.03i - Programming File Generator G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Completed process "Generate Programming File". Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD in Library work. Entity (Architecture ) compiled. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 265: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 273: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 281: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 289: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 297: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 305: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 312: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 321: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 327: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 335: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 343: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 351: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 359: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 367: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 375: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 384: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 392: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 400: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 407: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 418: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 426: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 434: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 443: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 450: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 458: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 466: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 473: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 484: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 492: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 500: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 507: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 518: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 526: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 534: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 541: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 549: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 557: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 568: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 575: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 583: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 591: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 599: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 607: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 614: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 625: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 633: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 641: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 648: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 656: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 664: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 671: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 679: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 687: Generating a Black Box for component . Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD. Unit synthesized. ========================================================================= * Advanced HDL Synthesis * ========================================================================= Advanced RAM inference ... Advanced multiplier inference ... Advanced Registered AddSub inference ... Dynamic shift register inference ... ========================================================================= HDL Synthesis Report Found no macro ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Completed process "Synthesize". Started process "Translate". Release 6.3.03i - ngdbuild G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -uc logic_locked.ucf -p xc9500 logic.ngc logic.ngd Reading NGO file "C:/Xilinx/bin/Safety/logic.ngc" ... Reading component libraries for design expansion... Annotating constraints to design from file "logic_locked.ucf" ... INFO:NgdBuild:738 - A case sensitive search for the INST, PAD, or NET element referred to by a constraint entry in 'logic_locked.ucf' that accompanies this design has failed, while a case insensitive search is in progress. The result of the case insensitive search will be used, but messages will accompany each and every use of a case insensitive result. Constraints are case sensitive with respect to user-specified identifiers, which includes names of logic elements in a design. INFO:NgdBuild:740 - Line 29 in 'logic_locked.ucf': Found case insensitive match for NET name 'Horizon_Stop_LATCH'. NET is 'HORIZON_STOP_LATCH'. INFO:NgdBuild:740 - Line 35 in 'logic_locked.ucf': Found case insensitive match for NET name 'Watchdog_Timer_LATCH'. NET is 'WATCHDOG_TIMER_LATCH'. Checking timing specifications ... Checking expanded design ... ERROR:NgdBuild:455 - logical net 'PinSignal_U7_O' has multiple drivers. The possible drivers causing this are: pin O on block U7 with type INV, pin PAD on block PinSignal_U7_O with type PAD ERROR:NgdBuild:466 - input pad net 'PinSignal_U7_O' has illegal connection. Possible pins causing this are: pin O on block U7 with type INV ERROR:NgdBuild:455 - logical net 'PinSignal_U20_O' has multiple drivers. The possible drivers causing this are: pin O on block U20 with type INV, pin PAD on block PinSignal_U20_O with type PAD ERROR:NgdBuild:466 - input pad net 'PinSignal_U20_O' has illegal connection. Possible pins causing this are: pin O on block U20 with type INV ERROR:NgdBuild:455 - logical net 'PinSignal_U28_O' has multiple drivers. The possible drivers causing this are: pin O on block U28 with type INV, pin PAD on block PinSignal_U28_O with type PAD ERROR:NgdBuild:466 - input pad net 'PinSignal_U28_O' has illegal connection. Possible pins causing this are: pin O on block U28 with type INV ERROR:NgdBuild:455 - logical net 'PinSignal_U16_O' has multiple drivers. The possible drivers causing this are: pin O on block U16 with type INV, pin PAD on block PinSignal_U16_O with type PAD ERROR:NgdBuild:466 - input pad net 'PinSignal_U16_O' has illegal connection. Possible pins causing this are: pin O on block U16 with type INV ERROR:NgdBuild:455 - logical net 'PinSignal_U36_O' has multiple drivers. The possible drivers causing this are: pin O on block U36 with type INV, pin PAD on block PinSignal_U36_O with type PAD ERROR:NgdBuild:466 - input pad net 'PinSignal_U36_O' has illegal connection. Possible pins causing this are: pin O on block U36 with type INV ERROR:NgdBuild:455 - logical net 'PinSignal_U4_O' has multiple drivers. The possible drivers causing this are: pin O on block U4 with type INV, pin PAD on block PinSignal_U4_O with type PAD ERROR:NgdBuild:466 - input pad net 'PinSignal_U4_O' has illegal connection. Possible pins causing this are: pin O on block U4 with type INV ERROR:NgdBuild:455 - logical net 'PinSignal_U24_O' has multiple drivers. The possible drivers causing this are: pin O on block U24 with type INV, pin PAD on block PinSignal_U24_O with type PAD ERROR:NgdBuild:466 - input pad net 'PinSignal_U24_O' has illegal connection. Possible pins causing this are: pin O on block U24 with type INV ERROR:NgdBuild:455 - logical net 'PinSignal_U1_O' has multiple drivers. The possible drivers causing this are: pin O on block U1 with type INV, pin PAD on block PinSignal_U1_O with type PAD ERROR:NgdBuild:466 - input pad net 'PinSignal_U1_O' has illegal connection. Possible pins causing this are: pin O on block U1 with type INV ERROR:NgdBuild:455 - logical net 'PinSignal_U11_O' has multiple drivers. The possible drivers causing this are: pin O on block U11 with type INV, pin PAD on block PinSignal_U11_O with type PAD ERROR:NgdBuild:466 - input pad net 'PinSignal_U11_O' has illegal connection. Possible pins causing this are: pin O on block U11 with type INV ERROR:NgdBuild:455 - logical net 'PinSignal_U31_O' has multiple drivers. The possible drivers causing this are: pin O on block U31 with type INV, pin PAD on block PinSignal_U31_O with type PAD ERROR:NgdBuild:466 - input pad net 'PinSignal_U31_O' has illegal connection. Possible pins causing this are: pin O on block U31 with type INV NGDBUILD Design Results Summary: Number of errors: 20 Number of warnings: 0 Total memory usage is 39776 kilobytes One or more errors were found during NGDBUILD. No NGD file will be written. Writing NGDBUILD log file "logic.bld"... Error: Process "Translate" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Translate". Release 6.3.03i - ngdbuild G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -uc logic_locked.ucf -p xc9500 logic.ngc logic.ngd Reading NGO file "c:/xilinx/bin/safety/logic.ngc" ... Reading component libraries for design expansion... Annotating constraints to design from file "logic_locked.ucf" ... INFO:NgdBuild:738 - A case sensitive search for the INST, PAD, or NET element referred to by a constraint entry in 'logic_locked.ucf' that accompanies this design has failed, while a case insensitive search is in progress. The result of the case insensitive search will be used, but messages will accompany each and every use of a case insensitive result. Constraints are case sensitive with respect to user-specified identifiers, which includes names of logic elements in a design. INFO:NgdBuild:740 - Line 29 in 'logic_locked.ucf': Found case insensitive match for NET name 'Horizon_Stop_LATCH'. NET is 'HORIZON_STOP_LATCH'. INFO:NgdBuild:740 - Line 35 in 'logic_locked.ucf': Found case insensitive match for NET name 'Watchdog_Timer_LATCH'. NET is 'WATCHDOG_TIMER_LATCH'. Checking timing specifications ... Checking expanded design ... ERROR:NgdBuild:455 - logical net 'PinSignal_U7_O' has multiple drivers. The possible drivers causing this are: pin O on block U7 with type INV, pin PAD on block PinSignal_U7_O with type PAD ERROR:NgdBuild:466 - input pad net 'PinSignal_U7_O' has illegal connection. Possible pins causing this are: pin O on block U7 with type INV ERROR:NgdBuild:455 - logical net 'PinSignal_U20_O' has multiple drivers. The possible drivers causing this are: pin O on block U20 with type INV, pin PAD on block PinSignal_U20_O with type PAD ERROR:NgdBuild:466 - input pad net 'PinSignal_U20_O' has illegal connection. Possible pins causing this are: pin O on block U20 with type INV ERROR:NgdBuild:455 - logical net 'PinSignal_U28_O' has multiple drivers. The possible drivers causing this are: pin O on block U28 with type INV, pin PAD on block PinSignal_U28_O with type PAD ERROR:NgdBuild:466 - input pad net 'PinSignal_U28_O' has illegal connection. Possible pins causing this are: pin O on block U28 with type INV ERROR:NgdBuild:455 - logical net 'PinSignal_U16_O' has multiple drivers. The possible drivers causing this are: pin O on block U16 with type INV, pin PAD on block PinSignal_U16_O with type PAD ERROR:NgdBuild:466 - input pad net 'PinSignal_U16_O' has illegal connection. Possible pins causing this are: pin O on block U16 with type INV ERROR:NgdBuild:455 - logical net 'PinSignal_U36_O' has multiple drivers. The possible drivers causing this are: pin O on block U36 with type INV, pin PAD on block PinSignal_U36_O with type PAD ERROR:NgdBuild:466 - input pad net 'PinSignal_U36_O' has illegal connection. Possible pins causing this are: pin O on block U36 with type INV ERROR:NgdBuild:455 - logical net 'PinSignal_U4_O' has multiple drivers. The possible drivers causing this are: pin O on block U4 with type INV, pin PAD on block PinSignal_U4_O with type PAD ERROR:NgdBuild:466 - input pad net 'PinSignal_U4_O' has illegal connection. Possible pins causing this are: pin O on block U4 with type INV ERROR:NgdBuild:455 - logical net 'PinSignal_U24_O' has multiple drivers. The possible drivers causing this are: pin O on block U24 with type INV, pin PAD on block PinSignal_U24_O with type PAD ERROR:NgdBuild:466 - input pad net 'PinSignal_U24_O' has illegal connection. Possible pins causing this are: pin O on block U24 with type INV ERROR:NgdBuild:455 - logical net 'PinSignal_U1_O' has multiple drivers. The possible drivers causing this are: pin O on block U1 with type INV, pin PAD on block PinSignal_U1_O with type PAD ERROR:NgdBuild:466 - input pad net 'PinSignal_U1_O' has illegal connection. Possible pins causing this are: pin O on block U1 with type INV ERROR:NgdBuild:455 - logical net 'PinSignal_U11_O' has multiple drivers. The possible drivers causing this are: pin O on block U11 with type INV, pin PAD on block PinSignal_U11_O with type PAD ERROR:NgdBuild:466 - input pad net 'PinSignal_U11_O' has illegal connection. Possible pins causing this are: pin O on block U11 with type INV ERROR:NgdBuild:455 - logical net 'PinSignal_U31_O' has multiple drivers. The possible drivers causing this are: pin O on block U31 with type INV, pin PAD on block PinSignal_U31_O with type PAD ERROR:NgdBuild:466 - input pad net 'PinSignal_U31_O' has illegal connection. Possible pins causing this are: pin O on block U31 with type INV NGDBUILD Design Results Summary: Number of errors: 20 Number of warnings: 0 Total memory usage is 39776 kilobytes One or more errors were found during NGDBUILD. No NGD file will be written. Writing NGDBUILD log file "logic.bld"... Error: Process "Translate" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD in Library work. Entity (Architecture ) compiled. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 265: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 273: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 281: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 289: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 297: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 305: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 312: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 321: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 327: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 335: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 343: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 351: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 359: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 367: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 375: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 384: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 392: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 400: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 407: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 418: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 426: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 434: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 443: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 450: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 458: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 466: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 473: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 484: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 492: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 500: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 507: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 518: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 526: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 534: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 541: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 549: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 557: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 568: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 575: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 583: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 591: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 599: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 607: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 614: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 625: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 633: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 641: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 648: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 656: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 664: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 671: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 679: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 687: Generating a Black Box for component . Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD. Unit synthesized. ========================================================================= * Advanced HDL Synthesis * ========================================================================= Advanced RAM inference ... Advanced multiplier inference ... Advanced Registered AddSub inference ... Dynamic shift register inference ... ========================================================================= HDL Synthesis Report Found no macro ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Completed process "Synthesize". Started process "Translate". Release 6.3.03i - ngdbuild G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -uc logic_locked.ucf -p xc9500 logic.ngc logic.ngd Reading NGO file "c:/xilinx/bin/safety/logic.ngc" ... Reading component libraries for design expansion... Annotating constraints to design from file "logic_locked.ucf" ... INFO:NgdBuild:738 - A case sensitive search for the INST, PAD, or NET element referred to by a constraint entry in 'logic_locked.ucf' that accompanies this design has failed, while a case insensitive search is in progress. The result of the case insensitive search will be used, but messages will accompany each and every use of a case insensitive result. Constraints are case sensitive with respect to user-specified identifiers, which includes names of logic elements in a design. INFO:NgdBuild:740 - Line 29 in 'logic_locked.ucf': Found case insensitive match for NET name 'Horizon_Stop_LATCH'. NET is 'HORIZON_STOP_LATCH'. INFO:NgdBuild:740 - Line 35 in 'logic_locked.ucf': Found case insensitive match for NET name 'Watchdog_Timer_LATCH'. NET is 'WATCHDOG_TIMER_LATCH'. Checking timing specifications ... Checking expanded design ... ERROR:NgdBuild:455 - logical net 'PinSignal_U7_O' has multiple drivers. The possible drivers causing this are: pin O on block U7 with type INV, pin PAD on block PinSignal_U7_O with type PAD ERROR:NgdBuild:466 - input pad net 'PinSignal_U7_O' has illegal connection. Possible pins causing this are: pin O on block U7 with type INV ERROR:NgdBuild:455 - logical net 'PinSignal_U20_O' has multiple drivers. The possible drivers causing this are: pin O on block U20 with type INV, pin PAD on block PinSignal_U20_O with type PAD ERROR:NgdBuild:466 - input pad net 'PinSignal_U20_O' has illegal connection. Possible pins causing this are: pin O on block U20 with type INV ERROR:NgdBuild:455 - logical net 'PinSignal_U28_O' has multiple drivers. The possible drivers causing this are: pin O on block U28 with type INV, pin PAD on block PinSignal_U28_O with type PAD ERROR:NgdBuild:466 - input pad net 'PinSignal_U28_O' has illegal connection. Possible pins causing this are: pin O on block U28 with type INV ERROR:NgdBuild:455 - logical net 'PinSignal_U16_O' has multiple drivers. The possible drivers causing this are: pin O on block U16 with type INV, pin PAD on block PinSignal_U16_O with type PAD ERROR:NgdBuild:466 - input pad net 'PinSignal_U16_O' has illegal connection. Possible pins causing this are: pin O on block U16 with type INV ERROR:NgdBuild:455 - logical net 'PinSignal_U36_O' has multiple drivers. The possible drivers causing this are: pin O on block U36 with type INV, pin PAD on block PinSignal_U36_O with type PAD ERROR:NgdBuild:466 - input pad net 'PinSignal_U36_O' has illegal connection. Possible pins causing this are: pin O on block U36 with type INV ERROR:NgdBuild:455 - logical net 'PinSignal_U4_O' has multiple drivers. The possible drivers causing this are: pin O on block U4 with type INV, pin PAD on block PinSignal_U4_O with type PAD ERROR:NgdBuild:466 - input pad net 'PinSignal_U4_O' has illegal connection. Possible pins causing this are: pin O on block U4 with type INV ERROR:NgdBuild:455 - logical net 'PinSignal_U24_O' has multiple drivers. The possible drivers causing this are: pin O on block U24 with type INV, pin PAD on block PinSignal_U24_O with type PAD ERROR:NgdBuild:466 - input pad net 'PinSignal_U24_O' has illegal connection. Possible pins causing this are: pin O on block U24 with type INV ERROR:NgdBuild:455 - logical net 'PinSignal_U1_O' has multiple drivers. The possible drivers causing this are: pin O on block U1 with type INV, pin PAD on block PinSignal_U1_O with type PAD ERROR:NgdBuild:466 - input pad net 'PinSignal_U1_O' has illegal connection. Possible pins causing this are: pin O on block U1 with type INV ERROR:NgdBuild:455 - logical net 'PinSignal_U11_O' has multiple drivers. The possible drivers causing this are: pin O on block U11 with type INV, pin PAD on block PinSignal_U11_O with type PAD ERROR:NgdBuild:466 - input pad net 'PinSignal_U11_O' has illegal connection. Possible pins causing this are: pin O on block U11 with type INV ERROR:NgdBuild:455 - logical net 'PinSignal_U31_O' has multiple drivers. The possible drivers causing this are: pin O on block U31 with type INV, pin PAD on block PinSignal_U31_O with type PAD ERROR:NgdBuild:466 - input pad net 'PinSignal_U31_O' has illegal connection. Possible pins causing this are: pin O on block U31 with type INV NGDBUILD Design Results Summary: Number of errors: 20 Number of warnings: 0 Total memory usage is 39776 kilobytes One or more errors were found during NGDBUILD. No NGD file will be written. Writing NGDBUILD log file "logic.bld"... Error: Process "Translate" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD in Library work. Entity (Architecture ) compiled. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 263: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 271: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 279: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 287: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 295: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 303: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 310: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 319: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 325: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 333: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 341: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 349: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 357: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 365: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 373: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 382: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 390: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 398: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 405: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 416: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 424: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 432: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 441: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 449: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 457: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 464: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 475: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 483: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 491: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 498: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 509: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 517: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 525: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 532: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 540: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 548: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 559: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 566: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 574: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 582: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 590: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 598: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 609: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 617: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 625: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 632: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 640: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 648: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 655: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 663: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 671: Generating a Black Box for component . Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD. Unit synthesized. ========================================================================= * Advanced HDL Synthesis * ========================================================================= Advanced RAM inference ... Advanced multiplier inference ... Advanced Registered AddSub inference ... Dynamic shift register inference ... ========================================================================= HDL Synthesis Report Found no macro ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Completed process "Synthesize". Started process "Translate". Release 6.3.03i - ngdbuild G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -uc logic_locked.ucf -p xc9500 logic.ngc logic.ngd Reading NGO file "c:/xilinx/bin/safety/logic.ngc" ... Reading component libraries for design expansion... Annotating constraints to design from file "logic_locked.ucf" ... INFO:NgdBuild:738 - A case sensitive search for the INST, PAD, or NET element referred to by a constraint entry in 'logic_locked.ucf' that accompanies this design has failed, while a case insensitive search is in progress. The result of the case insensitive search will be used, but messages will accompany each and every use of a case insensitive result. Constraints are case sensitive with respect to user-specified identifiers, which includes names of logic elements in a design. INFO:NgdBuild:740 - Line 29 in 'logic_locked.ucf': Found case insensitive match for NET name 'Horizon_Stop_LATCH'. NET is 'HORIZON_STOP_LATCH'. INFO:NgdBuild:740 - Line 35 in 'logic_locked.ucf': Found case insensitive match for NET name 'Watchdog_Timer_LATCH'. NET is 'WATCHDOG_TIMER_LATCH'. Checking timing specifications ... Checking expanded design ... ERROR:NgdBuild:455 - logical net 'PinSignal_U7_O' has multiple drivers. The possible drivers causing this are: pin O on block U7 with type INV, pin PAD on block PinSignal_U7_O with type PAD ERROR:NgdBuild:466 - input pad net 'PinSignal_U7_O' has illegal connection. Possible pins causing this are: pin O on block U7 with type INV ERROR:NgdBuild:455 - logical net 'PinSignal_U20_O' has multiple drivers. The possible drivers causing this are: pin O on block U20 with type INV, pin PAD on block PinSignal_U20_O with type PAD ERROR:NgdBuild:466 - input pad net 'PinSignal_U20_O' has illegal connection. Possible pins causing this are: pin O on block U20 with type INV ERROR:NgdBuild:455 - logical net 'PinSignal_U36_O' has multiple drivers. The possible drivers causing this are: pin O on block U36 with type INV, pin PAD on block PinSignal_U36_O with type PAD ERROR:NgdBuild:466 - input pad net 'PinSignal_U36_O' has illegal connection. Possible pins causing this are: pin O on block U36 with type INV ERROR:NgdBuild:455 - logical net 'PinSignal_U16_O' has multiple drivers. The possible drivers causing this are: pin O on block U16 with type INV, pin PAD on block PinSignal_U16_O with type PAD ERROR:NgdBuild:466 - input pad net 'PinSignal_U16_O' has illegal connection. Possible pins causing this are: pin O on block U16 with type INV ERROR:NgdBuild:455 - logical net 'PinSignal_U4_O' has multiple drivers. The possible drivers causing this are: pin O on block U4 with type INV, pin PAD on block PinSignal_U4_O with type PAD ERROR:NgdBuild:466 - input pad net 'PinSignal_U4_O' has illegal connection. Possible pins causing this are: pin O on block U4 with type INV ERROR:NgdBuild:455 - logical net 'PinSignal_U24_O' has multiple drivers. The possible drivers causing this are: pin O on block U24 with type INV, pin PAD on block PinSignal_U24_O with type PAD ERROR:NgdBuild:466 - input pad net 'PinSignal_U24_O' has illegal connection. Possible pins causing this are: pin O on block U24 with type INV ERROR:NgdBuild:455 - logical net 'PinSignal_U28_O' has multiple drivers. The possible drivers causing this are: pin O on block U28 with type INV, pin PAD on block PinSignal_U28_O with type PAD ERROR:NgdBuild:466 - input pad net 'PinSignal_U28_O' has illegal connection. Possible pins causing this are: pin O on block U28 with type INV ERROR:NgdBuild:455 - logical net 'PinSignal_U1_O' has multiple drivers. The possible drivers causing this are: pin O on block U1 with type INV, pin PAD on block PinSignal_U1_O with type PAD ERROR:NgdBuild:466 - input pad net 'PinSignal_U1_O' has illegal connection. Possible pins causing this are: pin O on block U1 with type INV NGDBUILD Design Results Summary: Number of errors: 16 Number of warnings: 0 Total memory usage is 39776 kilobytes One or more errors were found during NGDBUILD. No NGD file will be written. Writing NGDBUILD log file "logic.bld"... Error: Process "Translate" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD in Library work. Entity (Architecture ) compiled. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 259: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 267: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 275: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 283: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 291: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 299: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 306: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 315: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 321: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 329: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 337: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 345: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 353: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 361: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 369: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 378: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 386: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 394: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 401: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 412: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 420: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 428: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 437: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 445: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 453: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 464: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 472: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 480: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 491: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 499: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 507: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 514: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 522: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 530: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 541: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 548: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 556: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 564: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 572: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 580: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 591: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 599: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 607: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 614: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 622: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 630: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 638: Generating a Black Box for component . Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD. Unit synthesized. ========================================================================= * Advanced HDL Synthesis * ========================================================================= Advanced RAM inference ... Advanced multiplier inference ... Advanced Registered AddSub inference ... Dynamic shift register inference ... ========================================================================= HDL Synthesis Report Found no macro ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Completed process "Synthesize". Started process "Translate". Release 6.3.03i - ngdbuild G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -uc logic_locked.ucf -p xc9500 logic.ngc logic.ngd Reading NGO file "c:/xilinx/bin/safety/logic.ngc" ... Reading component libraries for design expansion... Annotating constraints to design from file "logic_locked.ucf" ... INFO:NgdBuild:738 - A case sensitive search for the INST, PAD, or NET element referred to by a constraint entry in 'logic_locked.ucf' that accompanies this design has failed, while a case insensitive search is in progress. The result of the case insensitive search will be used, but messages will accompany each and every use of a case insensitive result. Constraints are case sensitive with respect to user-specified identifiers, which includes names of logic elements in a design. INFO:NgdBuild:740 - Line 29 in 'logic_locked.ucf': Found case insensitive match for NET name 'Horizon_Stop_LATCH'. NET is 'HORIZON_STOP_LATCH'. INFO:NgdBuild:740 - Line 35 in 'logic_locked.ucf': Found case insensitive match for NET name 'Watchdog_Timer_LATCH'. NET is 'WATCHDOG_TIMER_LATCH'. Checking timing specifications ... Checking expanded design ... ERROR:NgdBuild:455 - logical net 'PinSignal_U7_O' has multiple drivers. The possible drivers causing this are: pin O on block U7 with type INV, pin PAD on block PinSignal_U7_O with type PAD ERROR:NgdBuild:466 - input pad net 'PinSignal_U7_O' has illegal connection. Possible pins causing this are: pin O on block U7 with type INV ERROR:NgdBuild:455 - logical net 'PinSignal_U36_O' has multiple drivers. The possible drivers causing this are: pin O on block U36 with type INV, pin PAD on block PinSignal_U36_O with type PAD ERROR:NgdBuild:466 - input pad net 'PinSignal_U36_O' has illegal connection. Possible pins causing this are: pin O on block U36 with type INV ERROR:NgdBuild:455 - logical net 'PinSignal_U16_O' has multiple drivers. The possible drivers causing this are: pin O on block U16 with type INV, pin PAD on block PinSignal_U16_O with type PAD ERROR:NgdBuild:466 - input pad net 'PinSignal_U16_O' has illegal connection. Possible pins causing this are: pin O on block U16 with type INV ERROR:NgdBuild:455 - logical net 'PinSignal_U20_O' has multiple drivers. The possible drivers causing this are: pin O on block U20 with type INV, pin PAD on block PinSignal_U20_O with type PAD ERROR:NgdBuild:466 - input pad net 'PinSignal_U20_O' has illegal connection. Possible pins causing this are: pin O on block U20 with type INV NGDBUILD Design Results Summary: Number of errors: 8 Number of warnings: 0 Total memory usage is 39776 kilobytes One or more errors were found during NGDBUILD. No NGD file will be written. Writing NGDBUILD log file "logic.bld"... Error: Process "Translate" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD in Library work. Entity (Architecture ) compiled. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 265: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 273: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 281: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 289: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 297: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 305: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 312: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 321: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 327: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 335: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 343: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 351: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 359: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 367: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 375: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 384: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 392: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 400: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 407: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 418: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 426: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 434: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 443: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 450: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 458: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 466: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 473: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 484: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 492: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 500: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 507: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 518: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 526: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 534: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 541: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 549: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 557: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 568: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 575: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 583: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 591: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 599: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 607: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 614: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 625: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 633: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 641: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 648: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 656: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 664: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 671: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 679: Generating a Black Box for component . WARNING:Xst:766 - c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD line 687: Generating a Black Box for component . Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is c:/xilinx/bin/safety/./ProjectOutputs/Logic.VHD. Unit synthesized. ========================================================================= * Advanced HDL Synthesis * ========================================================================= Advanced RAM inference ... Advanced multiplier inference ... Advanced Registered AddSub inference ... Dynamic shift register inference ... ========================================================================= HDL Synthesis Report Found no macro ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Completed process "Synthesize". Started process "Translate". Release 6.3.03i - ngdbuild G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -uc logic_locked.ucf -p xc9500 logic.ngc logic.ngd Reading NGO file "c:/xilinx/bin/safety/logic.ngc" ... Reading component libraries for design expansion... Annotating constraints to design from file "logic_locked.ucf" ... INFO:NgdBuild:738 - A case sensitive search for the INST, PAD, or NET element referred to by a constraint entry in 'logic_locked.ucf' that accompanies this design has failed, while a case insensitive search is in progress. The result of the case insensitive search will be used, but messages will accompany each and every use of a case insensitive result. Constraints are case sensitive with respect to user-specified identifiers, which includes names of logic elements in a design. INFO:NgdBuild:740 - Line 29 in 'logic_locked.ucf': Found case insensitive match for NET name 'Horizon_Stop_LATCH'. NET is 'HORIZON_STOP_LATCH'. INFO:NgdBuild:740 - Line 35 in 'logic_locked.ucf': Found case insensitive match for NET name 'Watchdog_Timer_LATCH'. NET is 'WATCHDOG_TIMER_LATCH'. Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 39776 kilobytes Writing NGD file "logic.ngd" ... Writing NGDBUILD log file "logic.bld"... NGDBUILD done. Completed process "Translate". Started process "Fit". Release 6.3.03i - CPLD Optimizer/Partitioner G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Considering device XC9572-15-PC84. Flattening design.. Multi-level logic optimization... Timing optimization.............. Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 33 equations into 4 function blocks.... Design logic has been optimized and fit into device XC9572-15-PC84. Completed process "Fit". Started process "Generate Programming File". Release 6.3.03i - Programming File Generator G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Completed process "Generate Programming File". Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD in Library work. Entity (Architecture ) compiled. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 265: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 273: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 281: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 289: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 297: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 305: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 312: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 321: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 327: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 335: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 343: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 351: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 359: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 367: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 375: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 384: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 392: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 400: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 407: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 418: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 426: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 434: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 443: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 450: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 458: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 466: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 473: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 484: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 492: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 500: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 507: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 518: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 526: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 534: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 541: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 549: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 557: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 568: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 575: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 583: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 591: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 599: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 607: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 614: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 625: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 633: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 641: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 648: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 656: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 664: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 671: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 679: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 687: Generating a Black Box for component . Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD. Unit synthesized. ========================================================================= * Advanced HDL Synthesis * ========================================================================= Advanced RAM inference ... Advanced multiplier inference ... Advanced Registered AddSub inference ... Dynamic shift register inference ... ========================================================================= HDL Synthesis Report Found no macro ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Completed process "Synthesize". Started process "Translate". Release 6.3.03i - ngdbuild G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -uc logic_locked.ucf -p xc9500 logic.ngc logic.ngd Reading NGO file "C:/Xilinx/bin/Safety/logic.ngc" ... Reading component libraries for design expansion... Annotating constraints to design from file "logic_locked.ucf" ... INFO:NgdBuild:738 - A case sensitive search for the INST, PAD, or NET element referred to by a constraint entry in 'logic_locked.ucf' that accompanies this design has failed, while a case insensitive search is in progress. The result of the case insensitive search will be used, but messages will accompany each and every use of a case insensitive result. Constraints are case sensitive with respect to user-specified identifiers, which includes names of logic elements in a design. INFO:NgdBuild:740 - Line 29 in 'logic_locked.ucf': Found case insensitive match for NET name 'Horizon_Stop_LATCH'. NET is 'HORIZON_STOP_LATCH'. INFO:NgdBuild:740 - Line 35 in 'logic_locked.ucf': Found case insensitive match for NET name 'Watchdog_Timer_LATCH'. NET is 'WATCHDOG_TIMER_LATCH'. Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 39776 kilobytes Writing NGD file "logic.ngd" ... Writing NGDBUILD log file "logic.bld"... NGDBUILD done. Completed process "Translate". Started process "Fit". Release 6.3.03i - CPLD Optimizer/Partitioner G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Considering device XC9572-15-PC84. Flattening design.. Multi-level logic optimization... Timing optimization.............. Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 33 equations into 4 function blocks.... Design logic has been optimized and fit into device XC9572-15-PC84. Completed process "Fit". Started process "Generate HTML report". Release 6.3.03i - CPLD HTML Report Processor G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD in Library work. Entity (Architecture ) compiled. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 279: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 287: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 295: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 303: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 311: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 319: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 326: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 335: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 341: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 349: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 357: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 365: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 374: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 382: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 390: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 398: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 407: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 415: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 423: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 430: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 442: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 451: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 459: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 467: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 474: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 482: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 490: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 501: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 508: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 516: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 524: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 531: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 542: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 550: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 558: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 565: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 576: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 584: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 592: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 599: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 607: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 615: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 626: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 634: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 642: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 649: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 657: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 665: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 673: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 680: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 688: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 696: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 704: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 711: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 719: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 727: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 735: Generating a Black Box for component . Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD. Unit synthesized. ========================================================================= * Advanced HDL Synthesis * ========================================================================= Advanced RAM inference ... Advanced multiplier inference ... Advanced Registered AddSub inference ... Dynamic shift register inference ... ========================================================================= HDL Synthesis Report Found no macro ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Completed process "Synthesize". Started process "Translate". Release 6.3.03i - ngdbuild G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -i -p xc9500 logic.ngc logic.ngd Reading NGO file "C:/Xilinx/bin/Safety/logic.ngc" ... Reading component libraries for design expansion... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 38752 kilobytes Writing NGD file "logic.ngd" ... Writing NGDBUILD log file "logic.bld"... NGDBUILD done. Completed process "Translate". Started process "Fit". Release 6.3.03i - CPLD Optimizer/Partitioner G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Considering device XC9572-15-PC84. Flattening design.. Multi-level logic optimization... Timing optimization............... Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 36 equations into 4 function blocks.............................. Design logic has been optimized and fit into device XC9572-15-PC84. Completed process "Fit". Started process "Generate Programming File". Release 6.3.03i - Programming File Generator G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Completed process "Generate Programming File". Project Navigator Auto-Make Log File ------------------------------------- Started process "Lock Pins". pin2ucf: Xilinx Pin Locker G.35.Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Pin Locking constraints file generated in : logic_locked.ucf Completed process "Lock Pins". Project Navigator Auto-Make Log File ------------------------------------- Started process "Translate". Release 6.3.03i - ngdbuild G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -uc logic_locked.ucf -p xc9500 logic.ngc logic.ngd Reading NGO file "C:/Xilinx/bin/Safety/logic.ngc" ... Reading component libraries for design expansion... Annotating constraints to design from file "logic_locked.ucf" ... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 39776 kilobytes Writing NGD file "logic.ngd" ... Writing NGDBUILD log file "logic.bld"... NGDBUILD done. Completed process "Translate". Started process "Fit". Release 6.3.03i - CPLD Optimizer/Partitioner G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Considering device XC9572-15-PC84. Flattening design.. Multi-level logic optimization... Timing optimization............... Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 36 equations into 4 function blocks...... Design logic has been optimized and fit into device XC9572-15-PC84. Completed process "Fit". Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD in Library work. ERROR:HDLParsers:163 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD Line 221. Unexpected symbol read: ?. ERROR:HDLParsers:163 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD Line 221. Unexpected symbol read: _. ERROR:HDLParsers:164 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD Line 221. parse error, unexpected IDENTIFIER, expecting COMMA or COLON ERROR:HDLParsers:163 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD Line 286. Unexpected symbol read: ?. ERROR:HDLParsers:163 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD Line 286. Unexpected symbol read: _. ERROR:HDLParsers:3312 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD Line 286. Undefined symbol 'PinSignal_U'. ERROR:HDLParsers:1209 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD Line 286. PinSignal_U: Undefined symbol (last report in this block) ERROR:HDLParsers:164 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD Line 286. parse error, unexpected IDENTIFIER, expecting COMMA or CLOSEPAR ERROR:HDLParsers:163 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD Line 388. Unexpected symbol read: ?. ERROR:HDLParsers:163 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD Line 388. Unexpected symbol read: _. ERROR:HDLParsers:164 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD Line 388. parse error, unexpected IDENTIFIER, expecting COMMA or CLOSEPAR --> Total memory usage is 48092 kilobytes ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD in Library work. Entity (Architecture ) compiled. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 281: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 289: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 297: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 305: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 313: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 321: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 329: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 336: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 345: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 351: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 359: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 367: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 375: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 384: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 392: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 400: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 408: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 417: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 425: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 433: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 440: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 452: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 461: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 469: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 477: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 484: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 492: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 500: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 511: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 518: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 526: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 534: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 541: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 552: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 560: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 568: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 575: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 586: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 594: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 602: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 609: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 617: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 625: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 636: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 644: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 652: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 659: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 667: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 675: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 683: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 690: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 698: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 706: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 714: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 721: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 729: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 737: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 745: Generating a Black Box for component . Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD. Unit synthesized. ========================================================================= * Advanced HDL Synthesis * ========================================================================= Advanced RAM inference ... Advanced multiplier inference ... Advanced Registered AddSub inference ... Dynamic shift register inference ... ========================================================================= HDL Synthesis Report Found no macro ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Completed process "Synthesize". Started process "Translate". Release 6.3.03i - ngdbuild G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -i -p xc9500 logic.ngc logic.ngd Reading NGO file "C:/Xilinx/bin/Safety/logic.ngc" ... Reading component libraries for design expansion... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 38752 kilobytes Writing NGD file "logic.ngd" ... Writing NGDBUILD log file "logic.bld"... NGDBUILD done. Completed process "Translate". Started process "Fit". Release 6.3.03i - CPLD Optimizer/Partitioner G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Considering device XC9572-15-PC84. Flattening design.. Multi-level logic optimization... Timing optimization............... Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 36 equations into 4 function blocks............................. Design logic has been optimized and fit into device XC9572-15-PC84. Completed process "Fit". Started process "Generate Programming File". Release 6.3.03i - Programming File Generator G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Completed process "Generate Programming File". Project Navigator Auto-Make Log File ------------------------------------- Started process "Lock Pins". pin2ucf: Xilinx Pin Locker G.35.Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. ERROR:Pin2Ucf - pin2ucf found that the UCF file for this design already have some pin locking constraints. Since pin2ucf will not overwrite user constraints, please check the UCF file and remove those constraints before trying pin2ucf again. You could also delete the UCF file before trying again. To get a listing of all possible conflicts among constraints for this design please check the pin2ucf report file: logic.lck Process "Lock Pins" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Lock Pins". pin2ucf: Xilinx Pin Locker G.35.Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Pin Locking constraints file generated in : logic_locked.ucf Completed process "Lock Pins". Project Navigator Auto-Make Log File ------------------------------------- Started process "Translate". Release 6.3.03i - ngdbuild G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -uc logic_locked.ucf -p xc9500 logic.ngc logic.ngd Reading NGO file "C:/Xilinx/bin/Safety/logic.ngc" ... Reading component libraries for design expansion... Annotating constraints to design from file "logic_locked.ucf" ... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 39776 kilobytes Writing NGD file "logic.ngd" ... Writing NGDBUILD log file "logic.bld"... NGDBUILD done. Completed process "Translate". Started process "Fit". Release 6.3.03i - CPLD Optimizer/Partitioner G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Considering device XC9572-15-PC84. Flattening design.. Multi-level logic optimization... Timing optimization............... Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 36 equations into 4 function blocks...... Design logic has been optimized and fit into device XC9572-15-PC84. Completed process "Fit". Project Navigator Auto-Make Log File ------------------------------------- Started process "Generate HTML report". Release 6.3.03i - CPLD HTML Report Processor G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Project Navigator Auto-Make Log File ------------------------------------- Started process "Generate Programming File". Release 6.3.03i - Programming File Generator G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Completed process "Generate Programming File". Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD in Library work. Entity (Architecture ) compiled. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 288: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 295: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 302: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 309: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 316: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 323: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 330: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 337: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 345: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 353: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 361: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 369: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 377: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 385: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 392: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 401: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 407: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 415: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 423: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 431: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 440: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 448: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 456: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 464: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 473: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 481: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 489: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 496: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 508: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 517: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 525: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 533: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 540: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 548: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 556: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 567: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 574: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 582: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 590: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 597: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 608: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 616: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 624: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 631: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 642: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 650: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 658: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 665: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 673: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 681: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 692: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 700: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 708: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 715: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 723: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 731: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 739: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 746: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 754: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 762: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 770: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 777: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 785: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 793: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 801: Generating a Black Box for component . Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD. Unit synthesized. ========================================================================= * Advanced HDL Synthesis * ========================================================================= Advanced RAM inference ... Advanced multiplier inference ... Advanced Registered AddSub inference ... Dynamic shift register inference ... ========================================================================= HDL Synthesis Report Found no macro ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Completed process "Synthesize". Started process "Translate". Release 6.3.03i - ngdbuild G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -uc logic_locked.ucf -p xc9500 logic.ngc logic.ngd Reading NGO file "C:/Xilinx/bin/Safety/logic.ngc" ... Reading component libraries for design expansion... Annotating constraints to design from file "logic_locked.ucf" ... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 39780 kilobytes Writing NGD file "logic.ngd" ... Writing NGDBUILD log file "logic.bld"... NGDBUILD done. Completed process "Translate". Started process "Fit". Release 6.3.03i - CPLD Optimizer/Partitioner G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Considering device XC9572-15-PC84. Flattening design.. Multi-level logic optimization... Timing optimization............... Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 36 equations into 4 function blocks...... Design logic has been optimized and fit into device XC9572-15-PC84. Completed process "Fit". Project Navigator Auto-Make Log File ------------------------------------- Started process "Generate Programming File". Release 6.3.03i - Programming File Generator G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Completed process "Generate Programming File". Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD in Library work. Entity (Architecture ) compiled. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 306: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 313: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 320: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 327: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 334: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 341: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 348: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 355: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 363: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 371: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 379: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 387: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 395: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 403: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 410: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 419: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 425: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 433: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 441: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 449: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 458: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 466: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 474: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 482: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 491: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 499: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 507: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 514: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 526: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 535: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 543: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 551: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 558: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 566: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 574: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 585: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 592: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 600: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 608: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 615: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 626: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 634: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 642: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 649: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 660: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 668: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 676: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 683: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 691: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 699: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 710: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 718: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 726: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 733: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 741: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 749: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 757: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 764: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 772: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 780: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 788: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 795: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 803: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 811: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 819: Generating a Black Box for component . Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD. Unit synthesized. ========================================================================= * Advanced HDL Synthesis * ========================================================================= Advanced RAM inference ... Advanced multiplier inference ... Advanced Registered AddSub inference ... Dynamic shift register inference ... ========================================================================= HDL Synthesis Report Found no macro ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Completed process "Synthesize". Started process "Translate". Release 6.3.03i - ngdbuild G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -uc logic_locked.ucf -p xc9500 logic.ngc logic.ngd Reading NGO file "C:/Xilinx/bin/Safety/logic.ngc" ... Reading component libraries for design expansion... Annotating constraints to design from file "logic_locked.ucf" ... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 39780 kilobytes Writing NGD file "logic.ngd" ... Writing NGDBUILD log file "logic.bld"... NGDBUILD done. Completed process "Translate". Started process "Fit". Release 6.3.03i - CPLD Optimizer/Partitioner G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Considering device XC9572-15-PC84. Flattening design.. Multi-level logic optimization... Timing optimization............... Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 36 equations into 4 function blocks...... Design logic has been optimized and fit into device XC9572-15-PC84. Completed process "Fit". Project Navigator Auto-Make Log File ------------------------------------- Started process "Generate Programming File". Release 6.3.03i - Programming File Generator G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Completed process "Generate Programming File". Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD in Library work. ERROR:HDLParsers:851 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD Line 372. Formal I1 of NAND2B2 with no default value must be associated with an actual value. --> Total memory usage is 48096 kilobytes ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD in Library work. Entity (Architecture ) compiled. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 315: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 322: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 329: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 336: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 343: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 350: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 357: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 364: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 372: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 380: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 388: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 396: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 404: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 412: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 419: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 428: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 434: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 442: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 450: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 458: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 467: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 475: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 483: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 491: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 500: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 508: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 516: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 523: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 535: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 544: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 552: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 560: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 567: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 575: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 583: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 594: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 601: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 609: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 617: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 624: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 635: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 643: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 651: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 658: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 669: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 677: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 685: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 692: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 700: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 708: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 719: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 727: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 735: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 742: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 750: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 758: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 766: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 773: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 781: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 789: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 797: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 804: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 812: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 820: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 828: Generating a Black Box for component . Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD. Unit synthesized. ========================================================================= * Advanced HDL Synthesis * ========================================================================= Advanced RAM inference ... Advanced multiplier inference ... Advanced Registered AddSub inference ... Dynamic shift register inference ... ========================================================================= HDL Synthesis Report Found no macro ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Completed process "Synthesize". Started process "Translate". Release 6.3.03i - ngdbuild G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -uc logic_locked.ucf -p xc9500 logic.ngc logic.ngd Reading NGO file "C:/Xilinx/bin/Safety/logic.ngc" ... Reading component libraries for design expansion... Annotating constraints to design from file "logic_locked.ucf" ... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 39780 kilobytes Writing NGD file "logic.ngd" ... Writing NGDBUILD log file "logic.bld"... NGDBUILD done. Completed process "Translate". Started process "Fit". Release 6.3.03i - CPLD Optimizer/Partitioner G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Considering device XC9572-15-PC84. Flattening design.. Multi-level logic optimization... Timing optimization.............. Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 36 equations into 4 function blocks...... Design logic has been optimized and fit into device XC9572-15-PC84. Completed process "Fit". Started process "Generate Programming File". Release 6.3.03i - Programming File Generator G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Completed process "Generate Programming File". Project Navigator Auto-Make Log File ------------------------------------- Started process "Generate HTML report". Release 6.3.03i - CPLD HTML Report Processor G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD in Library work. ERROR:HDLParsers:3312 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD Line 20. Undefined symbol 'UnDef'. ERROR:HDLParsers:1209 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD Line 20. UnDef: Undefined symbol (last report in this block) ERROR:HDLParsers:3312 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD Line 857. Undefined symbol 'CLK'. ERROR:HDLParsers:1209 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD Line 857. CLK: Undefined symbol (last report in this block) ERROR:HDLParsers:164 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD Line 857. parse error, unexpected IN, expecting OPENPAR or TICK or LSQBRACK ERROR:HDLParsers:164 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD Line 906. parse error, unexpected IN, expecting SEMICOLON --> Total memory usage is 48096 kilobytes ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD in Library work. ERROR:HDLParsers:3312 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD Line 326. Undefined symbol 'CLK'. ERROR:HDLParsers:1209 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD Line 326. CLK: Undefined symbol (last report in this block) ERROR:HDLParsers:164 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD Line 326. parse error, unexpected IN, expecting COMMA or CLOSEPAR --> Total memory usage is 48096 kilobytes ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD in Library work. Entity (Architecture ) compiled. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 323: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 330: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 339: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 348: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 356: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 363: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 370: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 377: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 384: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 391: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 398: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 406: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 414: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 422: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 430: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 438: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 446: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 453: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 462: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 468: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 476: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 484: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 492: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 500: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 508: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 516: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 526: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 534: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 542: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 549: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 560: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 570: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 578: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 586: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 593: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 601: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 609: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 620: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 627: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 635: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 643: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 650: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 661: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 669: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 677: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 684: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 695: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 703: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 711: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 718: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 726: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 734: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 745: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 753: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 761: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 768: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 776: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 784: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 791: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 799: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 807: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 815: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 822: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 830: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 838: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 846: Generating a Black Box for component . Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD. Unit synthesized. ========================================================================= * Advanced HDL Synthesis * ========================================================================= Advanced RAM inference ... Advanced multiplier inference ... Advanced Registered AddSub inference ... Dynamic shift register inference ... ========================================================================= HDL Synthesis Report Found no macro ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Completed process "Synthesize". Started process "Translate". Release 6.3.03i - ngdbuild G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -uc logic_locked.ucf -p xc9500 logic.ngc logic.ngd Reading NGO file "C:/Xilinx/bin/Safety/logic.ngc" ... Reading component libraries for design expansion... Annotating constraints to design from file "logic_locked.ucf" ... Checking timing specifications ... Checking expanded design ... ERROR:NgdBuild:604 - logical block 'U68' with type 'FDR' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, or the misspelling of a type name. Symbol 'FDR' is not supported in target 'xc9500'. ERROR:NgdBuild:604 - logical block 'U67' with type 'FDR' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, or the misspelling of a type name. Symbol 'FDR' is not supported in target 'xc9500'. NGDBUILD Design Results Summary: Number of errors: 2 Number of warnings: 0 Total memory usage is 40804 kilobytes One or more errors were found during NGDBUILD. No NGD file will be written. Writing NGDBUILD log file "logic.bld"... Error: Process "Translate" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD in Library work. ERROR:HDLParsers:851 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD Line 330. Formal C of FDC with no default value must be associated with an actual value. --> Total memory usage is 48096 kilobytes ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD in Library work. Entity (Architecture ) compiled. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 323: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 330: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 339: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 348: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 356: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 363: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 370: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 377: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 384: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 391: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 398: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 406: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 414: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 422: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 430: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 438: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 446: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 453: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 462: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 468: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 476: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 484: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 492: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 500: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 508: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 516: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 526: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 534: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 542: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 549: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 560: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 570: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 578: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 586: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 593: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 601: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 609: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 620: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 627: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 635: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 643: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 650: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 661: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 669: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 677: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 684: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 695: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 703: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 711: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 718: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 726: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 734: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 745: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 753: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 761: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 768: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 776: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 784: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 791: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 799: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 807: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 815: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 822: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 830: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 838: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 846: Generating a Black Box for component . Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD. Unit synthesized. ========================================================================= * Advanced HDL Synthesis * ========================================================================= Advanced RAM inference ... Advanced multiplier inference ... Advanced Registered AddSub inference ... Dynamic shift register inference ... ========================================================================= HDL Synthesis Report Found no macro ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Completed process "Synthesize". Started process "Translate". Release 6.3.03i - ngdbuild G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -uc logic_locked.ucf -p xc9500 logic.ngc logic.ngd Reading NGO file "C:/Xilinx/bin/Safety/logic.ngc" ... Reading component libraries for design expansion... Annotating constraints to design from file "logic_locked.ucf" ... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 39780 kilobytes Writing NGD file "logic.ngd" ... Writing NGDBUILD log file "logic.bld"... NGDBUILD done. Completed process "Translate". Started process "Fit". Release 6.3.03i - CPLD Optimizer/Partitioner G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Considering device XC9572-15-PC84. Flattening design.. Multi-level logic optimization... Timing optimization..... Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 37 equations into 4 function blocks...... Design logic has been optimized and fit into device XC9572-15-PC84. Completed process "Fit". Started process "Generate Programming File". Release 6.3.03i - Programming File Generator G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Completed process "Generate Programming File". Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD in Library work. Entity (Architecture ) compiled. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 332: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 339: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 348: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 357: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 365: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 372: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 379: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 386: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 393: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 400: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 407: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 415: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 423: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 431: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 439: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 447: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 454: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 463: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 469: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 478: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 486: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 494: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 502: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 510: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 518: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 528: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 536: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 544: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 551: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 562: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 572: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 580: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 588: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 595: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 603: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 611: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 622: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 629: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 637: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 645: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 652: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 663: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 671: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 679: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 686: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 697: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 705: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 713: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 720: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 728: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 736: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 747: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 755: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 763: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 770: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 778: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 786: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 793: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 801: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 809: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 817: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 824: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 832: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 840: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 848: Generating a Black Box for component . Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD. Unit synthesized. ========================================================================= * Advanced HDL Synthesis * ========================================================================= Advanced RAM inference ... Advanced multiplier inference ... Advanced Registered AddSub inference ... Dynamic shift register inference ... ========================================================================= HDL Synthesis Report Found no macro ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Completed process "Synthesize". Started process "Translate". Release 6.3.03i - ngdbuild G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -uc logic_locked.ucf -p xc9500 logic.ngc logic.ngd Reading NGO file "C:/Xilinx/bin/Safety/logic.ngc" ... Reading component libraries for design expansion... Annotating constraints to design from file "logic_locked.ucf" ... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 39780 kilobytes Writing NGD file "logic.ngd" ... Writing NGDBUILD log file "logic.bld"... NGDBUILD done. Completed process "Translate". Started process "Fit". Release 6.3.03i - CPLD Optimizer/Partitioner G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Considering device XC9572-15-PC84. Flattening design.. Multi-level logic optimization... Timing optimization..... Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 37 equations into 4 function blocks...... Design logic has been optimized and fit into device XC9572-15-PC84. Completed process "Fit". Started process "Generate Programming File". Release 6.3.03i - Programming File Generator G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Completed process "Generate Programming File". Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD in Library work. Entity (Architecture ) compiled. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 335: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 342: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 351: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 360: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 368: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 375: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 382: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 389: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 396: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 403: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 410: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 418: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 426: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 434: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 442: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 450: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 457: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 466: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 472: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 481: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 489: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 497: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 505: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 513: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 521: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 529: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 539: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 547: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 555: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 562: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 573: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 583: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 591: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 599: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 606: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 614: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 622: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 633: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 640: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 648: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 656: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 663: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 674: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 682: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 690: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 697: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 708: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 716: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 724: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 731: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 739: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 747: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 758: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 766: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 774: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 781: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 788: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 796: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 804: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 811: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 819: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 827: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 835: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 842: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 850: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 858: Generating a Black Box for component . WARNING:Xst:766 - C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD line 866: Generating a Black Box for component . Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is C:/Xilinx/bin/Safety/./ProjectOutputs/Logic.VHD. Unit synthesized. ========================================================================= * Advanced HDL Synthesis * ========================================================================= Advanced RAM inference ... Advanced multiplier inference ... Advanced Registered AddSub inference ... Dynamic shift register inference ... ========================================================================= HDL Synthesis Report Found no macro ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Completed process "Synthesize". Started process "Translate". Release 6.3.03i - ngdbuild G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -i -p xc9500 logic.ngc logic.ngd Reading NGO file "C:/Xilinx/bin/Safety/logic.ngc" ... Reading component libraries for design expansion... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 37732 kilobytes Writing NGD file "logic.ngd" ... Writing NGDBUILD log file "logic.bld"... NGDBUILD done. Completed process "Translate". Started process "Fit". Release 6.3.03i - CPLD Optimizer/Partitioner G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Considering device XC9572-15-PC84. Flattening design.. Multi-level logic optimization... Timing optimization..... Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 37 equations into 4 function blocks................................ Design logic has been optimized and fit into device XC9572-15-PC84. Completed process "Fit". Started process "Generate Programming File". Release 6.3.03i - Programming File Generator G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Completed process "Generate Programming File". Project Navigator Auto-Make Log File ------------------------------------- Started process "Generate HTML report". Release 6.3.03i - CPLD HTML Report Processor G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Project Navigator Auto-Make Log File ------------------------------------- Started process "Lock Pins". pin2ucf: Xilinx Pin Locker G.35.Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Pin Locking constraints file generated in : logic_locked.ucf Completed process "Lock Pins".