Design Name | logic |
Fitting Status | Successful |
SW Version | G.38 |
Device Used | XC9572-15-PC84 |
Date | 4-25-2006, 10:04AM |
Macrocells Used | Pterms Used | Registers Used | Pins Used | Function Block Inputs Used |
---|---|---|---|---|
37/72 (52%) | 71/360 (20%) | 31/72 (44%) | 69/69 (100%) | 72/144 (50%) |
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Total Macrocells Available | 72 |
Registered Macrocells | 31 |
Non-registered Macrocells driving I/O | 4 |
Signal mapped onto global clock net (GCK1) | CLK_IN |
Signal mapped onto global output enable net (GSR) | /RESET |
Macrocells in high performance mode (MCHP) | 37 |
Macrocells in low power mode (MCLP) | 0 |
Total macrocells used (MC) | 37 |