Release 8.1i - Fit I.32
Copyright(c) 1995-2003 Xilinx Inc. All rights reserved

 7-31-2006  6:52PM

NOTE: This file is designed to be imported into a spreadsheet program
such as Microsoft Excel for viewing, printing and sorting. The pipe '|'
character is used as the data field separator.
This file is also designed to support parsing.

Input file:  Logic.ngd
output file: Logic.pad
Part type:   xc9572
Speed grade: -15
Package:     pc84

Pinout by Pin Number:

-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|
Pin Number|Signal Name|Pin Usage|Pin Name|Direction|IO Standard|IO Bank Number|{blank}|Slew Rate|Termination|{blank}|Voltage|Constraint|
P1|TEL_ENABLE|O|I/O|OUTPUT|||||||||
P2|DOME1_OC_LATCH|I/O|I/O|BIDIR|||||||||
P3|DEC_STOP_N|I|I/O|INPUT|||||||||
P4|DEC_STOP_N_LATCH|I/O|I/O|BIDIR|||||||||
P5|HA_OS|I|I/O|INPUT|||||||||
P6|DEC_EMERG_S_LATCH|I/O|I/O|BIDIR|||||||||
P7|TOP_TCS_ENABLE|O|I/O|OUTPUT|||||||||
P8|GND||GND||||||||||
P9|CLK_IN|GCK|I/O/GCK1||||||||||
P10|MTR_CNTR_ERR|I|I/O/GCK2|INPUT|||||||||
P11|DOME2_OC_LATCH|I/O|I/O|BIDIR|||||||||
P12|SPARE1|I|I/O/GCK3|INPUT|||||||||
P13|DOME3_OC_LATCH|I/O|I/O|BIDIR|||||||||
P14|TOP_LM_OVERRIDE_SWITCH|I|I/O|INPUT|||||||||
P15|WEST_OC|I|I/O|INPUT|||||||||
P16|GND||GND||||||||||
P17|MTR_CNTR_ERR_LATCH|I/O|I/O|BIDIR|||||||||
P18|DOME1_OC|I|I/O|INPUT|||||||||
P19|HP_STOP|I|I/O|INPUT|||||||||
P20|EAST_OC_LATCH|I/O|I/O|BIDIR|||||||||
P21|SPARE1_LATCH|I/O|I/O|BIDIR|||||||||
P22|VCC||VCCIO||||||||||
P23|EMERG_STOP_LATCH|I/O|I/O|BIDIR|||||||||
P24|TOP_BRAKE_ENABLE_OUT|O|I/O|OUTPUT|||||||||
P25|SPARE6|I|I/O|INPUT|||||||||
P26|DEC_EMERG_S|I|I/O|INPUT|||||||||
P27|GND||GND||||||||||
P28|TDI||TDI||||||||||
P29|TMS||TMS||||||||||
P30|TCK||TCK||||||||||
P31|DOME3_OC|I|I/O|INPUT|||||||||
P32|NORTH_OC_LATCH|I/O|I/O|BIDIR|||||||||
P33|DEC_EMERG_N|I|I/O|INPUT|||||||||
P34|SOUTH_OC_LATCH|I/O|I/O|BIDIR|||||||||
P35|EMERG_STOP|I|I/O|INPUT|||||||||
P36|SPARE4_LATCH|I/O|I/O|BIDIR|||||||||
P37|HA_STOP_W|I|I/O|INPUT|||||||||
P38|VCC||VCCINT||||||||||
P39|SPARE6_LATCH|O|I/O|OUTPUT|||||||||
P40|SPARE2_LATCH|I/O|I/O|BIDIR|||||||||
P41|SPARE3_LATCH|I/O|I/O|BIDIR|||||||||
P42|GND||GND||||||||||
P43|DOME2_OC|I|I/O|INPUT|||||||||
P44|DEC_EMERG_N_LATCH|I/O|I/O|BIDIR|||||||||
P45|SPARE5_LATCH|I/O|I/O|BIDIR|||||||||
P46|EAST_OC|I|I/O|INPUT|||||||||
P47|HORIZON_STOP|I|I/O|INPUT|||||||||
P48|HORIZON_STOP_LATCH|I/O|I/O|BIDIR|||||||||
P49|GND||GND||||||||||
P50|TOP_DOMECNTL_HANDPADDLE|I|I/O|INPUT|||||||||
P51|SPARE5|I|I/O|INPUT|||||||||
P52|DEC_STOP_S_LATCH|I/O|I/O|BIDIR|||||||||
P53|HA_EMERG_W|I|I/O|INPUT|||||||||
P54|DEC_OS_LATCH|I/O|I/O|BIDIR|||||||||
P55|BRAKE_EN_IN|I|I/O|INPUT|||||||||
P56|WATCHDOG_TIMER_LATCH|I/O|I/O|BIDIR|||||||||
P57|HP_STOP_LATCH|I/O|I/O|BIDIR|||||||||
P58|TCS_LOCKOUT_LATCH|I/O|I/O|BIDIR|||||||||
P59|TDO||TDO||||||||||
P60|GND||GND||||||||||
P61|SPARE2|I|I/O|INPUT|||||||||
P62|WEST_OC_LATCH|I/O|I/O|BIDIR|||||||||
P63|HA_EMERG_E_LATCH|O|I/O|OUTPUT|||||||||
P64|VCC||VCCIO||||||||||
P65|DEC_OS|I|I/O|INPUT|||||||||
P66|DOME_ENABLE|O|I/O|OUTPUT|||||||||
P67|DEC_STOP_S|I|I/O|INPUT|||||||||
P68|HA_EMERG_W_LATCH|O|I/O|OUTPUT|||||||||
P69|TOP_TEL_ENABLE_SWITCH|I|I/O|INPUT|||||||||
P70|HA_STOP_E|I|I/O|INPUT|||||||||
P71|WATCHDOG_TIMER|I|I/O|INPUT|||||||||
P72|HA_OS_LATCH|O|I/O|OUTPUT|||||||||
P73|VCC||VCCINT||||||||||
P74|RESET|GSR/I|I/O/GSR||||||||||
P75|SPARE3|I|I/O|INPUT|||||||||
P76|SOUTH_OC|I|I/O/GTS1|INPUT|||||||||
P77|NORTH_OC|I|I/O/GTS2|INPUT|||||||||
P78|VCC||VCCINT||||||||||
P79|SPARE4|I|I/O|INPUT|||||||||
P80|HA_STOP_E_LATCH|O|I/O|OUTPUT|||||||||
P81|TOP_DOMECNTL_SOFTWARE|I|I/O|INPUT|||||||||
P82|HA_STOP_W_LATCH|O|I/O|OUTPUT|||||||||
P83|HA_EMERG_E|I|I/O|INPUT|||||||||
P84|TCS_LOCKOUT|I|I/O|INPUT|||||||||

To preserve the pinout above for future design iterations in
Project Navigator simply execute the (Lock Pins) process
located under the (Implement Design) process in a toolbox named
(Optional Implementation Tools) or invoke PIN2UCF from the
command line. The location constraints will be written into your
specified UCF file