/************************************************************************** ** ** h2.c - support for H2RG IR Arrays. ** *************************************************************************** */ /*-------------------------- ** include files **-------------------------- */ #if LINUX #include #include #include #include #include #else #include // uboot general include file #include // uboot general include file #endif #include "ce.h" #include "ir.h" #include "al.h" #include "h2.h" #include "pnp.h" #define H2_DEBUG 1 #define HDIR_REG_ADDR 0x0001 // Horizontal Direction Register #define GAIN_REG_ADDR 0x0002 // Gain Mode Register #define OUTP_REG_ADDR 0x0004 // Output Buffer Register #define NORM_REG_ADDR 0x0005 // Normal Mode Register #define WINM_REG_ADDR 0x0006 // Window Mode Register #define MISC_REG_ADDR 0x0007 // Misc. Register #define PWRD_REG_ADDR 0x000C // Power Down Register #define OPTN_REG_ADDR 0x000D // Options Register #define PEDESTAL 0x0001 // Pedestal side #define SIGNAL 0x0002 // Signal side #define ARMP_READ_START 8 #define ARMP_READ_START2 9 #define ARMP_READ_START3 10 #define OP_TYPE_READ 1 #define OP_TYPE_RESET 2 #define OP_TYPE_RESET_READ 3 #define OP_TYPE_BGR 4 #define H2RG_TRUE 0x0000 #define H2RG_FALSE 0x0001 #define READ_ODD_FIRST 1 // first hclk, at beginning of frame. #define READ_MIDDLE 5 // does a cnvrt,rd,and hclk #define READ_LAST 6 // the very last pixel of the frame #define READ_DUMMY 7 #define READ_START 8 #define READ_START2 9 #define READ_START3 10 #define TYPE_READ_FIRST_ROW 0 #define TYPE_READ_MIDDLE_ROW 1 #define TYPE_READ_LAST_ROW 2 #define HORIDIRREG {0x0001, 0x0000, 0x0001, 0x0000, 0x0001, 0x0000, 0x0001, 0x0000, 0x0001} #define GAINREG {0x0002, 0x0000, 0x0000, 0x0000, 0x0000, 0x0001, 0x0000, 0x0000, 0x0000} #define OUTPUTMODEREG {0x0003, 0x0000, 0x0001, 0x0000, 0x0000, 0x0001, 0x0001, 0x0001, 0x0000} #define OUTPUTBUFREG {0x0004, 0x0001, 0x0000, 0x0000, 0x0000, 0x0001, 0x0000, 0x0000, 0x0000} #define NORMALMODEREG {0x0005, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000} #define WINDOWMODEREG {0x0006, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000} #define MISCREG {0x0007, 0x0000, 0x0000, 0x0001, 0x0001, 0x0000, 0x0000, 0x0000, 0x0000} #define POWERDOWNREG {0x000A, 0x0001, 0x0000, 0x0001, 0x0000, 0x0001, 0x0000, 0x0001, 0x0000} #define OPTIONSREG {0x000B, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000} //#define FIXME struct h2rg_register { const unsigned int address; unsigned int bit0; unsigned int bit1; unsigned int bit2; unsigned int bit3; unsigned int bit4; unsigned int bit5; unsigned int bit6; unsigned int bit7; }; struct outputmodereg { const unsigned int address; unsigned int mode1; unsigned int mode4; unsigned int mode32; unsigned int wmouten; unsigned int refpixen; unsigned int refmode; unsigned int refvolt; unsigned int refrow; }; struct outputbufreg { const unsigned int address; unsigned int sfena; unsigned int sfenb; unsigned int nosfa; unsigned int nosfb; unsigned int highohm; unsigned int fastbuf; unsigned int nofbufa; unsigned int nofbufb; }; struct normalmodereg { const unsigned int address; unsigned int vmode; unsigned int hmode; unsigned int vinvdir; unsigned int unused; unsigned int vedge; unsigned int hedge; unsigned int rstedge; unsigned int global; }; struct miscreg { const unsigned int address; unsigned int vwmem; unsigned int hwmem; unsigned int vrstb; unsigned int hrstb; unsigned int fasten; unsigned int sampclk; unsigned int clkmod; unsigned int unused; }; struct powerdownreg { const unsigned int address; unsigned int pdref0; unsigned int pdref1; unsigned int pdref2; unsigned int pdref3; unsigned int pdref4; unsigned int pdref5; unsigned int pdref6; unsigned int pdref7; }; struct horidirreg { const unsigned int address; unsigned int hinvdir0; unsigned int hinvdir1; unsigned int hinvdir2; unsigned int hinvdir3; unsigned int hinvdir4; unsigned int hinvdir5; unsigned int hinvdir6; unsigned int hinvdir7; }; struct gainreg { const unsigned int address; unsigned int gain0; unsigned int gain1; unsigned int gain2; unsigned int gain3; unsigned int capen; unsigned int unused; unsigned int vtesten; unsigned int htesten; }; struct windowmodereg { unsigned int address; unsigned int vmodwm; unsigned int hmodwm; unsigned int vdirwm; unsigned int hdirwm; unsigned int vedgwm; unsigned int hedgwm; unsigned int redgwm; unsigned int globwm; }; struct optionsreg { const unsigned int address; unsigned int pdck; unsigned int pdckwm; unsigned int ifctrl; unsigned int doen; unsigned int unused0; unsigned int unused1; unsigned int unused2; unsigned int unused3; }; struct horidirreg hori_dir_reg = HORIDIRREG; struct gainreg gain_reg = GAINREG; struct outputmodereg output_mode_reg = OUTPUTMODEREG; struct outputbufreg output_buf_reg = OUTPUTBUFREG; struct normalmodereg normal_mode_reg = NORMALMODEREG; struct windowmodereg window_mode_reg = WINDOWMODEREG; struct miscreg misc_reg = MISCREG; struct powerdownreg power_down_reg = POWERDOWNREG; struct optionsreg options_reg = OPTIONSREG; // FLAGS unsigned int readoutArrayFlag1 = FALSE; unsigned int termination_type = TERMINATION_NONE; unsigned int reset_first_read = 0; unsigned int painintheass = 0; unsigned int painintheass2 = 0; unsigned int single_line_mode = 0; unsigned int refrow = 0; unsigned int omreg_refvoltagemode = 0; unsigned int reference_row_enable = 0; // PARAMETERS unsigned int slowcounts = 0; // slow shift reset times/pattern // This resets the slow shift register, which controls the vertical pointer //initial condition #define ssr_before_fsyncb_duration 0x047E //0x0025 #define ssr_before_fsyncb_value 0x134C //toggle FSYNCB low then high to clear and load the slow shift register #define ssr_during_fsyncb_duration 0x047E //0x0025 #define ssr_during_fsyncb_value 0x130C //return to initial condition #define ssr_after_fsyncb_duration 0x047E //0x0025 #define ssr_after_fsyncb_value 0x134C // digio bit pattern for initial conditions #define dbp_initial_conditions (D_MAINRSTB | D_FSYNCB | D_HRESETB | D_LSYNCB | D_CSB) unsigned int current_digio_bit_setting = 0x0; unsigned int current_ppg4_bit_setting = 0x0; unsigned int current_spg4_bit_setting = 0x0; extern struct pattern_generator_4 ppg4; extern struct pattern_generator_4 pg4; extern struct ir_param_t Ip; struct fifo_buffer fb_first_row; struct fifo_buffer fb_middle_row; struct fifo_buffer fb_last_row; /** * * H2RG IR ROUTINES, all declared here are static * */ static int h2rg_reset_registers_ir(struct ir_ce_buf_t *ce_sample_buf, unsigned short *digout, FILE *fp); static int h2rg_program_register_ir(struct ir_ce_buf_t *ce_sample_buf, unsigned short *digout, struct h2rg_register *reg_info, FILE *fp); static int h2rg_precondition_fast_shift_register_ir(struct ir_ce_buf_t *ce_sample_buf, unsigned short *digout, FILE *fp); static int h2rg_slow_shift_reset_for_readout_ir(struct ir_ce_buf_t *ce_sample_buf, unsigned short *digout, FILE *fp); static int h2rg_readout_row_basic_ir(struct ir_ce_buf_t *ce_sample_buf, unsigned short *digout, int row_type, FILE *fp); static int h2rg_reset_row_basic_ir(struct ir_ce_buf_t *ce_sample_buf, unsigned short *digout, int row_type, FILE *fp); static int h2rg_terminate_readout_ir(struct ir_ce_buf_t *ce_sample_buf, unsigned short *digout, int termination_type, FILE *fp); static int h2rg_terminate_reference_enable(struct ir_ce_buf_t *ce_sample_buf, unsigned short *digout, FILE *fp); static int h2rg_readout_row_basic_first_ir(struct ir_ce_buf_t *ce_sample_buf, unsigned short *digout, FILE *fp); static int h2rg_readout_row_basic_middle_ir(struct ir_ce_buf_t *ce_sample_buf, unsigned short *digout, FILE *fp); static int h2rg_readout_row_basic_last_ir(struct ir_ce_buf_t *ce_sample_buf, unsigned short *digout, FILE *fp); static int h2rg_reset_row_basic_first_ir(struct ir_ce_buf_t *ce_sample_buf, unsigned short *digout, FILE *fp); static int h2rg_reset_row_basic_middle_ir(struct ir_ce_buf_t *ce_sample_buf, unsigned short *digout, FILE *fp); static int h2rg_reset_row_basic_last_ir(struct ir_ce_buf_t *ce_sample_buf, unsigned short *digout, FILE *fp); static int h2rg_address_next_row_ir(struct ir_ce_buf_t *ce_sample_buf, unsigned short *digout, FILE *fp); static int h2rg_add_read_first_pixel_ir(struct ir_ce_buf_t *ce_sample_buf, unsigned short *digout, FILE *fp); static int h2rg_add_read_middle_pixel_ir(struct ir_ce_buf_t *ce_sample_buf, unsigned short *digout, unsigned int type, unsigned int operation_type, int pixel_count, FILE *fp); static int h2rg_add_read_middle_pixel_f5_ir(struct ir_ce_buf_t *ce_sample_buf, unsigned short *digout, FILE *fp); static int h2rg_add_read_middle_pixel_f4_ir(struct ir_ce_buf_t *ce_sample_buf,unsigned short *digout, FILE *fp); static int h2rg_add_read_middle_pixel_s2_ir(struct ir_ce_buf_t *ce_sample_buf,unsigned short *digout, unsigned int operation_type, FILE *fp); static int h2rg_add_read_middle_pixel_s3_ir(struct ir_ce_buf_t *ce_sample_buf, unsigned short *digout, FILE *fp); static int h2rg_add_read_pixel_very_last_ir(struct ir_ce_buf_t *ce_sample_buf, unsigned short *digout, unsigned int operation_type, FILE *fp); static int h2rg_program_ppg_ir(struct ir_ce_buf_t *ce_sample_buf, int reps, short scale, unsigned short *durations, unsigned short *bits, FILE *fp); static int h2rg_program_vpg_ir(struct ir_ce_buf_t *ce_sample_buf, int reps, unsigned short *pg3_durations, unsigned short *pg3_bits, unsigned short *pg4_durations, unsigned short *pg4_bits, FILE *fp); static int h2rg_set_ppg_ir(struct ir_ce_buf_t *ce_sample_buf, unsigned short value, unsigned short duration, FILE *fp); static int h2rg_set_ppg_3way_ir(struct ir_ce_buf_t *ce_sample_buf, unsigned short value1, unsigned short duration1, unsigned short value2, unsigned short duration2, unsigned short value3, unsigned short int duration3, FILE *fp); static int h2rg_set_vpg4_3way_ir(struct ir_ce_buf_t *ce_sample_buf, unsigned short value1, unsigned short duration1, unsigned short value2, unsigned short duration2, unsigned short value3, unsigned short duration3, unsigned short value_pg3, FILE *fp); #ifdef LATER static int h2rg_set_vpg3_3way_ir(struct ir_ce_buf_t *ce_sample_buf, unsigned short value1, unsigned short duration1, unsigned short value2, unsigned short duration2, unsigned short value3, unsigned short duration3, unsigned short value_pg4, FILE *fp); #endif unsigned short digout, digout_hi; /** * * H2RG IR routines, all defined here are declared in h2.h * */ int h2rg_t1_ir(ce_t *Ce) { printf("h2rg_t1\n"); pnp_shutter_open(Ce); pnp_shutter_close(Ce); pnp_stop(Ce); pnp_digio_low(Ce, 0xAA); pnp_start(Ce); return PASS; } int h2rg_test_ir( struct ir_ce_buf_t *ce_sample_buf, FILE *fp ) { /* int ii; int bits = 0x1; */ printf("h2rg_test_ir(...)\n"); ir_ce_digout_lo(&digout, 0xFFFF, 0, ce_sample_buf, fp); ir_ce_digout_hi(&digout_hi, 0xFFFF, 0, ce_sample_buf, fp); #ifdef FUGGADABOUTIT ir_ce_digout_lo(&digout, 0, D_MAINRSTB, ce_sample_buf, fp); ir_ce_digout_lo(&digout, D_MAINRSTB, D_FASTPADEN, ce_sample_buf, fp); ir_ce_digout_lo(&digout, D_FASTPADEN, D_SAMPLECLK, ce_sample_buf, fp); ir_ce_digout_lo(&digout, D_SAMPLECLK, D_BUFDISABLE, ce_sample_buf, fp); ir_ce_digout_lo(&digout, D_BUFDISABLE, D_DATACLK, ce_sample_buf, fp); ir_ce_digout_lo(&digout, D_DATACLK, D_DATAIN, ce_sample_buf, fp); ir_ce_digout_lo(&digout, D_DATAIN , D_VRESETB, ce_sample_buf, fp); ir_ce_digout_lo(&digout, D_VRESETB , D_FSYNCB, ce_sample_buf, fp); ir_ce_digout_lo(&digout, D_FSYNCB, D_HRESETB, ce_sample_buf, fp); ir_ce_digout_lo(&digout, D_HRESETB, D_LSYNCB, ce_sample_buf, fp); ir_ce_digout_lo(&digout, D_LSYNCB, D_HTESTEN, ce_sample_buf, fp); ir_ce_digout_lo(&digout, D_HTESTEN, D_READEN, ce_sample_buf, fp); ir_ce_digout_lo(&digout, D_READEN, D_CSB, ce_sample_buf, fp); ir_ce_digout_lo(&digout, D_CSB, D_LA0, ce_sample_buf, fp); ir_ce_digout_lo(&digout, D_LA0, D_LA1, ce_sample_buf, fp); ir_ce_digout_lo(&digout, D_LA1, 0, ce_sample_buf, fp); ir_ce_digout_lo(&digout, 0xFFFF, 0, ce_sample_buf, fp); ir_ce_digout_lo(&digout, 0, 0xFFFF, ce_sample_buf, fp); ir_ce_digout_lo(&digout, 0xFFFF, 0, ce_sample_buf, fp); ir_ce_digout_lo(&digout, 0, 0xFFFF, ce_sample_buf, fp); ir_ce_digout_lo(&digout, 0xFFFF, 0, ce_sample_buf, fp); ir_ce_digout_lo(&digout, 0, 0xFFFF, ce_sample_buf, fp); ir_ce_digout_lo(&digout, 0xFFFF, 0, ce_sample_buf, fp); ir_ce_digout_lo(&digout, 0, 0xFFFF, ce_sample_buf, fp); ir_ce_digout_lo(&digout, 0xFFFF, 0, ce_sample_buf, fp); ir_ce_digout_lo(&digout, 0, 0xFFFF, ce_sample_buf, fp); ir_ce_digout_lo(&digout, 0xFFFF, 0, ce_sample_buf, fp); #endif /* for(ii = 0; ii < 16; ii++) { ir_ce_digout_lo(&digout, 0, D_MAINRSTB, ce_sample_buf, fp); bits = bits << 1; bits = bits | 0x1; } */ ir_ce_digout_lo(&digout, 0, D_MAINRSTB, ce_sample_buf, fp); ir_ce_cmd_delay(ce_sample_buf, 10, fp); ir_ce_digout_lo(&digout, 0xFFFF, 0, ce_sample_buf, fp); ir_ce_digout_lo(&digout, 0, D_MAINRSTB, ce_sample_buf, fp); ir_ce_cmd_delay(ce_sample_buf, 20, fp); ir_ce_digout_lo(&digout, 0xFFFF, 0, ce_sample_buf, fp); ir_ce_digout_lo(&digout, 0, D_MAINRSTB, ce_sample_buf, fp); ir_ce_cmd_delay(ce_sample_buf, 30, fp); ir_ce_digout_lo(&digout, 0xFFFF, 0, ce_sample_buf, fp); ir_ce_digout_lo(&digout, 0, D_MAINRSTB, ce_sample_buf, fp); ir_ce_cmd_delay(ce_sample_buf, 40, fp); ir_ce_digout_lo(&digout, 0xFFFF, 0, ce_sample_buf, fp); ir_ce_digout_lo(&digout, 0, D_MAINRSTB, ce_sample_buf, fp); ir_ce_cmd_delay(ce_sample_buf, 50, fp); ir_ce_digout_lo(&digout, 0xFFFF, 0, ce_sample_buf, fp); ir_ce_digout_lo(&digout, 0, D_MAINRSTB, ce_sample_buf, fp); ir_ce_cmd_delay(ce_sample_buf, 60, fp); ir_ce_digout_lo(&digout, 0xFFFF, 0, ce_sample_buf, fp); return PASS; } int h2rg_init_ir() { int ii = 0; /* start with all bits initialized to 0 */ digout = 0; digout_hi = 0; h2rg_settings.subarray_count = 1; for(ii = 0; ii < 3; ii++) { h2rg_settings.darray[0].x = 0; h2rg_settings.darray[0].y = 0; h2rg_settings.darray[0].wid = 2048; h2rg_settings.darray[0].hgt = 2048; } h2rg_settings.slow_counts = 0; h2rg_settings.termination_type = TERMINATION_NONE; h2rg_settings.reset_enable = 0; h2rg_settings.omg_refvoltagemode = 0; return PASS; } int h2rg_bgrclock(int usecs) { return PASS; } int h2rg_bgren(int onoff) { return PASS; } int h2rg_bgrrest(int usecs) { return PASS; } int h2rg_bgrwait(int usecs) { return PASS; } int h2rg_itime(double itime) { return PASS; } int h2rg_rdr(int onoff) { return PASS; } int h2rg_rom(int mode) { return PASS; } int h2rg_rren(int onoff) { return PASS; } int h2rg_setrstm(int mode) { return PASS; } int h2rg_setttf(int type) { return PASS; } int h2rg_setttl(char *type) { return PASS; } int h2rg_setvrd(int updown) { return PASS; } int h2rg_setwd(int welldepth) { return PASS; } int h2rg_slowcnt(int slowcnt) { return PASS; } int h2rg_surwt(int usecs) { return PASS; } int h2rge_suram(int mode) { return PASS; } int h2rge_setreg(char *regname, char *op, char *bits[]) { return PASS; } int h2rge_setemd(char *mode) { return PASS; } int h2rge_setspr(int *mode) { return PASS; } int h2rge_selsp(int x, int y) { return PASS; } int h2rge_selsl(int y) { return PASS; } int h2rge_vbg(float vbiasgate) { return PASS; } int h2rge_vds(float vdsub) { return PASS; } int h2rge_vrst(float vreset) { return PASS; } int h2rge_psswd(char *passwd) { return PASS; } int h2rg_generate_ce_array_setup_ir(struct ir_ce_buf_t *ce_sample_buf, struct h2rg_settings_t *h2rg_settings, FILE *fp ) { int digout_ns, ts_ns; printf("h2rg_generate_ce_array_setup_ir(...)\n"); if ( fp ) { ir_printf( fp, "#-------h2rg_generate_ce_readout_setup(...) ---------------------\n"); ir_printf( fp, "# h2rg_settings.slow_counts = %d \n", h2rg_settings->slow_counts); ir_printf( fp, "# h2rg_settings.numdarray = %d \n", h2rg_settings->subarray_count); } digout_ns = IR_CE_PARAM_UPDWR_LO_NS + IR_CE_CMD_UPDWR_NS; /* time to do a digout = 50+30 ns */ ts_ns = ir_ce_slowcnt_to_ns(h2rg_settings->slow_counts); /* one TS in nano seconds */ ir_printf( fp, "# ts_ns=%d ns \n", ts_ns); /* init the ce_sample_buf to make sure it's empty. */ ir_ce_clear( ce_sample_buf ); ir_ce_digout_lo(&digout, 0, dbp_initial_conditions, ce_sample_buf, fp); ir_ce_digout_hi(&digout_hi, 0, 0x01, ce_sample_buf, fp); ir_ce_digout_lo(&digout, 0xFFFF, 0, ce_sample_buf, fp); ir_ce_digout_lo(&digout, 0, dbp_initial_conditions, ce_sample_buf, fp); h2rg_reset_registers_ir(ce_sample_buf, &digout, fp); h2rg_program_register_ir(ce_sample_buf, &digout, (struct h2rg_register *)&normal_mode_reg, fp); h2rg_program_register_ir(ce_sample_buf, &digout, (struct h2rg_register *)&output_buf_reg, fp); h2rg_program_register_ir(ce_sample_buf, &digout, (struct h2rg_register *)&hori_dir_reg, fp); h2rg_program_register_ir(ce_sample_buf, &digout, (struct h2rg_register *)&gain_reg, fp); h2rg_program_register_ir(ce_sample_buf, &digout, (struct h2rg_register *)&window_mode_reg, fp); h2rg_program_register_ir(ce_sample_buf, &digout, (struct h2rg_register *)&misc_reg, fp); h2rg_program_register_ir(ce_sample_buf, &digout, (struct h2rg_register *)&power_down_reg, fp); h2rg_program_register_ir(ce_sample_buf, &digout, (struct h2rg_register *)&options_reg, fp); if (h2rg_settings->termination_type == TERMINATION_REFERENCE_ENABLE) h2rg_program_register_ir(ce_sample_buf, &digout, (struct h2rg_register *)&output_mode_reg, fp); h2rg_precondition_fast_shift_register_ir(ce_sample_buf, &digout, fp); return PASS; } int h2rg_generate_ce_readout_s_ir ( struct ir_ce_buf_t *ce_sample_buf, struct h2rg_settings_t *h2rg_settings, FILE *fp ) { int digout_ns, ts_ns; //ts_adc, //y, i; int ii = 0; int subarray_pos = 0; //struct ir_ce_adc_t adc_in; if ( fp ) { ir_printf( fp, "#-------h2rg_generate_ce_readout(...) ---------------------\n"); ir_printf( fp, "# h2rg_settings.slow_counts = %d \n", h2rg_settings->slow_counts); ir_printf( fp, "# h2rg_settings.numdarray = %d \n", h2rg_settings->subarray_count); } digout_ns = IR_CE_PARAM_UPDWR_LO_NS + IR_CE_CMD_UPDWR_NS; /* time to do a digout = 50+30 ns */ ts_ns = ir_ce_slowcnt_to_ns(h2rg_settings->slow_counts); /* one TS in nano seconds */ ir_printf( fp, "# ts_ns=%d ns \n", ts_ns); h2rg_slow_shift_reset_for_readout_ir(ce_sample_buf, &digout, fp); for (subarray_pos = 0; subarray_pos < h2rg_settings->subarray_count; subarray_pos++) { for (ii = 0; ii < h2rg_settings->darray[subarray_pos].y; ii++) h2rg_address_next_row_ir(ce_sample_buf,&digout, fp); h2rg_readout_row_basic_ir(ce_sample_buf,&digout, TYPE_READ_FIRST_ROW, fp); #ifdef FIXME need to fix following line so it handles ifheight - 2 is less than zero #endif for (ii = 0; ii < (h2rg_settings->darray[subarray_pos].hgt - 2); ii++) h2rg_readout_row_basic_ir(ce_sample_buf, &digout,TYPE_READ_MIDDLE_ROW, fp); h2rg_readout_row_basic_ir(ce_sample_buf, &digout,TYPE_READ_LAST_ROW, fp); h2rg_terminate_readout_ir(ce_sample_buf,&digout, h2rg_settings->termination_type, fp); } return PASS; } int h2rg_generate_ce_readout_m_ir ( struct ir_ce_buf_t *ce_sample_buf, struct h2rg_settings_t *h2rg_settings, FILE *fp ) { return PASS; } int h2rg_generate_ce_reset_s_ir ( struct ir_ce_buf_t *ce_sample_buf, struct h2rg_settings_t *h2rg_settings, FILE *fp ) { int digout_ns, ts_ns; //ts_adc, //y, i; int ii = 0; int subarray_pos = 0; //struct ir_ce_adc_t adc_in; if ( fp ) { ir_printf( fp, "#-------h2rg_generate_ce_reset_s_ir(...) ---------------------\n"); ir_printf( fp, "# h2rg_settings.slow_counts = %d \n", h2rg_settings->slow_counts); ir_printf( fp, "# h2rg_settings.numdarray = %d \n", h2rg_settings->subarray_count); } digout_ns = IR_CE_PARAM_UPDWR_LO_NS + IR_CE_CMD_UPDWR_NS; /* time to do a digout = 50+30 ns */ ts_ns = ir_ce_slowcnt_to_ns(h2rg_settings->slow_counts); /* one TS in nano seconds */ ir_printf( fp, "# ts_ns=%d ns \n", ts_ns); h2rg_slow_shift_reset_for_readout_ir(ce_sample_buf, &digout, fp); for (subarray_pos = 0; subarray_pos < h2rg_settings->subarray_count; subarray_pos++) { for (ii = 0; ii < h2rg_settings->darray[subarray_pos].y; ii++) h2rg_address_next_row_ir(ce_sample_buf,&digout, fp); h2rg_reset_row_basic_ir(ce_sample_buf,&digout, TYPE_READ_FIRST_ROW, fp); #ifdef FIXME need to fix following line so it handles ifheight - 2 is less than zero #endif for (ii = 0; ii < h2rg_settings->darray[subarray_pos].hgt - 2; ii++) h2rg_reset_row_basic_ir(ce_sample_buf, &digout,TYPE_READ_MIDDLE_ROW, fp); h2rg_reset_row_basic_ir(ce_sample_buf, &digout,TYPE_READ_LAST_ROW, fp); h2rg_terminate_readout_ir(ce_sample_buf,&digout, h2rg_settings->termination_type, fp); } return PASS; } int h2rg_generate_ce_reset_m_ir ( struct ir_ce_buf_t *ce_sample_buf, struct h2rg_settings_t *h2rg_settings, FILE *fp ) { return PASS; } int h2rg_check_subarray ( int subarray_count, struct ir_array_t *da) { return PASS; } /** * * H2RG IR routines, all defined here are static * */ static int h2rg_reset_registers_ir(struct ir_ce_buf_t *ce_sample_buf, unsigned short *digout, FILE *fp) { ir_ce_digout_lo(digout, 0, 0, ce_sample_buf, fp); ir_ce_digout_lo(digout, D_FSYNCB, 0, ce_sample_buf, fp); ir_ce_digout_lo(digout, 0, 0, ce_sample_buf, fp); return PASS; } static int h2rg_program_register_ir(struct ir_ce_buf_t *ce_sample_buf, unsigned short *digout, struct h2rg_register *reg_info, FILE *fp) { int ii = 0; unsigned int *bits; if (fp) ir_printf(fp, "# printing to register address %i\n", reg_info->address); /* take CSB low */ ir_ce_digout_lo(digout, D_DATACLK, 0, ce_sample_buf, fp); ir_ce_digout_lo(digout, D_CSB, 0, ce_sample_buf, fp); #ifdef FIXME insert delays between transitions #endif /* program the address bits */ for (ii = 0; ii < 4; ii++) { /* set or clear the dtatin line */ if (reg_info->address & (0x8 >> ii)) ir_ce_digout_lo(digout, 0, D_DATACLK, ce_sample_buf, fp); else ir_ce_digout_lo(digout, D_DATACLK, 0, ce_sample_buf, fp); #ifdef FIXME insert delay here #endif /* transition the data clk */ ir_ce_digout_lo(digout, 0, D_DATACLK, ce_sample_buf, fp); ir_ce_digout_lo(digout, D_DATACLK, 0, ce_sample_buf, fp); } /* program the data bits */ bits = &(reg_info->bit0); for (ii = 0; ii < 12; ii++) { /* set or clear the dtatin line */ if (bits[ii] > 0) ir_ce_digout_lo(digout, 0, D_DATACLK, ce_sample_buf, fp); else ir_ce_digout_lo(digout, D_DATACLK, 0, ce_sample_buf, fp); #ifdef FIXME insert delay here #endif /* transition the data clk */ ir_ce_digout_lo(digout, 0, D_DATACLK, ce_sample_buf, fp); ir_ce_digout_lo(digout, D_DATACLK, 0, ce_sample_buf, fp); } #ifdef FIXME insert delay here #endif ir_ce_digout_lo(digout, 0, D_CSB, ce_sample_buf, fp); return PASS; } static int h2rg_precondition_fast_shift_register_ir(struct ir_ce_buf_t *ce_sample_buf, unsigned short *digout, FILE *fp) { int ii = 0; unsigned short vpg4_durations[IR_CE_VSEQ_N]; unsigned short vpg4_bits[IR_CE_VSEQ_N]; unsigned short vpg3_durations[IR_CE_VSEQ_N]; unsigned short vpg3_bits[IR_CE_VSEQ_N]; if (fp) { ir_printf( fp, "#-------h2rg_precondition_fast_shift_register_ir(...) ---------------------\n"); } /* take LSYNC lo */ ir_ce_digout_lo(digout, D_LSYNCB, 0, ce_sample_buf, fp); /* HCLK 0*/ /* take hclk hi, then low, twice*/ vpg4_durations[0] = 1; vpg4_bits[0] = PG4_HCLK; vpg4_durations[1] = 1; vpg4_bits[1] = PG4_HCLK; vpg4_durations[2] = 1; vpg4_bits[2] = PG4_HCLK; vpg4_durations[3] = 1; vpg4_bits[3] = PG4_HCLK; vpg4_durations[4] = 1; vpg4_bits[4] = PG4_HCLK; vpg4_durations[5] = 1; vpg4_bits[5] = 0; vpg4_durations[6] = 1; vpg4_bits[6] = 0; vpg4_durations[7] = 1; vpg4_bits[7] = 0; vpg4_durations[8] = 1; vpg4_bits[8] = 0; for (ii = 0; ii < IR_CE_VSEQ_N; ii++) { vpg3_durations[ii] = 1; vpg3_bits[ii] = 0; } h2rg_program_vpg_ir(ce_sample_buf, 2, (unsigned short *)&vpg3_durations, (unsigned short *)&vpg3_bits, (unsigned short *)&vpg4_durations, (unsigned short *)&vpg4_bits, fp); /* take LSYNC hi*/ ir_ce_digout_lo(digout, 0, D_LSYNCB, ce_sample_buf, fp); /* HCLK 1*/ /* take hclk hi, then low*/ vpg4_durations[0] = 1; vpg4_bits[0] = PG4_HCLK; vpg4_durations[1] = 1; vpg4_bits[1] = PG4_HCLK; vpg4_durations[2] = 1; vpg4_bits[2] = PG4_HCLK; vpg4_durations[3] = 1; vpg4_bits[3] = PG4_HCLK; vpg4_durations[4] = 1; vpg4_bits[4] = PG4_HCLK; vpg4_durations[5] = 1; vpg4_bits[5] = 0; vpg4_durations[6] = 1; vpg4_bits[6] = 0; vpg4_durations[7] = 1; vpg4_bits[7] = 0; vpg4_durations[8] = 1; vpg4_bits[8] = 0; for (ii = 0; ii < IR_CE_VSEQ_N; ii++) { vpg3_durations[ii] = 1; vpg3_bits[ii] = 0; } h2rg_program_vpg_ir(ce_sample_buf, 1, (unsigned short *)&vpg3_durations, (unsigned short *)&vpg3_bits, (unsigned short *)&vpg4_durations, (unsigned short *)&vpg4_bits, fp); /* HCLK 2 */ /* take hclk hi, then low*/ vpg4_durations[0] = 1; vpg4_bits[0] = PG4_HCLK; vpg4_durations[1] = 1; vpg4_bits[1] = PG4_HCLK; vpg4_durations[2] = 1; vpg4_bits[2] = PG4_HCLK; vpg4_durations[3] = 1; vpg4_bits[3] = PG4_HCLK; vpg4_durations[4] = 1; vpg4_bits[4] = PG4_HCLK; vpg4_durations[5] = 1; vpg4_bits[5] = 0; vpg4_durations[6] = 1; vpg4_bits[6] = 0; vpg4_durations[7] = 1; vpg4_bits[7] = 0; vpg4_durations[8] = 1; vpg4_bits[8] = 0; for (ii = 0; ii < IR_CE_VSEQ_N; ii++) { vpg3_durations[ii] = 1; vpg3_bits[ii] = 0; } h2rg_program_vpg_ir(ce_sample_buf, 1, (unsigned short *)&vpg3_durations, (unsigned short *)&vpg3_bits, (unsigned short *)&vpg4_durations, (unsigned short *)&vpg4_bits, fp); /* take LSYNC low */ ir_ce_digout_lo(digout, D_LSYNCB, 0, ce_sample_buf, fp); /* take hclk hi, then low, 63 times */ vpg4_durations[0] = 1; vpg4_bits[0] = PG4_HCLK; vpg4_durations[1] = 1; vpg4_bits[1] = PG4_HCLK; vpg4_durations[2] = 1; vpg4_bits[2] = PG4_HCLK; vpg4_durations[3] = 1; vpg4_bits[3] = PG4_HCLK; vpg4_durations[4] = 1; vpg4_bits[4] = PG4_HCLK; vpg4_durations[5] = 1; vpg4_bits[5] = 0; vpg4_durations[6] = 1; vpg4_bits[6] = 0; vpg4_durations[7] = 1; vpg4_bits[7] = 0; vpg4_durations[8] = 1; vpg4_bits[8] = 0; for (ii = 0; ii < IR_CE_VSEQ_N; ii++) { vpg3_durations[ii] = 1; vpg3_bits[ii] = 0; } h2rg_program_vpg_ir(ce_sample_buf, 63, (unsigned short *)&vpg3_durations, (unsigned short *)&vpg3_bits, (unsigned short *)&vpg4_durations, (unsigned short *)&vpg4_bits, fp); /* take hclk hi, then low*/ vpg4_durations[0] = 1; vpg4_bits[0] = PG4_HCLK; vpg4_durations[1] = 1; vpg4_bits[1] = PG4_HCLK; vpg4_durations[2] = 1; vpg4_bits[2] = PG4_HCLK; vpg4_durations[3] = 1; vpg4_bits[3] = PG4_HCLK; vpg4_durations[4] = 1; vpg4_bits[4] = PG4_HCLK; vpg4_durations[5] = 1; vpg4_bits[5] = 0; vpg4_durations[6] = 1; vpg4_bits[6] = 0; vpg4_durations[7] = 1; vpg4_bits[7] = 0; vpg4_durations[8] = 1; vpg4_bits[8] = 0; for (ii = 0; ii < IR_CE_VSEQ_N; ii++) { vpg3_durations[ii] = 1; vpg3_bits[ii] = 0; } h2rg_program_vpg_ir(ce_sample_buf, 1, (unsigned short *)&vpg3_durations, (unsigned short *)&vpg3_bits, (unsigned short *)&vpg4_durations, (unsigned short *)&vpg4_bits, fp); /* take LSYNC hi*/ ir_ce_digout_lo(digout, 0, D_LSYNCB, ce_sample_buf, fp); return PASS; } /** * see add_slow_shift_reset_for_readout(...) in rs3 code * */ static int h2rg_slow_shift_reset_for_readout_ir( struct ir_ce_buf_t *ce_sample_buf, unsigned short *digout, FILE *fp) { /* Expecting D_FSYNCB to be high going into this, we take it low, then reset it high again. */ ir_ce_digout_lo(digout, D_FSYNCB, 0, ce_sample_buf, fp); ir_ce_digout_lo(digout, 0, D_FSYNCB, ce_sample_buf, fp); return PASS; } /** * see readoutRowALPHA(...) in rs3 code * */ static int h2rg_readout_row_basic_ir( struct ir_ce_buf_t *ce_sample_buf, unsigned short *digout, int row_type, FILE *fp) { switch (row_type) { case TYPE_READ_FIRST_ROW: h2rg_readout_row_basic_first_ir(ce_sample_buf, digout, fp); break; case TYPE_READ_MIDDLE_ROW: h2rg_readout_row_basic_middle_ir(ce_sample_buf, digout, fp); break; case TYPE_READ_LAST_ROW: h2rg_readout_row_basic_last_ir(ce_sample_buf, digout, fp); break; default: return FAIL; } return PASS; } /** * see readoutRowALPHA(...) in rs3 code * */ static int h2rg_reset_row_basic_ir( struct ir_ce_buf_t *ce_sample_buf, unsigned short *digout, int row_type, FILE *fp) { switch (row_type) { case TYPE_READ_FIRST_ROW: h2rg_reset_row_basic_first_ir(ce_sample_buf, digout, fp); break; case TYPE_READ_MIDDLE_ROW: h2rg_reset_row_basic_middle_ir(ce_sample_buf, digout, fp); break; case TYPE_READ_LAST_ROW: h2rg_reset_row_basic_last_ir(ce_sample_buf, digout, fp); break; default: return FAIL; } h2rg_address_next_row_ir(ce_sample_buf, digout, fp); return PASS; } /* static unsigned long h2rg_readout_fb_first_row(void) */ static int h2rg_readout_row_basic_first_ir(struct ir_ce_buf_t *ce_sample_buf, unsigned short *digout, FILE *fp) { h2rg_add_read_first_pixel_ir(ce_sample_buf, digout, fp); //add_read_pixelALPHAFirst(side,this.READ_ODD_FIRST, ((modifier | LSYNC_LINE) & 0xF7FF), operation_type); h2rg_add_read_middle_pixel_ir(ce_sample_buf, digout, READ_START3, OP_TYPE_READ, 1, fp); //add_read_pixelALPHAMiddle(side,this.READ_START3,modifier | LSYNC_LINE, operation_type); h2rg_add_read_middle_pixel_f5_ir(ce_sample_buf, digout, fp); //add_read_pixelALPHAMiddleSPANKED5(side,this.READ_MIDDLE,modifier, operation_type); h2rg_add_read_middle_pixel_ir(ce_sample_buf, digout, READ_MIDDLE, OP_TYPE_READ, 63, fp); //add_read_pixelALPHAMiddle(side,this.READ_MIDDLE,modifier, operation_type); h2rg_add_read_middle_pixel_s2_ir(ce_sample_buf, digout, OP_TYPE_READ, fp); //add_read_pixelALPHAMiddleSpecial2(side,this.READ_MIDDLE,modifier , operation_type); return PASS; } /* static unsigned long h2rg_readout_fb_middle_row(void) */ static int h2rg_readout_row_basic_middle_ir(struct ir_ce_buf_t *ce_sample_buf, unsigned short *digout, FILE *fp) { h2rg_add_read_middle_pixel_ir(ce_sample_buf, digout, READ_START2, OP_TYPE_READ, 1, fp); //add_read_pixelALPHAMiddle(side,this.READ_START2,modifier | LSYNC_LINE, operation_type); h2rg_add_read_middle_pixel_f4_ir(ce_sample_buf, digout, fp); //add_read_pixelALPHAMiddleSPANKED4(side,this.READ_MIDDLE,modifier, operation_type); h2rg_add_read_middle_pixel_ir(ce_sample_buf, digout, READ_MIDDLE, OP_TYPE_READ, 63, fp); //add_read_pixelALPHAMiddle(side,this.READ_MIDDLE,modifier, operation_type); h2rg_add_read_middle_pixel_s2_ir(ce_sample_buf, digout, OP_TYPE_READ, fp); //add_read_pixelALPHAMiddleSpecial2(side,this.READ_MIDDLE,modifier , operation_type); return PASS; } /*static unsigned long h2rg_readout_fb_last_row() */ static int h2rg_readout_row_basic_last_ir(struct ir_ce_buf_t *ce_sample_buf, unsigned short *digout, FILE *fp) { h2rg_add_read_middle_pixel_ir(ce_sample_buf, digout, READ_START2, OP_TYPE_READ, 0, fp); //add_read_pixelALPHAMiddle(side,this.READ_START2,modifier | LSYNC_LINE, operation_type); h2rg_add_read_middle_pixel_f4_ir(ce_sample_buf, digout, fp); //add_read_pixelALPHAMiddleSPANKED4(side,this.READ_MIDDLE,modifier, operation_type); h2rg_add_read_middle_pixel_ir(ce_sample_buf,digout, READ_MIDDLE, OP_TYPE_READ, 63, fp); //add_read_pixelALPHAMiddle(side,this.READ_MIDDLE,modifier, operation_type); h2rg_add_read_middle_pixel_s3_ir(ce_sample_buf, digout, fp); //add_read_pixelALPHAMiddleSpecial3(side,this.READ_MIDDLE,modifier, operation_type); h2rg_add_read_pixel_very_last_ir(ce_sample_buf, digout, OP_TYPE_READ, fp); //add_read_pixel_ALPHAVeryLast(side,this.READ_LAST,modifier, operation_type); return PASS; } /* static unsigned long h2rg_readout_fb_first_row(void) */ static int h2rg_reset_row_basic_first_ir(struct ir_ce_buf_t *ce_sample_buf, unsigned short *digout, FILE *fp) { h2rg_add_read_first_pixel_ir(ce_sample_buf, digout, fp); //add_read_pixelALPHAFirst(side,this.READ_ODD_FIRST, ((modifier | LSYNC_LINE) & 0xF7FF), operation_type); h2rg_add_read_middle_pixel_ir(ce_sample_buf, digout, READ_START3, OP_TYPE_RESET_READ, 1, fp); //add_read_pixelALPHAMiddle(side,this.READ_START3,modifier | LSYNC_LINE, operation_type); h2rg_add_read_middle_pixel_f5_ir(ce_sample_buf, digout, fp); //add_read_pixelALPHAMiddleSPANKED5(side,this.READ_MIDDLE,modifier, operation_type); h2rg_add_read_middle_pixel_ir(ce_sample_buf, digout, READ_MIDDLE, OP_TYPE_RESET_READ, 63, fp); //add_read_pixelALPHAMiddle(side,this.READ_MIDDLE,modifier, operation_type); h2rg_add_read_middle_pixel_s2_ir(ce_sample_buf, digout, OP_TYPE_RESET_READ, fp); //add_read_pixelALPHAMiddleSpecial2(side,this.READ_MIDDLE,modifier , operation_type); return PASS; } /* static unsigned long h2rg_readout_fb_middle_row(void) */ static int h2rg_reset_row_basic_middle_ir(struct ir_ce_buf_t *ce_sample_buf, unsigned short *digout, FILE *fp) { h2rg_add_read_middle_pixel_ir(ce_sample_buf, digout, READ_START2, OP_TYPE_RESET_READ, 1, fp); //add_read_pixelALPHAMiddle(side,this.READ_START2,modifier | LSYNC_LINE, operation_type); h2rg_add_read_middle_pixel_f4_ir(ce_sample_buf, digout, fp); //add_read_pixelALPHAMiddleSPANKED4(side,this.READ_MIDDLE,modifier, operation_type); h2rg_add_read_middle_pixel_ir(ce_sample_buf, digout, READ_MIDDLE, OP_TYPE_RESET_READ, 63, fp); //add_read_pixelALPHAMiddle(side,this.READ_MIDDLE,modifier, operation_type); h2rg_add_read_middle_pixel_s2_ir(ce_sample_buf, digout, OP_TYPE_RESET_READ, fp); //add_read_pixelALPHAMiddleSpecial2(side,this.READ_MIDDLE,modifier , operation_type); return PASS; } /*static unsigned long h2rg_readout_fb_last_row() */ static int h2rg_reset_row_basic_last_ir(struct ir_ce_buf_t *ce_sample_buf, unsigned short *digout, FILE *fp) { h2rg_add_read_middle_pixel_ir(ce_sample_buf, digout, READ_START2, OP_TYPE_RESET_READ, 0, fp); //add_read_pixelALPHAMiddle(side,this.READ_START2,modifier | LSYNC_LINE, operation_type); h2rg_add_read_middle_pixel_f4_ir(ce_sample_buf, digout, fp); //add_read_pixelALPHAMiddleSPANKED4(side,this.READ_MIDDLE,modifier, operation_type); h2rg_add_read_middle_pixel_ir(ce_sample_buf,digout, READ_MIDDLE, OP_TYPE_RESET_READ, 63, fp); //add_read_pixelALPHAMiddle(side,this.READ_MIDDLE,modifier, operation_type); h2rg_add_read_middle_pixel_s3_ir(ce_sample_buf, digout, fp); //add_read_pixelALPHAMiddleSpecial3(side,this.READ_MIDDLE,modifier, operation_type); h2rg_add_read_pixel_very_last_ir(ce_sample_buf, digout, OP_TYPE_RESET_READ, fp); //add_read_pixel_ALPHAVeryLast(side,this.READ_LAST,modifier, operation_type); return PASS; } static int h2rg_address_next_row_ir(struct ir_ce_buf_t *ce_sample_buf, unsigned short *digout, FILE *fp) { unsigned short ppg4_durations[IR_CE_PSEQ_N]; unsigned short ppg4_bits[IR_CE_PSEQ_N]; ppg4_durations[0] = 10; ppg4_bits[0] = 0; ppg4_durations[1] = 10; ppg4_bits[1] = 0; ppg4_durations[2] = 10; ppg4_bits[2] = 0; ppg4_durations[3] = 10; ppg4_bits[3] = 0; ppg4_durations[4] = 40; ppg4_bits[4] = PPG4_VCLK; ppg4_durations[5] = 10; ppg4_bits[5] = 0; ppg4_durations[6] = 10; ppg4_bits[6] = 0; ppg4_durations[7] = 10; ppg4_bits[7] = 0; ppg4_durations[8] = 10; ppg4_bits[8] = 0; h2rg_program_ppg_ir(ce_sample_buf, 1, 0, (unsigned short *)&ppg4_durations, (unsigned short *)&ppg4_bits, fp); return 0; } static int h2rg_add_read_first_pixel_ir(struct ir_ce_buf_t *ce_sample_buf, unsigned short *digout, FILE *fp) { /* Do a line sync to reset the slow shift register */ #ifdef FIXME NOTE: assuming digout value is D_READEN | D_HRESETB | D_FSYNCB | D_CSB | D_MAINRSTB #endif /* take LSYNC hi for 0x000E then lo for 0x000E */ ir_ce_digout_lo(digout, 0, D_LSYNCB, ce_sample_buf, fp); ir_ce_digout_lo(digout, D_LSYNCB, 0, ce_sample_buf, fp); /* do a VCLK to address the next row */ h2rg_set_ppg_3way_ir(ce_sample_buf, 0, 10, PPG4_VCLK, 50, 0, 10, fp); /* raise D_LSYNCB again*/ ir_ce_digout_lo(digout, 0, D_LSYNCB, ce_sample_buf, fp); // duration is 0x000E /* take PG4_HCLK high then low again */ h2rg_set_vpg4_3way_ir(ce_sample_buf,0x0015, 0, 0x0015, PG4_HCLK, 0x0015, 0x0, 0x0, fp); return PASS; } static int h2rg_add_read_middle_pixel_ir(struct ir_ce_buf_t *ce_sample_buf, unsigned short *digout, unsigned int type, unsigned int operation_type, int pixel_count, FILE *fp) { unsigned short pg3_durations[IR_CE_VSEQ_N]; unsigned short pg3_bits[IR_CE_VSEQ_N]; unsigned short pg4_durations[IR_CE_VSEQ_N]; unsigned short pg4_bits[IR_CE_VSEQ_N]; int ii; ir_ce_digout_lo(digout, 0, D_READEN | D_HRESETB | D_FSYNCB | D_CSB | D_MAINRSTB, ce_sample_buf, fp); /* h2_write_digio_value(fb, D_READEN | D_HRESETB | D_FSYNCB | D_CSB | D_MAINRSTB); // duration ix 0x00B8 */ if (type == READ_START) { for (ii = 0; ii < IR_CE_VSEQ_N; ii++) { pg3_durations[ii] = 0; pg3_bits[ii] = 0; } pg4_durations[0] = 100; pg4_bits[0] = 0; pg4_durations[1] = 100; pg4_bits[1] = 0; pg4_durations[2] = 100; pg4_bits[2] = 0; pg4_durations[3] = 100; pg4_bits[3] = PG4_HCLK; pg4_durations[4] = 100; pg4_bits[4] = PG4_HCLK; pg4_durations[5] = 100; pg4_bits[5] = PG4_HCLK; pg4_durations[6] = 100; pg4_bits[6] = 0; pg4_durations[7] = 100; pg4_bits[7] = 0; pg4_durations[8] = 100; pg4_bits[8] = 0; } else if (type == READ_START2) { if (operation_type == OP_TYPE_READ) { for (ii = 0; ii < IR_CE_VSEQ_N; ii++) { pg3_durations[ii] = 0; pg3_bits[ii] = 0; } pg4_durations[0] = 100; pg4_bits[0] = 0; pg4_durations[1] = 100; pg4_bits[1] = 0; pg4_durations[2] = 100; pg4_bits[2] = 0; pg4_durations[3] = 100; pg4_bits[3] = PG4_HCLK; pg4_durations[4] = 100; pg4_bits[4] = (PG4_HCLK) | (PG4_ADC); pg4_durations[5] = 100; pg4_bits[5] = PG4_HCLK; pg4_durations[6] = 100; pg4_bits[6] = 0; pg4_durations[7] = 100; pg4_bits[7] = 0; pg4_durations[8] = 100; pg4_bits[8] = 0; } else if (operation_type == OP_TYPE_RESET) { for (ii = 0; ii < IR_CE_VSEQ_N; ii++) { pg3_durations[ii] = 0; pg3_bits[ii] = PG3_RESETEN; } pg4_durations[0] = 100; pg4_bits[0] = 0; pg4_durations[1] = 100; pg4_bits[1] = 0; pg4_durations[2] = 100; pg4_bits[2] = 0; pg4_durations[3] = 100; pg4_bits[3] = PG4_HCLK; pg4_durations[4] = 100; pg4_bits[4] = ((PG4_HCLK) | (PG4_ADC)); pg4_durations[5] = 100; pg4_bits[5] = PG4_HCLK; pg4_durations[6] = 100; pg4_bits[6] = 0; pg4_durations[7] = 100; pg4_bits[7] = 0; pg4_durations[8] = 100; pg4_bits[8] = 0; } else if (operation_type == OP_TYPE_RESET_READ) { for (ii = 0; ii < IR_CE_VSEQ_N; ii++) { pg3_durations[ii] = 0; pg3_bits[ii] = PG3_RESETEN; } pg4_durations[0] = 100; pg4_bits[0] = 0; pg4_durations[1] = 100; pg4_bits[1] = 0; pg4_durations[2] = 100; pg4_bits[2] = 0; pg4_durations[3] = 100; pg4_bits[3] = PG4_HCLK; pg4_durations[4] = 100; pg4_bits[4] = (PG4_HCLK) | (PG4_ADC); pg4_durations[5] = 100; pg4_bits[5] = PG4_HCLK; pg4_durations[6] = 100; pg4_bits[6] = 0; pg4_durations[7] = 100; pg4_bits[7] = 0; pg4_durations[8] = 100; pg4_bits[8] = 0; } else // operation_type == OP_TYPE_BGR { for (ii = 0; ii < IR_CE_VSEQ_N; ii++) { pg3_durations[ii] = 0; pg3_bits[ii] = PG3_RESETEN; } pg4_durations[0] = 100; pg4_bits[0] = 0; pg4_durations[1] = 100; pg4_bits[1] = 0; pg4_durations[2] = 100; pg4_bits[2] = 0; pg4_durations[3] = 100; pg4_bits[3] = PG4_HCLK; pg4_durations[4] = 100; pg4_bits[4] = (PG4_HCLK) | (PG4_ADC); pg4_durations[5] = 100; pg4_bits[5] = PG4_HCLK; pg4_durations[6] = 100; pg4_bits[6] = 0; pg4_durations[7] = 100; pg4_bits[7] = 0; pg4_durations[8] = 100; pg4_bits[8] = 0; } } else if (type == READ_START3) { if (operation_type == OP_TYPE_READ) { for (ii = 0; ii < IR_CE_VSEQ_N; ii++) { pg3_durations[ii] = 0; pg3_bits[ii] = PG3_RESETEN; } pg4_durations[0] = 100; pg4_bits[0] = 0; pg4_durations[1] = 100; pg4_bits[1] = 0; pg4_durations[2] = 100; pg4_bits[2] = 0; pg4_durations[3] = 100; pg4_bits[3] = PG4_HCLK; pg4_durations[4] = 100; pg4_bits[4] = (PG4_HCLK) | (PG4_ADC); pg4_durations[5] = 100; pg4_bits[5] = PG4_HCLK; pg4_durations[6] = 100; pg4_bits[6] = 0; pg4_durations[7] = 100; pg4_bits[7] = 0; pg4_durations[8] = 100; pg4_bits[8] = 0; } else if (operation_type == OP_TYPE_RESET) { for (ii = 0; ii < IR_CE_VSEQ_N; ii++) { pg3_durations[ii] = 0; pg3_bits[ii] = PG3_RESETEN; } pg4_durations[0] = 100; pg4_bits[0] = 0; pg4_durations[1] = 100; pg4_bits[1] = 0; pg4_durations[2] = 100; pg4_bits[2] = 0; pg4_durations[3] = 100; pg4_bits[3] = PG4_HCLK; pg4_durations[4] = 100; pg4_bits[4] = (PG4_HCLK) | (PG4_ADC); pg4_durations[5] = 100; pg4_bits[5] = PG4_HCLK; pg4_durations[6] = 100; pg4_bits[6] = 0; pg4_durations[7] = 100; pg4_bits[7] = 0; pg4_durations[8] = 100; pg4_bits[8] = 0; } else if (operation_type == OP_TYPE_RESET_READ) { pg3_durations[0] = 100; pg3_bits[0] = 0; pg3_durations[1] = 100; pg3_bits[1] = PG3_RESETEN; pg3_durations[2] = 100; pg3_bits[2] = PG3_RESETEN; pg3_durations[3] = 100; pg3_bits[3] = PG3_RESETEN; pg3_durations[4] = 100; pg3_bits[4] = PG3_RESETEN; pg3_durations[5] = 100; pg3_bits[5] = PG3_RESETEN; pg3_durations[6] = 100; pg3_bits[6] = PG3_RESETEN; pg3_durations[7] = 100; pg3_bits[7] = PG3_RESETEN; pg3_durations[8] = 100; pg3_bits[8] = 0; pg4_durations[0] = 100; pg4_bits[0] = 0; pg4_durations[1] = 100; pg4_bits[1] = 0; pg4_durations[2] = 100; pg4_bits[2] = 0; pg4_durations[3] = 100; pg4_bits[3] = PG4_HCLK; pg4_durations[4] = 100; pg4_bits[4] = (PG4_HCLK) | (PG4_ADC); pg4_durations[5] = 100; pg4_bits[5] = PG4_HCLK; pg4_durations[6] = 100; pg4_bits[6] = 0; pg4_durations[7] = 100; pg4_bits[7] = 0; pg4_durations[8] = 100; pg4_bits[8] = 0; } else // operation_type == OP_TYPE_BGR { for (ii = 0; ii < IR_CE_VSEQ_N; ii++) { pg3_durations[ii] = 0; pg3_bits[ii] = PG3_RESETEN; } pg4_durations[0] = 100; pg4_bits[0] = 0; pg4_durations[1] = 100; pg4_bits[1] = 0; pg4_durations[2] = 100; pg4_bits[2] = 0; pg4_durations[3] = 100; pg4_bits[3] = PG4_HCLK; pg4_durations[4] = 100; pg4_bits[4] = (PG4_HCLK) | (PG4_ADC); pg4_durations[5] = 100; pg4_bits[5] = PG4_HCLK; pg4_durations[6] = 100; pg4_bits[6] = 0; pg4_durations[7] = 100; pg4_bits[7] = 0; pg4_durations[8] = 100; pg4_bits[8] = 0; } } else if (type == READ_DUMMY) { ir_ce_digout_lo(digout, 0, D_LSYNCB, ce_sample_buf, fp);// duration is 0x0068 return PASS; } else { if (operation_type == OP_TYPE_RESET) { // no convert/reads in reset. for (ii = 0; ii < IR_CE_VSEQ_N; ii++) { pg3_durations[ii] = 0; pg3_bits[ii] = PG3_RESETEN; } pg4_durations[0] = 100; pg4_bits[0] = 0; pg4_durations[1] = 100; pg4_bits[1] = 0; pg4_durations[2] = 100; pg4_bits[2] = 0; pg4_durations[3] = 100; pg4_bits[3] = PG4_HCLK; pg4_durations[4] = 100; pg4_bits[4] = (PG4_HCLK) | (PG4_ADC); pg4_durations[5] = 100; pg4_bits[5] = PG4_HCLK; pg4_durations[6] = 100; pg4_bits[6] = 0; pg4_durations[7] = 100; pg4_bits[7] = 0; pg4_durations[8] = 100; pg4_bits[8] = 0; } else if (operation_type == OP_TYPE_RESET_READ) { // no convert/reads in reset. for (ii = 0; ii < IR_CE_VSEQ_N; ii++) { pg3_durations[ii] = 0; pg3_bits[ii] = PG3_RESETEN; } pg4_durations[0] = 100; pg4_bits[0] = 0; pg4_durations[1] = 100; pg4_bits[1] = 0; pg4_durations[2] = 100; pg4_bits[2] = 0; pg4_durations[3] = 100; pg4_bits[3] = PG4_HCLK; pg4_durations[4] = 100; pg4_bits[4] = (PG4_HCLK) | (PG4_ADC); pg4_durations[5] = 100; pg4_bits[5] = PG4_HCLK; pg4_durations[6] = 100; pg4_bits[6] = 0; pg4_durations[7] = 100; pg4_bits[7] = 0; pg4_durations[8] = 100; pg4_bits[8] = 0; } else if (operation_type == OP_TYPE_BGR) { for (ii = 0; ii < IR_CE_VSEQ_N; ii++) { pg3_durations[ii] = 0; pg3_bits[ii] = PG3_RESETEN; } pg4_durations[0] = 100; pg4_bits[0] = 0; pg4_durations[1] = 100; pg4_bits[1] = 0; pg4_durations[2] = 100; pg4_bits[2] = 0; pg4_durations[3] = 100; pg4_bits[3] = PG4_HCLK; pg4_durations[4] = 100; pg4_bits[4] = (PG4_HCLK) | (PG4_ADC); pg4_durations[5] = 100; pg4_bits[5] = PG4_HCLK; pg4_durations[6] = 100; pg4_bits[6] = 0; pg4_durations[7] = 100; pg4_bits[7] = 0; pg4_durations[8] = 100; pg4_bits[8] = 0; } } h2rg_program_vpg_ir(ce_sample_buf, pixel_count, (unsigned short *)&pg3_durations, (unsigned short *)&pg3_bits, (unsigned short *)&pg4_durations, (unsigned short *)&pg4_bits, fp); return PASS; } static int h2rg_add_read_middle_pixel_f5_ir(struct ir_ce_buf_t *ce_sample_buf, unsigned short *digout, FILE *fp) { return PASS; } static int h2rg_add_read_middle_pixel_f4_ir(struct ir_ce_buf_t *ce_sample_buf, unsigned short *digout, FILE *fp) { return PASS; } static int h2rg_add_read_middle_pixel_s2_ir(struct ir_ce_buf_t *ce_sample_buf, unsigned short *digout, unsigned int operation_type, FILE *fp) { unsigned short pg3_durations[IR_CE_VSEQ_N]; unsigned short pg3_bits[IR_CE_VSEQ_N]; unsigned short pg4_durations[IR_CE_VSEQ_N]; unsigned short pg4_bits[IR_CE_VSEQ_N]; int ii; ir_ce_digout_lo(digout, 0, D_READEN | D_HRESETB | D_FSYNCB | D_CSB | D_MAINRSTB, ce_sample_buf, fp); /* h2_write_digio_value(fb, D_READEN | D_HRESETB | D_FSYNCB | D_CSB | D_MAINRSTB); // duration ix 0x00B8 */ for (ii = 0; ii < IR_CE_VSEQ_N; ii++) { pg3_durations[ii] = 0; pg3_bits[ii] = PG3_RESETEN; } pg4_durations[0] = 100; pg4_bits[0] = PG4_HCLK; pg4_durations[1] = 100; pg4_bits[1] = PG4_HCLK; pg4_durations[2] = 100; pg4_bits[2] = PG4_HCLK; pg4_durations[3] = 100; pg4_bits[3] = PG4_HCLK; pg4_durations[4] = 100; pg4_bits[4] = (PG4_HCLK) | (PG4_ADC); pg4_durations[5] = 100; pg4_bits[5] = PG4_HCLK; pg4_durations[6] = 100; pg4_bits[6] = PG4_HCLK; pg4_durations[7] = 100; pg4_bits[7] = PG4_HCLK; pg4_durations[8] = 100; pg4_bits[8] = PG4_HCLK; if (operation_type == OP_TYPE_RESET) { h2rg_program_vpg_ir(ce_sample_buf, 1, (unsigned short *)&pg3_durations, (unsigned short *)&pg3_bits, (unsigned short *)&pg4_durations, (unsigned short *)&pg4_bits, fp); ir_ce_digout_lo(digout, 0, D_LSYNCB, ce_sample_buf, fp); /* h2_write_digio_value(fb, D_READEN | D_HRESETB | D_FSYNCB | D_CSB | D_MAINRSTB); // duration ix 0x00B8 */ if (operation_type == OP_TYPE_RESET || operation_type == OP_TYPE_RESET_READ) { h2rg_set_ppg_ir(ce_sample_buf, PPG4_VCLK, 1, fp); } else { // need to insert a no-op here of duration 0x0001 } h2rg_set_ppg_ir(ce_sample_buf, 0, 1, fp); } if (operation_type == OP_TYPE_RESET_READ) { h2rg_program_vpg_ir(ce_sample_buf, 1, (unsigned short *)&pg3_durations, (unsigned short *)&pg3_bits, (unsigned short *)&pg4_durations, (unsigned short *)&pg4_bits, fp); ir_ce_digout_lo(digout, 0, D_LSYNCB, ce_sample_buf, fp); /* h2_write_digio_value(fb, D_READEN | D_HRESETB | D_FSYNCB | D_CSB | D_MAINRSTB); // duration ix 0x00B8 */ if (operation_type == OP_TYPE_RESET || operation_type == OP_TYPE_RESET_READ) { h2rg_set_ppg_ir(ce_sample_buf, PPG4_VCLK, 1, fp); } else { // need to insert a no-op here of duration 0x0001 } h2rg_set_ppg_ir(ce_sample_buf, 0, 1, fp); } else if (operation_type == OP_TYPE_BGR) { h2rg_program_vpg_ir(ce_sample_buf, 1, (unsigned short *)&pg3_durations, (unsigned short *)&pg3_bits, (unsigned short *)&pg4_durations, (unsigned short *)&pg4_bits, fp); ir_ce_digout_lo(digout, 0, D_LSYNCB, ce_sample_buf, fp); /* h2_write_digio_value(fb, D_READEN | D_HRESETB | D_FSYNCB | D_CSB | D_MAINRSTB); // duration ix 0x00B8 */ if (operation_type == OP_TYPE_RESET || operation_type == OP_TYPE_RESET_READ) { h2rg_set_ppg_ir(ce_sample_buf, PPG4_VCLK, 1, fp); } else { // need to insert a no-op here of duration 0x0001 } h2rg_set_ppg_ir(ce_sample_buf, 0, 1, fp); } else { h2rg_program_vpg_ir(ce_sample_buf, 1, (unsigned short *)&pg3_durations, (unsigned short *)&pg3_bits, (unsigned short *)&pg4_durations, (unsigned short *)&pg4_bits, fp); ir_ce_digout_lo(digout, 0, D_LSYNCB, ce_sample_buf, fp); /* h2_write_digio_value(fb, D_READEN | D_HRESETB | D_FSYNCB | D_CSB | D_MAINRSTB); // duration ix 0x00B8 */ if (operation_type == OP_TYPE_RESET || operation_type == OP_TYPE_RESET_READ) { h2rg_set_ppg_ir(ce_sample_buf, PPG4_VCLK, 1, fp); } else { // need to insert a no-op here of duration 0x0001 } h2rg_set_ppg_ir(ce_sample_buf, 0, 1, fp); } return PASS; } static int h2rg_add_read_middle_pixel_s3_ir(struct ir_ce_buf_t *ce_sample_buf, unsigned short *digout, FILE *fp) { return PASS; } static int h2rg_add_read_pixel_very_last_ir(struct ir_ce_buf_t *ce_sample_buf, unsigned short *digout, unsigned int operation_type, FILE *fp) { unsigned short pg3_durations[IR_CE_VSEQ_N]; unsigned short pg3_bits[IR_CE_VSEQ_N]; unsigned short pg4_durations[IR_CE_VSEQ_N]; unsigned short pg4_bits[IR_CE_VSEQ_N]; int ii; /* assuming that the digout value coming in is correct as per the following line: h2_write_digio_value(fb, D_READEN | D_HRESETB | D_FSYNCB | D_CSB | D_MAINRSTB); // duration is 1 usec */ if (operation_type == OP_TYPE_RESET) { /* #ifdef FIXME insert a pause here relevant to what the else operation is doing #endif */ } else { for (ii = 0; ii < IR_CE_VSEQ_N; ii++) { pg3_durations[ii] = 0; pg3_bits[ii] = 0; } pg4_durations[0] = 100; pg4_bits[0] = 0; pg4_durations[1] = 100; pg4_bits[1] = 0; pg4_durations[2] = 100; pg4_bits[2] = 0; pg4_durations[3] = 100; pg4_bits[3] = PG4_HCLK; pg4_durations[4] = 100; pg4_bits[4] = (PG4_HCLK) | (PG4_ADC); pg4_durations[5] = 100; pg4_bits[5] = PG4_HCLK; pg4_durations[6] = 100; pg4_bits[6] = 0; pg4_durations[7] = 100; pg4_bits[7] = 0; pg4_durations[8] = 100; pg4_bits[8] = 0; h2rg_program_vpg_ir(ce_sample_buf, 1, (unsigned short *)&pg3_durations, (unsigned short *)&pg3_bits, (unsigned short *)&pg4_durations, (unsigned short *)&pg4_bits, fp); } return PASS; } static int h2rg_terminate_readout_ir( struct ir_ce_buf_t *ce_sample_buf, unsigned short *digout, int termination_type, FILE *fp) { switch (termination_type) { case TERMINATION_NONE: break; case TERMINATION_VCLK: break; case TERMINATION_FIRST: break; case TERMINATION_REFERENCE_ENABLE: h2rg_terminate_reference_enable(ce_sample_buf, digout, fp); break; default: break; } return PASS; } static int h2rg_terminate_reference_enable(struct ir_ce_buf_t *ce_sample_buf, unsigned short *digout, FILE *fp) { output_mode_reg.refrow = 1; /* #ifdef FIXME this was experimental, need to review in final design output_mode_reg.refvolt = h2rg_settings.omg_refvoltagemode; */ h2rg_program_register_ir(ce_sample_buf, digout, (struct h2rg_register *)&output_mode_reg, fp); return PASS; } static int h2rg_set_ppg_ir(struct ir_ce_buf_t *ce_sample_buf, unsigned short value, unsigned short duration, FILE *fp) { unsigned short values[IR_CE_PSEQ_N]; unsigned short durations[IR_CE_PSEQ_N]; int ii = 0; for (ii = 0; ii < IR_CE_PSEQ_N; ii++) { values[ii] = value; durations[ii] = duration; } h2rg_program_ppg_ir(ce_sample_buf, 1, 1, (unsigned short *)&durations, (unsigned short *)&values, fp); return PASS; } static int h2rg_set_ppg_3way_ir(struct ir_ce_buf_t *ce_sample_buf, unsigned short value1, unsigned short duration1, unsigned short value2, unsigned short duration2, unsigned short value3, unsigned short duration3, FILE *fp) { unsigned short values[IR_CE_PSEQ_N]; unsigned short durations[IR_CE_PSEQ_N]; int ii = 0; for (ii = 0; ii < 3; ii++) { values[ii] = value1; values[3 + ii] = value2; values[6 + ii] = value3; durations[ii] = duration1; durations[3 + ii] = duration2; durations[6 + ii] = duration3; } h2rg_program_ppg_ir(ce_sample_buf, 1, 1, (unsigned short *)&durations, (unsigned short *)&values, fp); return PASS; } static int h2rg_set_vpg4_3way_ir(struct ir_ce_buf_t *ce_sample_buf, unsigned short value1, unsigned short duration1, unsigned short value2, unsigned short duration2, unsigned short value3, unsigned short duration3, unsigned short value_pg3, FILE *fp) { unsigned short values_pg4[IR_CE_PSEQ_N]; unsigned short durations_pg4[IR_CE_PSEQ_N]; unsigned short values_pg3[IR_CE_PSEQ_N]; unsigned short durations_pg3[IR_CE_PSEQ_N]; int ii = 0; for (ii = 0; ii < 3; ii++) { values_pg4[ii] = value1; values_pg4[3 + ii] = value2; values_pg4[6 + ii] = value3; durations_pg4[ii] = duration1; durations_pg4[3 + ii] = duration2; durations_pg4[6 + ii] = duration3; } for (ii = 0; ii < 9; ii++) { values_pg3[ii] = value_pg3; durations_pg3[ii] = 1; } h2rg_program_vpg_ir(ce_sample_buf,1,(unsigned short *)&durations_pg3, (unsigned short *)&values_pg3, (unsigned short *)&durations_pg4, (unsigned short *)&values_pg4, fp); return PASS; } #ifdef LATER static int h2rg_set_vpg3_3way_ir(struct ir_ce_buf_t *ce_sample_buf, unsigned short value1, unsigned short duration1, unsigned short value2, unsigned short duration2, unsigned short value3, unsigned short duration3, unsigned short value_pg4, FILE *fp) { unsigned short values_pg4[IR_CE_PSEQ_N]; unsigned short durations_pg4[IR_CE_PSEQ_N]; unsigned short values_pg3[IR_CE_PSEQ_N]; unsigned short durations_pg3[IR_CE_PSEQ_N]; int ii = 0; for (ii = 0; ii < 3; ii++) { values_pg3[ii] = value1; values_pg3[3 + ii] = value2; values_pg3[6 + ii] = value3; durations_pg3[ii] = duration1; durations_pg3[3 + ii] = duration2; durations_pg3[6 + ii] = duration3; } for (ii = 0; ii < 9; ii++) { values_pg4[ii] = value_pg4; durations_pg4[ii] = 1; } h2rg_program_vpg_ir(ce_sample_buf,1,(unsigned short *)&durations_pg3, (unsigned short *)&values_pg3, (unsigned short *)&durations_pg4, (unsigned short *)&values_pg4, fp); return PASS; } #endif static int h2rg_program_ppg_ir( struct ir_ce_buf_t *ce_sample_buf, int reps, short scale, unsigned short *durations, unsigned short *bits, FILE *fp) { struct ir_ce_pseq_t pseq; int ii = 0; pseq.scale = 1; for (ii = 0; ii < IR_CE_PSEQ_N; ii++) { pseq.dur[ii] = durations[ii]; pseq.bits[ii] = bits[ii]; } ir_printf(fp, "# Init FastMux: \n"); ir_ce_parseq_param(&pseq, ce_sample_buf, fp); ir_ce_parseq_exe(reps, &pseq, ce_sample_buf, fp); return PASS; } static int h2rg_program_vpg_ir( struct ir_ce_buf_t *ce_sample_buf, int reps, unsigned short *pg3_durations, unsigned short *pg3_bits, unsigned short *pg4_durations, unsigned short *pg4_bits, FILE *fp) { struct ir_ce_vseq_t vseq; int ii = 0; vseq.reps = 1; for (ii = 0; ii < IR_CE_VSEQ_N; ii++) { vseq.pg3_dur[ii] = pg3_durations[ii]; vseq.pg3_bits[ii] = pg3_bits[ii]; vseq.pg4_dur[ii] = pg4_durations[ii]; vseq.pg4_bits[ii] = pg4_bits[ii]; } ir_printf(fp, "# Init FastMux: \n"); ir_ce_vidseq_param(&vseq, ce_sample_buf, fp); ir_ce_vidseq_exe(reps, &vseq, ce_sample_buf, fp); return PASS; }