IR_ch  ADName   Dev Ch Color      DAC

 0     AD00_0     0   7  R         2  0
 1     AD01_0     0   6  R         2  1
 2     AD02_0     0   5  R         2  2
 3     AD03_0     0   4  R         2  3
 4     AD04_0     0   3  R         2  4
 5     AD05_0     0   2  R         2  5
 6     AD06_0     0   1  R         2  6
 7     AD07_0     0   0  R         2  7

 8     AD08_0     1   7  R         2  8
19     AD09_0     1   6  R         2  9
10     AD10_0     1   5  R         2 10
11     AD11_0     1   4  R         2 11
12     AD12_0     1   3  R         2 12
13     AD13_0     1   2  R         2 13
14     AD14_0     1   1  R         2 14
15     AD15_0     1   0  R         2 15

16     AD00_1     0   7  G             
17     AD01_1     0   6  G             
18     AD02_1     0   5  G             
19     AD03_1     0   4  G             
20     AD04_1     0   3  G             
21     AD05_1     0   2  G             
22     AD06_1     0   1  G             
23     AD07_1     0   0  G             

24     AD00_1     1   7  G             
25     AD01_1     1   6  G             
26     AD02_1     1   5  G             
27     AD03_1     1   4  G             
28     AD04_1     1   3  G             
29     AD05_1     1   2  G             
30     AD06_1     1   1  G             
31     AD07_1     1   0  G             


DAC chip - 3 dac, 32 channels each


dac    0   0             // bias for PG4-1 off
dac    0   1             //            ""   on
dac    0   2
dac    0   3
dac    0   4
dac    0   5
dac    0   6             // bias for PG3-0 off
dac    0   7             //            ""  on
dac    0   8
dac    0   9
dac    0  10             // bias for PGP4-2 off
dac    0  11             //            ""   on
dac    0  12             // bias for PPG4-1 off
dac    0  13             //            ""   on
dac    0  14             // bias for PPG4-0 off
dac    0  15             //           ""   on
dac    0  16
dac    0  17
dac    0  18
dac    0  19
dac    0  20
dac    0  21
dac    0  22
dac    0  23
dac    0  24
dac    0  25
dac    0  26
dac    0  27
dac    0  28
dac    0  29
dac    0  30                 //
dac    0  31                 //

dac    1   0
dac    1   1
dac    1   2
dac    1   3
dac    1   4
dac    1   5
dac    1   6
dac    1   7
dac    1   8
dac    1   9
dac    1  10
dac    1  11
dac    1  12
dac    1  13
dac    1  14
dac    1  15
dac    1  16
dac    1  17
dac    1  18
dac    1  19
dac    1  20
dac    1  21
dac    1  22
dac    1  23
dac    1  24
dac    1  25
dac    1  26
dac    1  27
dac    1  28
dac    1  29
dac    1  30                 //
dac    1  31                 // 

dac    2   0                 // IR Channel  0 offset for ADC
dac    2   1                 // IR Channel  1 offset for ADC
dac    2   2                 // IR Channel  2 offset for ADC
dac    2   3                 // IR Channel  3 offset for ADC
dac    2   4                 // IR Channel  4 offset for ADC
dac    2   5                 // IR Channel  5 offset for ADC
dac    2   6                 // IR Channel  6 offset for ADC
dac    2   7                 // IR Channel  7 offset for ADC
dac    2   8                 // IR Channel  8 offset for ADC
dac    2   9                 // IR Channel  9 offset for ADC
dac    2  10                 // IR Channel 10 offset for ADC
dac    2  11                 // IR Channel 11 offset for ADC
dac    2  12                 // IR Channel 12 offset for ADC
dac    2  13                 // IR Channel 13 offset for ADC
dac    2  14                 // IR Channel 14 offset for ADC
dac    2  15                 // IR Channel 15 offset for ADC
dac    2  16               
dac    2  17                 
dac    2  18
dac    2  19
dac    2  20
dac    2  21
dac    2  22
dac    2  23
dac    2  24
dac    2  25
dac    2  26
dac    2  27
dac    2  28
dac    2  29
dac    2  30
dac    2  31