 0000           ;------------------------------------------------------------------------------
 0000           ;  FILENAME:   Timer32_1.asm
 0000           ;   VERSION:   Rev B, 2002 Mar 30
 0000           ;------------------------------------------------------------------------------
 0000           ;  DESCRIPTION:
 0000           ;     Timer32_1 Timer32 User Module API.
 0000           ;
 0000           ;------------------------------------------------------------------------------
 0000           ;       Copyright (c) Cypress MicroSystems 2000-2002. All Rights Reserved.
 0000           ;------------------------------------------------------------------------------
 0000           
 0000           ;-----------------------------------------------
 0000           ; include instance specific register definitions
 0000           ;-----------------------------------------------
 0010           FlagXIOMask:  equ 10h
 0008           FlagSuper:    equ 08h
 0004           FlagCarry:    equ 04h
 0002           FlagZero:     equ 02h
 0001           FlagGlobalIE: equ 01h
 0000           
 0000           
 0000           ;;===================================
 0000           ;;      Register Space, Bank 0
 0000           ;;===================================
 0000           
 0000           ;------------------------------------------------
 0000           ;  Port Registers
 0000           ;  Note: Also see this address range in Bank 1.
 0000           ;------------------------------------------------
 0000           ; Port 0
 0000           PRT0DR:       equ 00h          ; Port 0 Data Register              (RW)
 0001           PRT0IE:       equ 01h          ; Port 0 Interrupt Enable Register  (WO)
 0002           PRT0GS:       equ 02h          ; Port 0 Global Select Register     (WO)
 0000           ; (Reserved)  equ 03h
 0000           ; Port 1
 0004           PRT1DR:       equ 04h          ; Port 1 Data Register              (RW)
 0005           PRT1IE:       equ 05h          ; Port 1 Interrupt Enable Register  (WO)
 0006           PRT1GS:       equ 06h          ; Port 1 Global Select Register     (WO)
 0000           ; (Reserved)  equ 07h
 0000           ; Port 2
 0008           PRT2DR:       equ 08h          ; Port 2 Data Register              (RW)
 0009           PRT2IE:       equ 09h          ; Port 2 Interrupt Enable Register  (WO)
 000A           PRT2GS:       equ 0Ah          ; Port 2 Global Select Register     (WO)
 0000           ; (Reserved)  equ 0Bh
 0000           ; Port 3
 000C           PRT3DR:       equ 0Ch          ; Port 3 Data Register              (RW)
 000D           PRT3IE:       equ 0Dh          ; Port 3 Interrupt Enable Register  (WO)
 000E           PRT3GS:       equ 0Eh          ; Port 3 Global Select Register     (WO)
 0000           ; (Reserved)  equ 0Fh
 0000           ; Port 4
 0010           PRT4DR:       equ 10h          ; Port 4 Data Register              (RW)
 0011           PRT4IE:       equ 11h          ; Port 4 Interrupt Enable Register  (WO)
 0012           PRT4GS:       equ 12h          ; Port 4 Global Select Register     (WO)
 0000           ; (Reserved)  equ 13h
 0000           ; Port 5
 0014           PRT5DR:       equ 14h          ; Port 5 Data Register              (RW)
 0015           PRT5IE:       equ 15h          ; Port 5 Interrupt Enable Register  (WO)
 0016           PRT5GS:       equ 16h          ; Port 5 Global Select Register     (WO)
 0000           ; (Reserved)  equ 17h
 0000           
 0000           ;------------------------------------------------
 0000           ;  Digital PSoC(tm) block Registers
 0000           ;  Note: Also see this address range in Bank 1.
 0000           ;------------------------------------------------
 0000           ; Digital PSoC block 0, Basic Type A
 0020           DBA00DR0:     equ 20h          ; data register 0                   (RO)
 0021           DBA00DR1:     equ 21h          ; data register 1                   (WO)
 0022           DBA00DR2:     equ 22h          ; data register 2                   (RW)
 0023           DBA00CR0:     equ 23h          ; control & status register 0       (RW)
 0000           
 0000           ; Digital PSoC block 1, Basic Type A
 0024           DBA01DR0:     equ 24h          ; data register 0                   (RO)
 0025           DBA01DR1:     equ 25h          ; data register 1                   (WO)
 0026           DBA01DR2:     equ 26h          ; data register 2                   (RW)
 0027           DBA01CR0:     equ 27h          ; control & status register 0       (RW)
 0000           
 0000           ; Digital PSoC block 2, Basic Type A
 0028           DBA02DR0:     equ 28h          ; data register 0                   (RO)
 0029           DBA02DR1:     equ 29h          ; data register 1                   (WO)
 002A           DBA02DR2:     equ 2Ah          ; data register 2                   (RW)
 002B           DBA02CR0:     equ 2Bh          ; control & status register 0       (RW)
 0000           
 0000           ; Digital PSoC block 3, Basic Type A
 002C           DBA03DR0:     equ 2Ch          ; data register 0                   (RO)
 002D           DBA03DR1:     equ 2Dh          ; data register 1                   (WO)
 002E           DBA03DR2:     equ 2Eh          ; data register 2                   (RW)
 002F           DBA03CR0:     equ 2Fh          ; control & status register 0       (RW)
 0000           
 0000           ; Digital PSoC block 4, Communications Type A
 0030           DCA04DR0:     equ 30h          ; data register 0                   (RO)
 0031           DCA04DR1:     equ 31h          ; data register 1                   (WO)
 0032           DCA04DR2:     equ 32h          ; data register 2                   (RW)
 0033           DCA04CR0:     equ 33h          ; control & status register 0       (RW)
 0000           
 0000           ; Digital PSoC block 5, Communications Type A
 0034           DCA05DR0:     equ 34h          ; data register 0                   (RO)
 0035           DCA05DR1:     equ 35h          ; data register 1                   (WO)
 0036           DCA05DR2:     equ 36h          ; data register 2                   (RW)
 0037           DCA05CR0:     equ 37h          ; control & status register 0       (RW)
 0000           
 0000           ; Digital PSoC block 6, Communications Type A
 0038           DCA06DR0:     equ 38h          ; data register 0                   (RO)
 0039           DCA06DR1:     equ 39h          ; data register 1                   (WO)
 003A           DCA06DR2:     equ 3Ah          ; data register 2                   (RW)
 003B           DCA06CR0:     equ 3Bh          ; control & status register 0       (RW)
 0000           
 0000           ; Digital PSoC block 7, Communications Type A
 003C           DCA07DR0:     equ 3Ch          ; data register 0                   (RO)
 003D           DCA07DR1:     equ 3Dh          ; data register 1                   (WO)
 003E           DCA07DR2:     equ 3Eh          ; data register 2                   (RW)
 003F           DCA07CR0:     equ 3Fh          ; control & status register 0       (RW)
 0000           
 0000           
 0000           ;-------------------------------------
 0000           ;  Analog Resource Control Registers
 0000           ;-------------------------------------
 0060           AMX_IN:       equ 60h          ; analog input multiplexor control  (RW)
 0000                                          ; AMX_IN Bit field masks:
 00C0           AMX_IN_ACI3:          equ C0h          ; column 3 input mux
 0030           AMX_IN_ACI2:          equ 30h          ; column 2 input mux
 000C           AMX_IN_ACI1:          equ 0Ch          ; column 1 input mux
 0003           AMX_IN_ACI0:          equ 03h          ; column 0 input mux
 0000           
 0000           ; (Reserved)  equ 61h          ; reserved
 0000           ; (Reserved)  equ 62h          ; reserved
 0000           
 0063           ARF_CR:       equ 63h          ; analog reference control          (RW)
 0000                                          ; ARF_CR Bit field masks:
 0080           ARF_CR_BGT:           equ 80h          ; Bandgap Test
 0040           ARF_CR_HBE:           equ 40h          ; Bias level control
 0038           ARF_CR_REF:           equ 38h          ; Analog array ref control
 0004           ARF_CR_APWR:          equ 04h          ; Analog Power
 0003           ARF_CR_SCPWR:         equ 03h          ; Switched Cap block power
 0000           
 0064           CMP_CR:       equ 64h          ; comparator control                (*)
 0000                                          ; CMP_CR Bit field masks:
 0080           CMP_CR_COMP3:         equ 80h          ; Column 3 comparator state     (R)
 0040           CMP_CR_COMP2:         equ 40h          ; Column 2 comparator state     (R)
 0020           CMP_CR_COMP1:         equ 20h          ; Column 1 comparator state     (R)
 0010           CMP_CR_COMP0:         equ 10h          ; Column 0 comparator state     (R)
 0008           CMP_CR_AINT3:         equ 08h          ; Column 3 interrupt source     (RW)
 0004           CMP_CR_AINT2:         equ 04h          ; Column 2 interrupt source     (RW)
 0002           CMP_CR_AINT1:         equ 02h          ; Column 1 interrupt source     (RW)
 0001           CMP_CR_AINT0:         equ 01h          ; Column 0 interrupt source     (RW)
 0000           
 0065           ASY_CR:       equ 65h          ; analog synchronizaton control     (*)
 0000                                          ; ASY_CR Bit field masks:
 0007           ASY_CR_SARCOUNT:      equ 07h          ; SAR support: resolution count (W0)
 0008           ASY_CR_SARSIGN:       equ 08h          ; SAR support: sign             (RW)
 0006           ASY_CR_SARCOL:        equ 06h          ; SAR support: column spec	   (RW)
 0001           ASY_CR_SYNCEN:        equ 01h          ; Stall bit                     (RW)
 0000           
 0000           
 0000           ;---------------------------------------------------
 0000           ;  Analog PSoC block Registers
 0000           ;
 0000           ;  Note: the following registers are mapped into
 0000           ;  both register bank 0 AND register bank 1.
 0000           ;---------------------------------------------------
 0000           
 0000           ; Continuous Time PSoC block Type A Row 0 Col 0
 0000           ; (Reserved)  equ 70h
 0071           ACA00CR0:     equ 71h          ; Control register 0                (RW)
 0072           ACA00CR1:     equ 72h          ; Control register 1                (RW)
 0073           ACA00CR2:     equ 73h          ; Control register 2                (RW)
 0000           
 0000           ; Continuous Time PSoC block Type A Row 0 Col 1
 0000           ; (Reserved)  equ 74h
 0075           ACA01CR0:     equ 75h          ; Control register 0                (RW)
 0076           ACA01CR1:     equ 76h          ; Control register 1                (RW)
 0077           ACA01CR2:     equ 77h          ; Control register 2                (RW)
 0000           
 0000           ; Continuous Time PSoC block Type A Row 0 Col 2
 0000           ; (Reserved)  equ 78h
 0079           ACA02CR0:     equ 79h          ; Control register 0                (RW)
 007A           ACA02CR1:     equ 7Ah          ; Control register 1                (RW)
 007B           ACA02CR2:     equ 7Bh          ; Control register 2                (RW)
 0000           
 0000           ; Continuous Time PSoC block Type A Row 0 Col 3
 0000           ; (Reserved)  equ 7Ch
 007D           ACA03CR0:     equ 7Dh          ; Control register 0                (RW)
 007E           ACA03CR1:     equ 7Eh          ; Control register 1                (RW)
 007F           ACA03CR2:     equ 7Fh          ; Control register 2                (RW)
 0000           
 0000           ; Switched Cap PSoC blockType A Row 1 Col 0
 0080           ASA10CR0:     equ 80h          ; Control register 0                (RW)
 0081           ASA10CR1:     equ 81h          ; Control register 1                (RW)
 0082           ASA10CR2:     equ 82h          ; Control register 2                (RW)
 0083           ASA10CR3:     equ 83h          ; Control register 3                (RW)
 0000           
 0000           ; Switched Cap PSoC blockType B Row 1 Col 1
 0084           ASB11CR0:     equ 84h          ; Control register 0                (RW)
 0085           ASB11CR1:     equ 85h          ; Control register 1                (RW)
 0086           ASB11CR2:     equ 86h          ; Control register 2                (RW)
 0087           ASB11CR3:     equ 87h          ; Control register 3                (RW)
 0000           
 0000           ; Switched Cap PSoC blockType A Row 1 Col 2
 0088           ASA12CR0:     equ 88h          ; Control register 0                (RW)
 0089           ASA12CR1:     equ 89h          ; Control register 1                (RW)
 008A           ASA12CR2:     equ 8Ah          ; Control register 2                (RW)
 008B           ASA12CR3:     equ 8Bh          ; Control register 3                (RW)
 0000           
 0000           ; Switched Cap PSoC blockType B Row 1 Col 3
 008C           ASB13CR0:     equ 8Ch          ; Control register 0                (RW)
 008D           ASB13CR1:     equ 8Dh          ; Control register 1                (RW)
 008E           ASB13CR2:     equ 8Eh          ; Control register 2                (RW)
 008F           ASB13CR3:     equ 8Fh          ; Control register 3                (RW)
 0000           
 0000           ; Switched Cap PSoC blockType B Row 2 Col 0
 0090           ASB20CR0:     equ 90h          ; Control register 0                (RW)
 0091           ASB20CR1:     equ 91h          ; Control register 1                (RW)
 0092           ASB20CR2:     equ 92h          ; Control register 2                (RW)
 0093           ASB20CR3:     equ 93h          ; Control register 3                (RW)
 0000           
 0000           ; Switched Cap PSoC blockType A Row 2 Col 1
 0094           ASA21CR0:     equ 94h          ; Control register 0                (RW)
 0095           ASA21CR1:     equ 95h          ; Control register 1                (RW)
 0096           ASA21CR2:     equ 96h          ; Control register 2                (RW)
 0097           ASA21CR3:     equ 97h          ; Control register 3                (RW)
 0000           
 0000           ; Switched Cap PSoC blockType B Row 2 Col 2
 0098           ASB22CR0:     equ 98h          ; Control register 0                (RW)
 0099           ASB22CR1:     equ 99h          ; Control register 1                (RW)
 009A           ASB22CR2:     equ 9Ah          ; Control register 2                (RW)
 009B           ASB22CR3:     equ 9Bh          ; Control register 3                (RW)
 0000           
 0000           ; Switched Cap PSoC blockType A Row 2 Col 3
 009C           ASA23CR0:     equ 9Ch          ; Control register 0                (RW)
 009D           ASA23CR1:     equ 9Dh          ; Control register 1                (RW)
 009E           ASA23CR2:     equ 9Eh          ; Control register 2                (RW)
 009F           ASA23CR3:     equ 9Fh          ; Control register 3                (RW)
 0000           
 0000           ;------------------------------------------------
 0000           ;  System and Global Resource Registers
 0000           ;  Note: Also see this address range in Bank 1.
 0000           ;------------------------------------------------
 00E0           INT_MSK0:                  equ E0h   ; General Interrupt Mask Register   (RW)
 0040           INT_MSK0_Sleep:            equ 40h  ; MASK: enable/disable sleep interrupt
 0020           INT_MSK0_GPIO:             equ 20h  ; MASK: enable/disable GPIO  interrupt
 0010           INT_MSK0_AColumn3:         equ 10h  ; MASK: enable/disable Analog col 3 interrupt
 0008           INT_MSK0_AColumn2:         equ 08h  ; MASK: enable/disable Analog col 2 interrupt
 0004           INT_MSK0_AColumn1:         equ 04h  ; MASK: enable/disable Analog col 1 interrupt
 0002           INT_MSK0_AColumn0:         equ 02h  ; MASK: enable/disable Analog col 0 interrupt
 0001           INT_MSK0_VoltageMonitor:   equ 01h  ; MASK: enable/disable Volts interrupt
 0000           
 00E1           INT_MSK1:     equ E1h          ; Digital PSoC block Mask Register  (RW)
 00E2           INT_VC:       equ E2h          ; Interrupt vector register         (RW)
 00E3           RES_WDT:      equ E3h          ; Watch Dog Timer                   (RW)
 0000           
 0000           ; DECIMATOR Registers
 00E4           DEC_DH:       equ E4h          ; Data Register (high byte)         (RW)
 00E5           DEC_DL:       equ E5h          ; Data Register ( low byte)         (RO)
 00E6           DEC_CR:       equ E6h          ; Data Control Register             (RW)
 0000           
 0000           ; Multiplier and MAC (Multiply/Accumulate) Unit
 00E8           MUL_X:        equ E8h          ; Multiplier X Register (write)            (WO)
 00E9           MUL_Y:        equ E9h          ; Multiplier Y Register (write)            (WO)
 00EA           MUL_DH:       equ EAh          ; Multiplier Result Data (high byte read)  (RO)
 00EB           MUL_DL:       equ EBh          ; Multiplier Result Data ( low byte read)  (RO)
 00EC           MAC_X:        equ ECh          ; MAC X register (write) [also see ACC_DR1](WO)
 00ED           MAC_Y:        equ EDh          ; MAC Y register (write) [also see ACC_DR0](WO)
 00EE           MAC_CL0:      equ EEh          ; MAC Clear Accum (write)[also see ACC_DR3](WO)
 00EF           MAC_CL1:      equ EFh          ; MAC Clear Accum (write)[also see ACC_DR2](WO)
 00EC           ACC_DR1:      equ ECh          ; MAC Accumulator (Read, byte 0)           (RO)
 00ED           ACC_DR0:      equ EDh          ; MAC Accumulator (Read, byte 0)           (RO)
 00EE           ACC_DR3:      equ EEh          ; MAC Accumulator (Read, byte 0)           (RO)
 00EF           ACC_DR2:      equ EFh          ; MAC Accumulator (Read, byte 0)           (RO)
 0000           
 0000           ; Test Mode mapping of the CPU Flag (F) Register
 00F7           CPU_FLAG:     equ F7h          ; NOTE: Only mapped when in Test Mode !!!
 0000           
 0000           
 0000           ;------------------------------------------------
 0000           ;  System Status and Control Register
 0000           ;
 0000           ;  Note: the following register is mapped into
 0000           ;  both register bank 0 AND register bank 1.
 0000           ;------------------------------------------------
 00FF           CPU_SCR:                equ FFh   ;                                     (*)
 0080           CPUSCR_GIEMask:         equ 80h   ; MASK: flag reg Global Int Enable shadow
 0020           CPUSCR_WDRSMask:        equ 20h   ; MASK: Watch Dog Timer Reset
 0010           CPUSCR_PORSMask:        equ 10h   ; MASK: power-on reset bit PORS
 0008           CPUSCR_SleepMask:       equ 08h   ; MASK: Enable Sleep
 0001           CPUSCR_StopMask:        equ 01h   ; MASK: Halt CPU bit
 0000           
 0000           
 0000           ;;===================================
 0000           ;;      Register Space, Bank 1
 0000           ;;===================================
 0000           
 0000           ;------------------------------------------------
 0000           ;  Port Registers
 0000           ;  Note: Also see this address range in Bank 0.
 0000           ;------------------------------------------------
 0000           ; Port 0
 0000           PRT0DM0:      equ 00h          ; Port 0 Drive Mode 0               (WO)
 0001           PRT0DM1:      equ 01h          ; Port 0 Drive Mode 1               (WO)
 0002           PRT0IC0:      equ 02h          ; Port 0 Interrupt Control 0        (WO)
 0003           PRT0IC1:      equ 03h          ; Port 0 Interrupt Control 1        (WO)
 0000           
 0000           ; Port 1
 0004           PRT1DM0:      equ 04h          ; Port 1 Drive Mode 0               (WO)
 0005           PRT1DM1:      equ 05h          ; Port 1 Drive Mode 1               (WO)
 0006           PRT1IC0:      equ 06h          ; Port 1 Interrupt Control 0        (WO)
 0007           PRT1IC1:      equ 07h          ; Port 1 Interrupt Control 1        (WO)
 0000           
 0000           ; Port 2
 0008           PRT2DM0:      equ 08h          ; Port 2 Drive Mode 0               (WO)
 0009           PRT2DM1:      equ 09h          ; Port 2 Drive Mode 1               (WO)
 000A           PRT2IC0:      equ 0Ah          ; Port 2 Interrupt Control 0        (WO)
 000B           PRT2IC1:      equ 0Bh          ; Port 2 Interrupt Control 1        (WO)
 0000           
 0000           ; Port 3
 000C           PRT3DM0:      equ 0Ch          ; Port 3 Drive Mode 0               (WO)
 000D           PRT3DM1:      equ 0Dh          ; Port 3 Drive Mode 1               (WO)
 000E           PRT3IC0:      equ 0Eh          ; Port 3 Interrupt Control 0        (WO)
 000F           PRT3IC1:      equ 0Fh          ; Port 3 Interrupt Control 1        (WO)
 0000           
 0000           ; Port 4
 0010           PRT4DM0:      equ 10h          ; Port 4 Drive Mode 0               (WO)
 0011           PRT4DM1:      equ 11h          ; Port 4 Drive Mode 1               (WO)
 0012           PRT4IC0:      equ 12h          ; Port 4 Interrupt Control 0        (WO)
 0013           PRT4IC1:      equ 13h          ; Port 4 Interrupt Control 1        (WO)
 0000           
 0000           ; Port 5
 0014           PRT5DM0:      equ 14h          ; Port 5 Drive Mode 0               (WO)
 0015           PRT5DM1:      equ 15h          ; Port 5 Drive Mode 1               (WO)
 0016           PRT5IC0:      equ 16h          ; Port 5 Interrupt Control 0        (WO)
 0017           PRT5IC1:      equ 17h          ; Port 5 Interrupt Control 1        (WO)
 0000           
 0000           
 0000           ;------------------------------------------------
 0000           ;  Digital PSoC(tm) block Registers
 0000           ;  Note: Also see this address range in Bank 0.
 0000           ;------------------------------------------------
 0000           
 0000           ; Digital PSoC block 0, Basic Type A
 0020           DBA00FN:      equ 20h          ; Function Register                 (RW)
 0021           DBA00IN:      equ 21h          ;    Input Register                 (RW)
 0022           DBA00OU:      equ 22h          ;   Output Register                 (RW)
 0000           ; (Reserved)  equ 23h
 0000           
 0000           ; Digital PSoC block 1, Basic Type A
 0024           DBA01FN:      equ 24h          ; Function Register                 (RW)
 0025           DBA01IN:      equ 25h          ;    Input Register                 (RW)
 0026           DBA01OU:      equ 26h          ;   Output Register                 (RW)
 0000           ; (Reserved)  equ 27h
 0000           
 0000           ; Digital PSoC block 2, Basic Type A
 0028           DBA02FN:      equ 28h          ; Function Register                 (RW)
 0029           DBA02IN:      equ 29h          ;    Input Register                 (RW)
 002A           DBA02OU:      equ 2Ah          ;   Output Register                 (RW)
 0000           ; (Reserved)  equ 2Bh
 0000           
 0000           ; Digital PSoC block 3, Basic Type A
 002C           DBA03FN:      equ 2Ch          ; Function Register                 (RW)
 002D           DBA03IN:      equ 2Dh          ;    Input Register                 (RW)
 002E           DBA03OU:      equ 2Eh          ;   Output Register                 (RW)
 0000           ; (Reserved)  equ 2Fh
 0000           
 0000           ; Digital PSoC block 4, Communications Type A
 0030           DCA04FN:      equ 30h          ; Function Register                 (RW)
 0031           DCA04IN:      equ 31h          ;    Input Register                 (RW)
 0032           DCA04OU:      equ 32h          ;   Output Register                 (RW)
 0000           ; (Reserved)  equ 33h
 0000           
 0000           ; Digital PSoC block 5, Communications Type A
 0034           DCA05FN:      equ 34h          ; Function Register                 (RW)
 0035           DCA05IN:      equ 35h          ;    Input Register                 (RW)
 0036           DCA05OU:      equ 36h          ;   Output Register                 (RW)
 0000           ; (Reserved)  equ 37h
 0000           
 0000           ; Digital PSoC block 6, Communications Type A
 0038           DCA06FN:      equ 38h          ; Function Register                 (RW)
 0039           DCA06IN:      equ 39h          ;    Input Register                 (RW)
 003A           DCA06OU:      equ 3Ah          ;   Output Register                 (RW)
 0000           ; (Reserved)  equ 3Bh
 0000           
 0000           ; Digital PSoC block 7, Communications Type A
 003C           DCA07FN:      equ 3Ch          ; Function Register                 (RW)
 003D           DCA07IN:      equ 3Dh          ;    Input Register                 (RW)
 003E           DCA07OU:      equ 3Eh          ;   Output Register                 (RW)
 0000           ; (Reserved)  equ 3Fh
 0000           
 0000           
 0000           ;------------------------------------------------
 0000           ;  System and Global Resource Registers
 0000           ;  Note: Also see this address range in Bank 0.
 0000           ;------------------------------------------------
 0000           
 0060           CLK_CR0:      equ 60h          ; Analog Column Clock Select Register     (RW)
 00C0           CLK_CR0_AColumn3:     equ C0h  ; MASK: Specify clock for analog cloumn
 0030           CLK_CR0_AColumn2:     equ 30h  ; MASK: Specify clock for analog cloumn
 000C           CLK_CR0_AColumn1:     equ 0Ch  ; MASK: Specify clock for analog cloumn
 0003           CLK_CR0_AColumn0:     equ 03h  ; MASK: Specify clock for analog cloumn
 0000           
 0061           CLK_CR1:      equ 61h          ; Analog Clock Source Select Register     (RW)
 0040           CLK_CR1_SHDIS:        equ 40h  ; MASK: Sample and Hold Disable (all Columns)
 0038           CLK_CR1_ACLK1:        equ 38h  ; MASK: Digital PSoC block for analog source
 0007           CLK_CR1_ACLK2:        equ 07h  ; MASK: Digital PSoC block for analog source
 0000           
 0062           ABF_CR:       equ 62h          ; Analog Output Buffer Control Register   (RW)
 00C0           ABF_CR_ACI3:          equ C0h  ; MASK: Level 1 input mux for analog column 3
 0030           ABF_CR_ACI2:          equ 30h  ; MASK: Level 1 input mux for analog column 2
 000C           ABF_CR_ACI1:          equ 0Ch  ; MASK: Level 1 input mux for analog column 1
 0003           ABF_CR_ACI0:          equ 03h  ; MASK: Level 1 input mux for analog column 0
 0000           
 0063           AMD_CR:       equ 63h          ; Analog Modulator Control Register       (RW)
 000C           AMD_CR_AMOD2:         equ 0Ch  ; MASK: Modulation source for analog column 2
 0003           AMD_CR_AMOD0:         equ 03h  ; MASK: Modulation source for analog column 1
 0000           
 0000           
 00E0           OSC_CR0:      equ E0h          ; System Oscillator Control Register      (RW)
 0080           OSC_CR0_32K_Select:   equ 80h  ; MASK: Enable/Disable External XTAL Oscillator
 0040           OSC_CR0_PLL_Mode:     equ 40h  ; MASK: Enable/Disable PLL
 0018           OSC_CR0_Sleep:        equ 18h  ; MASK: Set Sleep timer freq/period
 0000           OSC_CR0_Sleep_512Hz:  equ 00h  ;     Set sleep bits for 1.95ms period
 0008           OSC_CR0_Sleep_64Hz:   equ 08h  ;     Set sleep bits for 15.6ms period
 0010           OSC_CR0_Sleep_8Hz:    equ 10h  ;     Set sleep bits for 125ms period
 0018           OSC_CR0_Sleep_1Hz:    equ 18h  ;     Set sleep bits for 1 sec period
 0007           OSC_CR0_CPU:          equ 07h  ; MASK: Set CPU Frequency
 0000           OSC_CR0_CPU_3MHz:     equ 00h  ;     set CPU Freq bits for 3MHz Operation
 0001           OSC_CR0_CPU_6MHz:     equ 01h  ;     set CPU Freq bits for 6MHz Operation
 0002           OSC_CR0_CPU_12MHz:    equ 02h  ;     set CPU Freq bits for 12MHz Operation
 0003           OSC_CR0_CPU_24MHz:    equ 03h  ;     set CPU Freq bits for 24MHz Operation
 0004           OSC_CR0_CPU_1d5MHz:   equ 04h  ;     set CPU Freq bits for 1.5MHz Operation
 0005           OSC_CR0_CPU_750kHz:   equ 05h  ;     set CPU Freq bits for 750kHz Operation
 0006           OSC_CR0_CPU_187d5kHz: equ 06h  ;     set CPU Freq bits for 187.5kHz Operation
 0007           OSC_CR0_CPU_93d7kHz:  equ 07h  ;     set CPU Freq bits for 93.7kHz Operation
 0000           
 00E1           OSC_CR1:      equ E1h          ; System V1/V2 Divider Control Register   (RW)
 00F0           OSC_CR1_V1:           equ F0h  ; MASK System V1 24MHz divider
 000F           OSC_CR1_V2:           equ 0Fh  ; MASK System V2 24MHz divider
 0000           
 0000           ;Reserved     equ E2h
 00E3           VLT_CR:       equ E3h          ; Voltage Monitor Control Register        (RW)
 0000           
 00E8           IMO_TR:       equ E8h          ; Internal Main Oscillator Trim Register  (WO)
 00E9           ILO_TR:       equ E9h          ; Internal Low-speed Oscillator Trim      (WO)
 00EA           BDG_TR:       equ EAh          ; Band Gap Trim Register                  (WO)
 00EB           ECO_TR:       equ EBh          ; External Oscillator Trim Register       (WO)
 0000           
 0000           
 0000           
 0000           ;;===================================
 0000           ;;      M8C System Macros
 0000           ;;===================================
 0000           
 0000           
 0000           ;-------------------------------
 0000           ;  Swapping Register Banks
 0000           ;-------------------------------
 0000           
 0000               macro M8C_SetBank0
 0000               and   F, ~FlagXIOMask
 0000               macro M8C_SetBank1
 0000               or    F, FlagXIOMask
 0000               macro M8C_EnableGInt
 0000               or    F, FlagGlobalIE
 0000               macro M8C_DisableGInt
 0000               and   F, ~FlagGlobalIE
 0001           DISABLE_INT_FIX:   equ   1
 0000           ;---------------------------------------------------
 0000           ;  Use the following macros to enable/disable
 0000           ;  either of the two global interrupt mask registers,
 0000           ;  INT_MSK0 or INT_MSK1.
 0000           ; 
 0000           ;  This is a fix to a noted problem in which an 
 0000           ;  inadvertant reset can occur if an interrupt occurs
 0000           ;  while clearing an interrupt mask bit.
 0000           ; 
 0000           ;  Usage:    M8C_DisableIntMask INT_MSKN, MASK
 0000           ;            M8C_EnableIntMask  INT_MSKN, MASK
 0000           ;            
 0000           ;  where INT_MSKN is INT_MSK0 or INT_MSK1 and
 0000           ;        MASK is the bit set to enable or disable
 0000           ;-------------------------------------------------
 0000           ; Disable Interrupt Bit Mask(s) 
 0000               macro M8C_DisableIntMask
 0000           if DISABLE_INT_FIX
 0000               mov   A, reg[CPU_SCR]           ; save the current Global interrupt state
 0000               M8C_DisableGInt                 ; disable global interrupts
 0000           endif
 0000               and   reg[@0], ~@1              ; disable specified interrupt enable bit
 0000           if DISABLE_INT_FIX
 0000               and   A, CPUSCR_GIEMask         ; determine if global interrupt was set
 0000               jz    . + 4                     ; jump if global interrupt disabled
 0000               M8C_EnableGInt                  ; set global interrupt
 0000           endif
 0000               macro M8C_EnableIntMask                             
 0000               or    reg[@0], @1              
 0000               macro M8C_EnableWatchDog
 0000               ; Clearing the Power-On Reset bit starts up the Watchdog timer
 0000               ; See the 25xxx/26xxx Family Datasheet, Section 9.3.4.
 0000               and   reg[CPU_SCR], ~CPUSCR_PORSMask & ~CPUSCR_WDRSMask
 0000               macro M8C_ClearWDT
 0000               mov   reg[RES_WDT], 00h
 0000               macro M8C_ClearWDTAndSleep
 0000               mov   reg[RES_WDT], 38h
 0000               macro M8C_Stall
 0000               or    reg[ASY_CR], ASY_CR_SYNCEN
 0000               macro M8C_Unstall
 0000               and   reg[ASY_CR], ~ASY_CR_SYNCEN
 0000               macro M8C_Sleep
 0000               or    reg[CPU_SCR], CPUSCR_SleepMask
 0000               ; The next instruction to be executed depends on the state of the
 0000               ; various interrupt enable bits. If some interrupts are enabled
 0000               ; and the global interrupts are disabled, the next instruction will
 0000               ; be the one that follows the invocation of this macro. If global
 0000               ; interrupts are also enabled then the next instruction will be
 0000               ; from the interrupt vector table. If no interrupts are enabled
 0000               ; then RIP.
 0000               macro M8C_Stop
 0000               ; In general, you probably don't want to do this, but here's how:
 0000               or    reg[CPU_SCR], CPUSCR_StopMask
 0000               ; Next instruction to be executed is located in the interrupt
 0000               ; vector table entry for Power-On Reset.
 0000               macro M8C_Reset
 0000               ; Restore everything to the power-on reset state.
 0000               mov A, 0
 0000               SSC
 0000               ; Next non-supervisor instruction will be at interrupt vector 0.
 0000               macro SSC
 0000               db 0
 0000               macro Suspend_CodeCompressor
 0000               or   f, 0
 0000               macro Resume_CodeCompressor
 0000               add  sp, 0
 0008           bTimer32_1_INT_MASK:     equ   08h
 00E1           Timer32_1_INT_REG:	      equ   0e1h
 0000           
 0000           ;---------------------------------
 0000           ;  Registers used by Timer32
 0000           ;---------------------------------
 0023           Timer32_1_CONTROL_LSB_REG:  equ 23h              ;Control register LSB
 0027           Timer32_1_CONTROL_ISB1_REG: equ 27h              ;Control register ISB1
 002B           Timer32_1_CONTROL_ISB2_REG: equ 2bh              ;Control register ISB2
 002F           Timer32_1_CONTROL_MSB_REG:  equ 2fh              ;Control register MSB
 0020           Timer32_1_COUNTER_LSB_REG:  equ 20h              ;Counter register LSB
 0024           Timer32_1_COUNTER_ISB1_REG: equ 24h              ;Counter register ISB1
 0028           Timer32_1_COUNTER_ISB2_REG: equ 28h              ;Counter register ISB2
 002C           Timer32_1_COUNTER_MSB_REG:  equ 2ch              ;Counter register MSB
 0021           Timer32_1_PERIOD_LSB_REG:   equ 21h              ;Period register LSB
 0025           Timer32_1_PERIOD_ISB1_REG:  equ 25h              ;Period register ISB1
 0029           Timer32_1_PERIOD_ISB2_REG:  equ 29h              ;Period register ISB2
 002D           Timer32_1_PERIOD_MSB_REG:   equ 2dh              ;Period register MSB
 0022           Timer32_1_COMPARE_LSB_REG:  equ 22h              ;CompareValue register LSB
 0026           Timer32_1_COMPARE_ISB1_REG: equ 26h              ;CompareValue register ISB1
 002A           Timer32_1_COMPARE_ISB2_REG: equ 2ah              ;CompareValue register ISB2
 002E           Timer32_1_COMPARE_MSB_REG:  equ 2eh              ;CompareValue register MSB
 0020           Timer32_1_FUNC_LSB_REG: equ 20h                  ;Function register LSB
 0024           Timer32_1_FUNC_ISB1_REG:    equ 24h              ;Function register ISB1
 0028           Timer32_1_FUNC_ISB2_REG:    equ 28h              ;Function register ISB2
 002C           Timer32_1_FUNC_MSB_REG: equ 2ch                  ;Function register MSB
 0021           Timer32_1_INPUT_LSB_REG:    equ 21h              ;Input register LSB
 0025           Timer32_1_INPUT_ISB1_REG:   equ 25h              ;Input register ISB1
 0029           Timer32_1_INPUT_ISB2_REG:   equ 29h              ;Input register ISB2
 002D           Timer32_1_INPUT_MSB_REG:    equ 2dh              ;Input register MSB
 0022           Timer32_1_OUTPUT_LSB_REG:   equ 22h              ;Output register LSB
 0026           Timer32_1_OUTPUT_ISB1_REG:  equ 26h              ;Output register ISB1
 002A           Timer32_1_OUTPUT_ISB2_REG:  equ 2ah              ;Output register ISB2
 002E           Timer32_1_OUTPUT_MSB_REG:   equ 2eh              ;Output register MSB
 0000           
 0000           ; end of file
 0000           
                area text (ROM, REL)
                
                ;-------------------------------------------------------------------
                ;  Declare the functions global for both assembler and C compiler.
                ;
                ;  Note that there are two names for each API. First name is 
                ;  assembler reference. Name with underscore is name refence for
                ;  C compiler.  Calling function in C source code does not require 
                ;  the underscore.
                ;-------------------------------------------------------------------
                export   Timer32_1_EnableInt 
                export  _Timer32_1_EnableInt 
                export   Timer32_1_DisableInt 
                export  _Timer32_1_DisableInt 
                export   Timer32_1_Start
                export  _Timer32_1_Start
                export   Timer32_1_Stop
                export  _Timer32_1_Stop
                export   Timer32_1_WritePeriod
                export  _Timer32_1_WritePeriod
                export   Timer32_1_WriteCompareValue
                export  _Timer32_1_WriteCompareValue
                export   Timer32_1_ReadCompareValue
                export  _Timer32_1_ReadCompareValue
                export   Timer32_1_ReadTimerSaveCV
                export  _Timer32_1_ReadTimerSaveCV 
                export   Timer32_1_ReadTimer
                export  _Timer32_1_ReadTimer 
                export   Timer32_1_ReadCounter        ; obsolete
                export  _Timer32_1_ReadCounter        ; obsolete
                export   Timer32_1_CaptureCounter     ; obsolete
                export  _Timer32_1_CaptureCounter     ; obsolete
                
                ;-----------
                ;  EQUATES
                ;-----------
 0001           bfCONTROL_REG_START_BIT:   equ   1     ; Control register start bit 
 0000           
 0000           ;-----------------------------------------------------------------------------
 0000           ;  FUNCTION NAME: Timer32_1_EnableInt
 0000           ;
 0000           ;  DESCRIPTION:
 0000           ;     Enables this Timer's interrupt by setting the interrupt enable mask bit
 0000           ;     associated with this User Module. Remember to call the global interrupt
 0000           ;     enable function by using the macro: M8C_EnableGInt.
 0000           ;
 0000           ;  ARGUMENTS:
 0000           ;     none.
 0000           ;
 0000           ;  RETURNS:
 0000           ;     none.
 0000           ;
 0000           ;  SIDE EFFECTS:
 0000           ;     none.
 0000           ;
 0000           ;  THEORY of OPERATION:  
 0000           ;     Sets the specific user module interrupt enable mask bit.
 0000           ;
 0000           ;-----------------------------------------------------------------------------
 0000            Timer32_1_EnableInt:
 0000           _Timer32_1_EnableInt:
 0000 43E108        or    reg[Timer32_1_INT_REG], bTimer32_1_INT_MASK              
 0003 7F           ret  
 0004           
 0004           
 0004           ;-----------------------------------------------------------------------------
 0004           ;  FUNCTION NAME: Timer32_1_DisableInt
 0004           ;
 0004           ;  DESCRIPTION:
 0004           ;     Disables this Timer's interrupt by clearing the interrupt enable mask bit
 0004           ;     associated with this User Module. 
 0004           ;
 0004           ;  ARGUMENTS:
 0004           ;     none.
 0004           ;
 0004           ;  RETURNS:
 0004           ;     none.
 0004           ;
 0004           ;  SIDE EFFECTS:
 0004           ;     none.
 0004           ;
 0004           ;  THEORY of OPERATION:  
 0004           ;     Clears the specific user module interrupt enable mask bit.
 0004           ;
 0004           ;-----------------------------------------------------------------------------
 0004            Timer32_1_DisableInt:
 0004           _Timer32_1_DisableInt:
                if DISABLE_INT_FIX
 0004 5DFF          mov   A, reg[CPU_SCR]           ; save the current Global interrupt state
 0006 70FE          and   F, ~FlagGlobalIE
                endif
 0008 41E1F7        and   reg[Timer32_1_INT_REG], ~bTimer32_1_INT_MASK              ; disable specified interrupt enable bit
                if DISABLE_INT_FIX
 000B 2180          and   A, CPUSCR_GIEMask         ; determine if global interrupt was set
 000D A003          jz    . + 4                     ; jump if global interrupt disabled
 000F 7101          or    F, FlagGlobalIE
                endif
 0011 7F           ret
 0012           
 0012           
 0012           ;-----------------------------------------------------------------------------
 0012           ;  FUNCTION NAME: Timer32_1_Start
 0012           ;
 0012           ;  DESCRIPTION:
 0012           ;     Sets the start bit in the Control register of this user module.  The
 0012           ;     counter will begin counting on the next input clock as soon as the 
 0012           ;     enable input is asserted high.
 0012           ;
 0012           ;  ARGUMENTS:
 0012           ;     none.
 0012           ;
 0012           ;  RETURNS:
 0012           ;     none.
 0012           ;
 0012           ;  SIDE EFFECTS:
 0012           ;     none.
 0012           ;
 0012           ;  THEORY of OPERATION:  
 0012           ;     Set the start bit in the Control register of the LSB block.
 0012           ;
 0012           ;-----------------------------------------------------------------------------
 0012            Timer32_1_Start:
 0012           _Timer32_1_Start:
 0012 432301       or    reg[Timer32_1_CONTROL_LSB_REG], bfCONTROL_REG_START_BIT
 0015 7F           ret  
 0016           
 0016           
 0016           ;-----------------------------------------------------------------------------
 0016           ;  FUNCTION NAME: Timer32_1_Stop
 0016           ;
 0016           ;  DESCRIPTION:
 0016           ;     Disables Timer operation.
 0016           ;
 0016           ;  ARGUMENTS:
 0016           ;     none.
 0016           ;
 0016           ;  RETURNS:
 0016           ;     none.
 0016           ;
 0016           ;  SIDE EFFECTS:
 0016           ;     After this function completes, the Counter register will latch any data
 0016           ;     written to the Period register.  Writing to the Period register is 
 0016           ;     performed using the Timer32_1_WritePeriod function.
 0016           ;
 0016           ;  THEORY of OPERATION:  
 0016           ;     Clear the start bit in the Control register of the LSB block.
 0016           ;
 0016           ;-----------------------------------------------------------------------------
 0016            Timer32_1_Stop:
 0016           _Timer32_1_Stop:
 0016 4123FE       and   reg[Timer32_1_CONTROL_LSB_REG], ~bfCONTROL_REG_START_BIT
 0019 7F           ret  
 001A           
 001A           
 001A           ;-----------------------------------------------------------------------------
 001A           ;  FUNCTION NAME: Timer32_1_WritePeriod
 001A           ;
 001A           ;  DESCRIPTION:
 001A           ;     Write the period value into the Period register.
 001A           ;
 001A           ;  ARGUMENTS:
 001A           ;     DWORD dwPeriodValue - period count - 
 001A           ;        X register points to 4 byte dword value 
 001A           ;        Note that X points to MSB.
 001A           ;
 001A           ;  RETURNS:
 001A           ;     none.
 001A           ;
 001A           ;  SIDE EFFECTS:
 001A           ;     If the Timer user module is stopped, then this value will also be
 001A           ;     latched into the Counter registers.
 001A           ;
 001A           ;  THEORY of OPERATION:  
 001A           ;     Write data into the Period registers.
 001A           ;
 001A           ;-----------------------------------------------------------------------------
 001A           _Timer32_1_WritePeriod:
 001A              ;compensate for compiler
 001A 5B           mov   A, X
 001B 01FD         add   A, -3
 001D 5C           mov   X, A
 001E              
 001E            Timer32_1_WritePeriod:
 001E 492301       tst   reg[Timer32_1_CONTROL_LSB_REG], bfCONTROL_REG_START_BIT
 0021 B036         jnz   .CounterRunning
 0023           
 0023           ; Counter is stopped.  Due to chip errata, we have to set the clock low for
 0023           ; the write to the period register to cause the data to be immediately transferred
 0023           ; into the Counter.
 0023           .CounterStopped:
 0023 7110          or    F, FlagXIOMask
 0025 5D21         mov   A, reg[Timer32_1_INPUT_LSB_REG]          ; save the context of the clock - input register
 0027 08           push  A
 0028 4121F0       and   reg[Timer32_1_INPUT_LSB_REG],  F0h      ; set the clock signal low
 002B 4125F0       and   reg[Timer32_1_INPUT_ISB1_REG], F0h
 002E 4129F0       and   reg[Timer32_1_INPUT_ISB2_REG], F0h
 0031 412DF0       and   reg[Timer32_1_INPUT_MSB_REG],  F0h
 0034 70EF          and   F, ~FlagXIOMask
 0036 5200         mov   A, [X]                                    ; load the period registers
 0038 602D         mov   reg[Timer32_1_PERIOD_MSB_REG], A
 003A 5201         mov   A, [X+1]
 003C 6029         mov   reg[Timer32_1_PERIOD_ISB2_REG], A
 003E 5202         mov   A, [X+2]
 0040 6025         mov   reg[Timer32_1_PERIOD_ISB1_REG], A
 0042 5203         mov   A, [X+3]
 0044 6021         mov   reg[Timer32_1_PERIOD_LSB_REG], A
 0046 18           pop   A
 0047 7110          or    F, FlagXIOMask
 0049 6021         mov   reg[Timer32_1_INPUT_LSB_REG], A          ; restore the clock
 004B 210F         and   A, 0Fh                                    ; High nibble is always 0x3 for higher order bits 
 004D 2930         or    A, 30h
 004F 6025         mov   reg[Timer32_1_INPUT_ISB1_REG], A         
 0051 6029         mov   reg[Timer32_1_INPUT_ISB2_REG], A
 0053 602D         mov   reg[Timer32_1_INPUT_MSB_REG],  A
 0055 70EF          and   F, ~FlagXIOMask
 0057 7F           ret
 0058           
 0058           ; Counter is running - write the period into the period register.
 0058           ; Upon Terminal Count this value will get loaded into the counter.
 0058           .CounterRunning:
 0058 5200         mov   A, [X]
 005A 602D         mov   reg[Timer32_1_PERIOD_MSB_REG], A
 005C 5201         mov   A, [X+1]
 005E 6029         mov   reg[Timer32_1_PERIOD_ISB2_REG], A
 0060 5202         mov   A, [X+2]
 0062 6025         mov   reg[Timer32_1_PERIOD_ISB1_REG], A
 0064 5203         mov   A, [X+3]
 0066 6021         mov   reg[Timer32_1_PERIOD_LSB_REG], A
 0068 7F           ret
 0069           
 0069           
 0069           ;-----------------------------------------------------------------------------
 0069           ;  FUNCTION NAME: Timer32_1_WriteCompareValue
 0069           ;
 0069           ;  DESCRIPTION:
 0069           ;     Writes compare value into the CompareValue register.
 0069           ;
 0069           ;     NOTE! The Timer user module must be STOPPED in order to write
 0069           ;           the CompareValue register.
 0069           ;
 0069           ;  ARGUMENTS:
 0069           ;     DWORD  dwCompareValue - compare value count - 
 0069           ;        X register points to 4 byte dword value 
 0069           ;        Note that X points to MSB.
 0069           ;
 0069           ;  RETURNS:
 0069           ;     none.
 0069           ;
 0069           ;  SIDE EFFECTS:
 0069           ;     none.
 0069           ;
 0069           ;  THEORY of OPERATION:  
 0069           ;     Write data into the CompareValue registers.
 0069           ;
 0069           ;-----------------------------------------------------------------------------
 0069           _Timer32_1_WriteCompareValue:
 0069              ;compensate for compiler
 0069 5B           mov   A, X
 006A 01FD         add   A, -3
 006C 5C           mov   X, A
 006D            Timer32_1_WriteCompareValue:
 006D 5200         mov   A, [X]
 006F 602E         mov   reg[Timer32_1_COMPARE_MSB_REG], A
 0071 5201         mov   A, [X+1]
 0073 602A         mov   reg[Timer32_1_COMPARE_ISB2_REG], A
 0075 5202         mov   A, [X+2]
 0077 6026         mov   reg[Timer32_1_COMPARE_ISB1_REG], A
 0079 5203         mov   A, [X+3]
 007B 6022         mov   reg[Timer32_1_COMPARE_LSB_REG], A
 007D 7F           ret
 007E           
 007E           
 007E           ;-----------------------------------------------------------------------------
 007E           ;  FUNCTION NAME: dwTimer32_1_ReadCompareValue
 007E           ;
 007E           ;  DESCRIPTION:
 007E           ;     Reads the CompareValue registers.
 007E           ;
 007E           ;     DWORD * pdwCompareValue - a pointer to a DWORD buffer to put the compare value. 
 007E           ;        The pointer is passed in the X register.
 007E           ;        X points to the MSB.
 007E           ;
 007E           ;  RETURNS:
 007E           ;     The CompareValue is placed in the data buffer pointed to by pdwCompareValue as
 007E           ;     passed in the X register.
 007E           ;
 007E           ;  SIDE EFFECTS:
 007E           ;     none.
 007E           ;
 007E           ;  THEORY of OPERATION:  
 007E           ;     Read the CompareValue register and return value in buffer pointed by 
 007E           ;     X.
 007E           ;-----------------------------------------------------------------------------
 007E            Timer32_1_ReadCompareValue:
 007E           _Timer32_1_ReadCompareValue:
 007E 5D2E         mov   A, reg[Timer32_1_COMPARE_MSB_REG]
 0080 5400         mov   [X], A
 0082 5D2A         mov   A, reg[Timer32_1_COMPARE_ISB2_REG]
 0084 5401         mov   [X+1], A
 0086 5D26         mov   A, reg[Timer32_1_COMPARE_ISB1_REG]
 0088 5402         mov   [X+2], A
 008A 5D22         mov   A, reg[Timer32_1_COMPARE_LSB_REG]
 008C 5403         mov   [X+3], A
 008E 7F           ret
 008F           
 008F           
 008F           ;-----------------------------------------------------------------------------
 008F           ;  FUNCTION NAME: Timer32_1_ReadTimerSaveCV
 008F           ;
 008F           ;  DESCRIPTION:
 008F           ;     Reads the count in the Counter register.  This function preserves the
 008F           ;     contents of the CompareValue register.  However, the cost of doing so
 008F           ;     is that the counter is halted.  This may cause the timer to miss one or 
 008F           ;     more counts, depending on the speed of the input clock.
 008F           ;
 008F           ;  ARGUMENTS:
 008F           ;     DWORD * pdwCount - a pointer to a DWORD buffer to put the counter value. 
 008F           ;        The pointer is passed in the X register.
 008F           ;     X points to the MSB 
 008F           ;
 008F           ;  RETURNS:
 008F           ;     The read value is placed in the data buffer pointed to by pdwCount as
 008F           ;     passed in the X register.
 008F           ;
 008F           ;  SIDE EFFECTS:
 008F           ;     1) May cause an interrupt, if interrupt on CompareValue is enabled.
 008F           ;     2) The user module is stopped momentarily while the compare value is
 008F           ;        restored.  This may cause the Count register to miss one or more
 008F           ;        counts depending on the input clock speed.
 008F           ;     3) Interrupts are momentarily disabled - this may cause other interrupt
 008F           ;        latency issues.
 008F           ;
 008F           ;  THEORY of OPERATION:  
 008F           ;     1) Read and save the CompareValue register.
 008F           ;     2) Read the Counter register, causing its data to be latched into 
 008F           ;        the CompareValue register.
 008F           ;     3) Read and save the Counter value, now in the CompareValue register,
 008F           ;        to the buffer.
 008F           ;     4) Disable global interrupts
 008F           ;     5) Halt the timer
 008F           ;     6) Restore the CompareValue register values
 008F           ;     7) Start the Counter again
 008F           ;     8) Restore global interrupt state
 008F           ;
 008F           ;-----------------------------------------------------------------------------
 008F            Timer32_1_ReadTimerSaveCV:
 008F           _Timer32_1_ReadTimerSaveCV: 
 008F            Timer32_1_ReadCounter:            ; obsolete
 008F           _Timer32_1_ReadCounter:            ; obsolete
 008F           
 008F              ; save the control register on the stack
 008F 5D23         mov   A, reg[Timer32_1_CONTROL_LSB_REG]
 0091 08           push  A
 0092           
 0092              ; save the CompareValue register value
 0092 5D2E         mov   A, reg[Timer32_1_COMPARE_MSB_REG]    
 0094 08           push  A
 0095 5D2A         mov   A, reg[Timer32_1_COMPARE_ISB2_REG]    
 0097 08           push  A
 0098 5D26         mov   A, reg[Timer32_1_COMPARE_ISB1_REG]    
 009A 08           push  A
 009B 5D22         mov   A, reg[Timer32_1_COMPARE_LSB_REG]    
 009D 08           push  A
 009E           
 009E              ; Read the LSB counter. This latches the counter data into the
 009E              ; CompareValue register of all bytes of chained PSoC blocks!
 009E              ; This may cause an interrupt.
 009E 5D20         mov   A, reg[Timer32_1_COUNTER_LSB_REG]    
 00A0           
 00A0              ; Read the CompareValue register, which contains the counter value
 00A0              ; and store ther return result
 00A0 5D2E         mov   A, reg[Timer32_1_COMPARE_MSB_REG]    
 00A2 5400         mov   [X], A
 00A4 5D2A         mov   A, reg[Timer32_1_COMPARE_ISB2_REG]    
 00A6 5401         mov   [X+1], A
 00A8 5D26         mov   A, reg[Timer32_1_COMPARE_ISB1_REG]    
 00AA 5402         mov   [X+2], A
 00AC 5D22         mov   A, reg[Timer32_1_COMPARE_LSB_REG]    
 00AE 5403         mov   [X+3], A
 00B0              
 00B0              ; determine current interrupt state and save in X
 00B0 5000         mov   A, 0
 00B2 49FF80       tst   reg[CPU_SCR], CPUSCR_GIEMask
 00B5 A003         jz    .SetupStatusFlag
 00B7 5001         mov   A, FlagGlobalIE
 00B9           .SetupStatusFlag:
 00B9 5C           mov   X, A
 00BA                 
 00BA              ; disable interrupts for the time being
 00BA 70FE          and   F, ~FlagGlobalIE
 00BC           
 00BC              ; stop the timer
 00BC 4123FE       and   reg[Timer32_1_CONTROL_LSB_REG], ~bfCONTROL_REG_START_BIT
 00BF           
 00BF              ; Restore the CompareValue register
 00BF 18           pop   A
 00C0 6022         mov   reg[Timer32_1_COMPARE_LSB_REG], A
 00C2 18           pop   A
 00C3 6026         mov   reg[Timer32_1_COMPARE_ISB1_REG], A
 00C5 18           pop   A
 00C6 602A         mov   reg[Timer32_1_COMPARE_ISB2_REG], A
 00C8 18           pop   A
 00C9 602E         mov   reg[Timer32_1_COMPARE_MSB_REG], A
 00CB           
 00CB              ; start the timer
 00CB 18           pop   A
 00CC 6023         mov   reg[Timer32_1_CONTROL_LSB_REG], A
 00CE           
 00CE              ; put the flag register to restore on the stack
 00CE 10           push  X
 00CF           
 00CF              ; Use RETI because it pops a the flag register off the stack
 00CF              ; and then returns to the caller.
 00CF 7E           reti
 00D0           
 00D0           
 00D0           ;-----------------------------------------------------------------------------
 00D0           ;  FUNCTION NAME: Timer32_1_ReadTimer
 00D0           ;
 00D0           ;  DESCRIPTION:
 00D0           ;     Performs a software capture of the Counter register.  A synchronous
 00D0           ;     read of the counter register is performed.  The timer is NOT stopped.
 00D0           ;
 00D0           ;     WARNING - this will cause loss of the CompareValue register data.
 00D0           ;
 00D0           ;  ARGUMENTS:
 00D0           ;     DWORD * pdwCount - a pointer to a DWORD buffer to put the counter value. 
 00D0           ;        The pointer is passed in the X register.
 00D0           ;     X points to the MSB 
 00D0           ;
 00D0           ;  RETURNS:
 00D0           ;     The read value is placed in the data buffer pointed to by pdwCount as
 00D0           ;     passed in the X register.
 00D0           ;
 00D0           ;  SIDE EFFECTS:
 00D0           ;     May cause an interrupt.
 00D0           ;
 00D0           ;  THEORY of OPERATION:  
 00D0           ;     1) Read the CounterRegister - this causes the count value to be 
 00D0           ;        latched into the CompareValue registers.
 00D0           ;     2) Read and return the count register values from the CompareValue
 00D0           ;        registers into the return buffer.
 00D0           ;
 00D0           ;-----------------------------------------------------------------------------
 00D0            Timer32_1_ReadTimer:
 00D0           _Timer32_1_ReadTimer: 
 00D0            Timer32_1_CaptureCounter:      ; obsolete
 00D0           _Timer32_1_CaptureCounter:      ; obsolete
 00D0           
 00D0              ; Read the LSB counter. This latches the counter data into the
 00D0              ; CompareValue register of all bytes of chained PSoC blocks!
 00D0              ; This may cause an interrupt.
 00D0 5D20         mov   A, reg[Timer32_1_COUNTER_LSB_REG]    
 00D2           
 00D2              ; Read the CompareValue register, which contains the counter value
 00D2              ; and store ther return result
 00D2 5D2E         mov   A, reg[Timer32_1_COMPARE_MSB_REG]    
 00D4 5400         mov   [X+0], A
 00D6 5D2A         mov   A, reg[Timer32_1_COMPARE_ISB2_REG]    
 00D8 5401         mov   [X+1], A
 00DA 5D26         mov   A, reg[Timer32_1_COMPARE_ISB1_REG]    
 00DC 5402         mov   [X+2], A
 00DE 5D22         mov   A, reg[Timer32_1_COMPARE_LSB_REG]    
 00E0 5403         mov   [X+3], A
 00E2           
 00E2 7F           ret
 00E3           ; end of Timer32 API code
 00E3           
 00E3           
