//
//	This file contains defines to support oscillator register initialization
//

#define CPU_CLOCK				0x0			//CPU clock value
#define CPU_CLOCK_MASK			0x7 		//CPU clock mask
#define CPU_CLOCK_JUST			0x0 		//CPU clock value justified
#define SELECT_32K				0x0 		//32K select value
#define SELECT_32K_MASK			0x80 		//32K select mask
#define SELECT_32K_JUST			0x0 		//32K select value justified
#define PLL_MODE				0x0 		//PLL mode value
#define PLL_MODE_MASK			0x40 		//PLL mode mask
#define PLL_MODE_JUST			0x0 		//PLL mode value justified
#define SLEEP_TIMER				0x0 		//Sleep Timer value
#define SLEEP_TIMER_MASK		0x18 	//Sleep Timer mask
#define SLEEP_TIMER_JUST		0x0 	//Sleep Timer value justified
#define SWITCH_MODE_PUMP		0x1 		//Switch Mode Pump value (off)
#define SWITCH_MODE_PUMP_MASK	0x80 	//Switch Mode Pump mask 
#define SWITCH_MODE_PUMP_JUST	0x80 	//Switch Mode Pump value justified
#define TRIP_VOLTAGE			0x7 		//Trip Voltage
#define SUPPLY_VOLTAGE			0x1 		//Supply Voltage 1 = 5.0V
									//				0 = 3.3V
#define CLOCK_DIV_24V1			0xf	// 24V1 clock divider 
#define CLOCK_DIV_24V1_MASK		0xf0	// 24V1 clock divider mask
#define CLOCK_DIV_24V1_JUST		0xf0	// 24V1 clock divider justified
#define CLOCK_DIV_24V2			0xf	// 24V2 clock divider 
#define CLOCK_DIV_24V2_MASK		0xf	// 24V2 clock divider mask
#define CLOCK_DIV_24V2_JUST		0xf	// 24V2 clock divider justified
#define ANALOG_BUFFER_PWR		0x0	// Analog buffer power level
#define ANALOG_BUFFER_PWR_MASK	0x1	// Analog buffer power level mask
#define ANALOG_BUFFER_PWR_JUST	0x0	// Analog buffer power level justified
#define ANALOG_POWER			0x5	// Analog power control
#define ANALOG_POWER_MASK		0x7	// Analog power control mask
#define ANALOG_POWER_JUST		0x5	// Analog power control justified
#define OP_AMP_BIAS				0x0	// Op amp bias level
#define OP_AMP_BIAS_MASK		0x40	// Op amp bias level mask
#define OP_AMP_BIAS_JUST		0x0	// Op amp bias level justified
#define REF_MUX					0x0	// Ref mux setting
#define REF_MUX_MASK			0x38	// Ref mux setting mask
#define REF_MUX_JUST			0x0	// Ref mux setting justified
//
// write only registers
//
#define ANALOG_IO_CONTROL	0x0 	//Analog IO Control register (ABF_CR)
#define PORT_0_BYPASS		0x0 	//Port 0 bypass register (PRT0GS)
#define PORT_0_DRIVE_0		0x0 	//Port 0 drive mode 0 register (PRT0DM0)
#define PORT_0_DRIVE_1		0x0 	//Port 0 drive mode 1 register (PRT0DM1)
#define PORT_0_INTENABLE	0x0 	//Port 0 interrupt enable register (PRT0IE)
#define PORT_0_INTCTRL_0	0x0 	//Port 0 interrupt control 0 register (PRT0IC0)
#define PORT_0_INTCTRL_1	0x0 	//Port 0 interrupt control 1 register (PRT0IC1)
#define PORT_1_BYPASS		0x0 	//Port 1 bypass register (PRT1GS)
#define PORT_1_DRIVE_0		0x0 	//Port 1 drive mode 0 register (PRT1DM0)
#define PORT_1_DRIVE_1		0x0 	//Port 1 drive mode 1 register (PRT1DM1)
#define PORT_1_INTENABLE	0x0 	//Port 1 interrupt enable register (PRT1IE)
#define PORT_1_INTCTRL_0	0x0 	//Port 1 interrupt control 0 register (PRT1IC0)
#define PORT_1_INTCTRL_1	0x0 	//Port 1 interrupt control 1 register (PRT1IC1)
#define PORT_2_BYPASS		0x0 	//Port 2 bypass register (PRT2GS)
#define PORT_2_DRIVE_0		0x0 	//Port 2 drive mode 0 register (PRT2DM0)
#define PORT_2_DRIVE_1		0x0 	//Port 2 drive mode 1 register (PRT2DM1)
#define PORT_2_INTENABLE	0x0 	//Port 2 interrupt enable register (PRT2IE)
#define PORT_2_INTCTRL_0	0x0 	//Port 2 interrupt control 0 register (PRT2IC0)
#define PORT_2_INTCTRL_1	0x0 	//Port 2 interrupt control 1 register (PRT2IC1)
#define PORT_3_BYPASS		0x0 	//Port 3 bypass register (PRT3GS)
#define PORT_3_DRIVE_0		0x0 	//Port 3 drive mode 0 register (PRT3DM0)
#define PORT_3_DRIVE_1		0x0 	//Port 3 drive mode 1 register (PRT3DM1)
#define PORT_3_INTENABLE	0x0 	//Port 3 interrupt enable register (PRT3IE)
#define PORT_3_INTCTRL_0	0x0 	//Port 3 interrupt control 0 register (PRT3IC0)
#define PORT_3_INTCTRL_1	0x0 	//Port 3 interrupt control 1 register (PRT3IC1)
#define PORT_4_BYPASS		0x0 	//Port 4 bypass register (PRT4GS)
#define PORT_4_DRIVE_0		0x0 	//Port 4 drive mode 0 register (PRT4DM0)
#define PORT_4_DRIVE_1		0x0 	//Port 4 drive mode 1 register (PRT4DM1)
#define PORT_4_INTENABLE	0x0 	//Port 4 interrupt enable register (PRT4IE)
#define PORT_4_INTCTRL_0	0x0 	//Port 4 interrupt control 0 register (PRT4IC0)
#define PORT_4_INTCTRL_1	0x0 	//Port 4 interrupt control 1 register (PRT4IC1)
#define PORT_5_BYPASS		0x0 	//Port 5 bypass register (PRT5GS)
#define PORT_5_DRIVE_0		0x0 	//Port 5 drive mode 0 register (PRT5DM0)
#define PORT_5_DRIVE_1		0x0 	//Port 5 drive mode 1 register (PRT5DM1)
#define PORT_5_INTENABLE	0x0 	//Port 5 interrupt enable register (PRT5IE)
#define PORT_5_INTCTRL_0	0x0 	//Port 5 interrupt control 0 register (PRT5IC0)
#define PORT_5_INTCTRL_1	0x0 	//Port 5 interrupt control 1 register (PRT5IC1)