
     | | | | | | |
   _________________
  -|               |-
  -|               |-
  -|               |-
  -|    CYPRESS    |-
  -|               |-
  -|               |-   Warp VHDL Synthesis Compiler: Version 6.2 IR 28.4
  -|               |-   Copyright (C) 1991-2001 Cypress Semiconductor
   |_______________|
     | | | | | | |

======================================================================
Compiling:  pc_remote_bus.vhd
Options:    -m -yu -e10 -w100 -o2 -ygs -fO -fP -v10 -dc37256 -pcy37256p160-125ac -b pc_remote_bus.vhd -u pcRemoteBusRev2dot1.hie -uch0000
======================================================================

vhdlfe V6.2 IR 27:  VHDL parser
Wed Aug 20 15:40:33 2003

Library 'work' => directory 'lc37256'
Linking 'C:\Program Files\Cypress\Warp\bin\std.vhd'.
Linking 'C:\Program Files\Cypress\Warp\lib\common\cypress.vhd'.
Linking 'C:\Program Files\Cypress\Warp\lib\common\work\cypress.vif'.
Using control file 'pc_remote_bus.ctl'.
Library 'ieee' => directory 'C:\Program Files\Cypress\Warp\lib\ieee\work'
Linking 'C:\Program Files\Cypress\Warp\lib\ieee\work\stdlogic.vif'.
Linking 'C:\Program Files\Cypress\Warp\lib\common\stdlogic\lpmpkg.vif'.
Linking 'C:\Program Files\Cypress\Warp\lib\common\stdlogic\rtlpkg.vif'.
Linking 'C:\Program Files\Cypress\Warp\lib\common\stdlogic\mod_cnst.vif'.
Linking 'C:\Program Files\Cypress\Warp\lib\common\stdlogic\mod_mthu.vif'.
Linking 'C:\Program Files\Cypress\Warp\lib\common\stdlogic\mod_mths.vif'.
Linking 'C:\Program Files\Cypress\Warp\lib\common\stdlogic\mod_genu.vif'.
Note:  Using config. rule 'clk' to set attribute 'pin_numbers' on 'clk'.
Note:  Using config. rule 'reset' to set attribute 'pin_numbers' on 'reset'.
pc_remote_bus.vhd (line 89, col 34):  Note: Substituting module 'cmp_vv_us' for '='.
pc_remote_bus.vhd (line 93, col 36):  Note: Substituting module 'add_vi_us' for '+'.
pc_remote_bus.vhd (line 102, col 34):  Note: Substituting module 'cmp_vv_us' for '='.
pc_remote_bus.vhd (line 105, col 36):  Note: Substituting module 'add_vi_us' for '+'.
Library 'ieee' => directory 'C:\Program Files\Cypress\Warp\lib\ieee\work'
Note:  Using config. rule 'clk' to set attribute 'pin_numbers' on 'clk'.
Note:  Using config. rule 'reset' to set attribute 'pin_numbers' on 'reset'.
pc_remote_bus.vhd (line 257, col 34):  Note: Substituting module 'cmp_vv_us' for '='.
pc_remote_bus.vhd (line 263, col 36):  Note: Substituting module 'add_vi_us' for '+'.
pc_remote_bus.vhd (line 279, col 34):  Note: Substituting module 'cmp_vv_us' for '='.
pc_remote_bus.vhd (line 288, col 36):  Note: Substituting module 'add_vi_us' for '+'.
pc_remote_bus.vhd (line 322, col 34):  Note: Substituting module 'cmp_vv_us' for '='.
pc_remote_bus.vhd (line 325, col 36):  Note: Substituting module 'add_vi_us' for '+'.
pc_remote_bus.vhd (line 333, col 34):  Note: Substituting module 'cmp_vv_us' for '='.
pc_remote_bus.vhd (line 336, col 36):  Note: Substituting module 'add_vi_us' for '+'.
Library 'ieee' => directory 'C:\Program Files\Cypress\Warp\lib\ieee\work'
Note:  Using config. rule 'clk' to set attribute 'pin_numbers' on 'clk'.
Note:  Using config. rule 'reset' to set attribute 'pin_numbers' on 'reset'.
Note:  Using config. rule 'led1' to set attribute 'pin_numbers' on 'led1'.
pc_remote_bus.vhd (line 450, col 44):  Note: Substituting module 'cmp_vv_us' for '='.
pc_remote_bus.vhd (line 454, col 35):  Note: Substituting module 'add_vi_us' for '+'.
pc_remote_bus.vhd (line 462, col 43):  Note: Substituting module 'cmp_vv_us' for '='.
pc_remote_bus.vhd (line 467, col 34):  Note: Substituting module 'add_vi_us' for '+'.
pc_remote_bus.vhd (line 475, col 33):  Note: Substituting module 'cmp_vv_us' for '='.
pc_remote_bus.vhd (line 478, col 36):  Note: Substituting module 'add_vi_us' for '+'.
pc_remote_bus.vhd (line 484, col 43):  Note: Substituting module 'cmp_vv_us' for '='.
pc_remote_bus.vhd (line 486, col 34):  Note: Substituting module 'add_vi_us' for '+'.
pc_remote_bus.vhd (line 488, col 34):  Note: Substituting module 'add_vi_us' for '+'.
pc_remote_bus.vhd (line 494, col 43):  Note: Substituting module 'cmp_vv_us' for '='.
pc_remote_bus.vhd (line 499, col 34):  Note: Substituting module 'add_vi_us' for '+'.
pc_remote_bus.vhd (line 506, col 34):  Note: Substituting module 'cmp_vv_us' for '='.
pc_remote_bus.vhd (line 509, col 37):  Note: Substituting module 'add_vi_us' for '+'.
Library 'ieee' => directory 'C:\Program Files\Cypress\Warp\lib\ieee\work'
Note:  Using config. rule 'clk' to set attribute 'pin_numbers' on 'clk'.
Note:  Using config. rule 'reset' to set attribute 'pin_numbers' on 'reset'.
Note:  Using config. rule 'hva_chassis_en_l' to set attribute 'pin_numbers' on 'hva_chassis_en_l'.
pc_remote_bus.vhd (line 609, col 37):  Note: Substituting module 'cmp_vv_us' for '='.
pc_remote_bus.vhd (line 621, col 50):  Note: Substituting module 'cmp_vv_us' for '='.
pc_remote_bus.vhd (line 658, col 45):  Note: Substituting module 'cmp_vv_us' for '='.
pc_remote_bus.vhd (line 673, col 46):  Note: Substituting module 'add_vi_us' for '+'.
pc_remote_bus.vhd (line 677, col 33):  Note: Substituting module 'cmp_vv_us' for '='.
pc_remote_bus.vhd (line 681, col 40):  Note: Substituting module 'add_vi_us' for '+'.
Library 'ieee' => directory 'C:\Program Files\Cypress\Warp\lib\ieee\work'
Note:  Using config. rule 'clk' to set attribute 'pin_numbers' on 'clk'.
Note:  Using config. rule 'fast' to set attribute 'pin_numbers' on 'fast'.
Note:  Using config. rule 'slow' to set attribute 'pin_numbers' on 'slow'.
Note:  Using config. rule 'led2' to set attribute 'pin_numbers' on 'led2'.
Note:  Using config. rule 'led3' to set attribute 'pin_numbers' on 'led3'.
Note:  Using config. rule 'reset' to set attribute 'pin_numbers' on 'reset'.
Library 'ieee' => directory 'C:\Program Files\Cypress\Warp\lib\ieee\work'
Note:  Using config. rule 'led1' to set attribute 'pin_numbers' on 'led1'.
Note:  Using config. rule 'led2' to set attribute 'pin_numbers' on 'led2'.
Note:  Using config. rule 'led3' to set attribute 'pin_numbers' on 'led3'.
Note:  Using config. rule 'clk' to set attribute 'pin_numbers' on 'clk'.
Note:  Using config. rule 'fast' to set attribute 'pin_numbers' on 'fast'.
Note:  Using config. rule 'slow' to set attribute 'pin_numbers' on 'slow'.
Note:  Using config. rule 'reset' to set attribute 'pin_numbers' on 'reset'.
Note:  Using config. rule 'ao_from_pc_strobe' to set attribute 'pin_numbers' on 'ao_from_pc_strobe'.
Note:  Using config. rule 'ao_from_pc_ack' to set attribute 'pin_numbers' on 'ao_from_pc_ack'.
Note:  Using config. rule 'ao_to_pc_strobe' to set attribute 'pin_numbers' on 'ao_to_pc_strobe'.
Note:  Using config. rule 'ao_to_pc_ack' to set attribute 'pin_numbers' on 'ao_to_pc_ack'.
Note:  Using config. rule 'bpd_h_dir' to set attribute 'pin_numbers' on 'bpd_h_dir'.
Note:  Using config. rule 'bpd_h_tristate' to set attribute 'pin_numbers' on 'bpd_h_tristate'.
Note:  Using config. rule 'bpd_l_dir' to set attribute 'pin_numbers' on 'bpd_l_dir'.
Note:  Using config. rule 'bpd_l_tristate' to set attribute 'pin_numbers' on 'bpd_l_tristate'.
Note:  Using config. rule 'bpaddr_dir' to set attribute 'pin_numbers' on 'bpaddr_dir'.
Note:  Using config. rule 'bpaddr_tristate' to set attribute 'pin_numbers' on 'bpaddr_tristate'.
Note:  Using config. rule 'bpctrl_h_dir' to set attribute 'pin_numbers' on 'bpctrl_h_dir'.
Note:  Using config. rule 'bpctrl_l_dir' to set attribute 'pin_numbers' on 'bpctrl_l_dir'.
Note:  Using config. rule 'bpctrl_h_tristate' to set attribute 'pin_numbers' on 'bpctrl_h_tristate'.
Note:  Using config. rule 'bpctrl_l_tristate' to set attribute 'pin_numbers' on 'bpctrl_l_tristate'.
Note:  Using config. rule 'sinphase_zeros' to set attribute 'pin_numbers' on 'sinphase_zeros'.
Note:  Using config. rule 'hva_chassis_en_l' to set attribute 'pin_numbers' on 'hva_chassis_en_l'.
Note:  Using config. rule 'bpctrl(15)' to set attribute 'pin_numbers' on 'bpctrl(15)'.
Note:  Using config. rule 'bpctrl(14)' to set attribute 'pin_numbers' on 'bpctrl(14)'.
Note:  Using config. rule 'bpctrl(13)' to set attribute 'pin_numbers' on 'bpctrl(13)'.
Note:  Using config. rule 'bpctrl(12)' to set attribute 'pin_numbers' on 'bpctrl(12)'.
Note:  Using config. rule 'bpctrl(11)' to set attribute 'pin_numbers' on 'bpctrl(11)'.
Note:  Using config. rule 'bpctrl(10)' to set attribute 'pin_numbers' on 'bpctrl(10)'.
Note:  Using config. rule 'bpctrl(9)' to set attribute 'pin_numbers' on 'bpctrl(9)'.
Note:  Using config. rule 'bpctrl(8)' to set attribute 'pin_numbers' on 'bpctrl(8)'.
Note:  Using config. rule 'bpctrl(7)' to set attribute 'pin_numbers' on 'bpctrl(7)'.
Note:  Using config. rule 'bpctrl(6)' to set attribute 'pin_numbers' on 'bpctrl(6)'.
Note:  Using config. rule 'bpctrl(5)' to set attribute 'pin_numbers' on 'bpctrl(5)'.
Note:  Using config. rule 'bpctrl(4)' to set attribute 'pin_numbers' on 'bpctrl(4)'.
Note:  Using config. rule 'bpctrl(3)' to set attribute 'pin_numbers' on 'bpctrl(3)'.
Note:  Using config. rule 'bpctrl(2)' to set attribute 'pin_numbers' on 'bpctrl(2)'.
Note:  Using config. rule 'bpctrl(1)' to set attribute 'pin_numbers' on 'bpctrl(1)'.
Note:  Using config. rule 'bpctrl(0)' to set attribute 'pin_numbers' on 'bpctrl(0)'.
Note:  Using config. rule 'clk' to set attribute 'pin_numbers' on 'clk'.
Note:  Using config. rule 'fast' to set attribute 'pin_numbers' on 'fast'.
Note:  Using config. rule 'slow' to set attribute 'pin_numbers' on 'slow'.
Note:  Using config. rule 'led2' to set attribute 'pin_numbers' on 'led2'.
Note:  Using config. rule 'led3' to set attribute 'pin_numbers' on 'led3'.
Note:  Using config. rule 'reset' to set attribute 'pin_numbers' on 'reset'.
Note:  Using config. rule 'clk' to set attribute 'pin_numbers' on 'clk'.
Note:  Using config. rule 'reset' to set attribute 'pin_numbers' on 'reset'.
Note:  Using config. rule 'clk' to set attribute 'pin_numbers' on 'clk'.
Note:  Using config. rule 'reset' to set attribute 'pin_numbers' on 'reset'.
Note:  Using config. rule 'clk' to set attribute 'pin_numbers' on 'clk'.
Note:  Using config. rule 'reset' to set attribute 'pin_numbers' on 'reset'.
Note:  Using config. rule 'led1' to set attribute 'pin_numbers' on 'led1'.
Note:  Using config. rule 'clk' to set attribute 'pin_numbers' on 'clk'.
Note:  Using config. rule 'reset' to set attribute 'pin_numbers' on 'reset'.
Note:  Using config. rule 'hva_chassis_en_l' to set attribute 'pin_numbers' on 'hva_chassis_en_l'.

vhdlfe:  No errors.


tovif V6.2 IR 27:  High-level synthesis
Wed Aug 20 15:40:33 2003

Linking 'C:\Program Files\Cypress\Warp\bin\std.vhd'.
Linking 'C:\Program Files\Cypress\Warp\lib\common\cypress.vhd'.
Linking 'C:\Program Files\Cypress\Warp\lib\common\work\cypress.vif'.
Linking 'C:\Documents and Settings\miket\My Documents\WORK\current_code\pc_remote_bus_rev2.1_reset\pc_remote_bus.ctl'.
Linking 'C:\Program Files\Cypress\Warp\lib\ieee\work\stdlogic.vif'.
Linking 'C:\Program Files\Cypress\Warp\lib\common\stdlogic\lpmpkg.vif'.
Linking 'C:\Program Files\Cypress\Warp\lib\common\stdlogic\rtlpkg.vif'.
Linking 'C:\Program Files\Cypress\Warp\lib\common\stdlogic\mod_cnst.vif'.
Linking 'C:\Program Files\Cypress\Warp\lib\common\stdlogic\mod_mthu.vif'.
Linking 'C:\Program Files\Cypress\Warp\lib\common\stdlogic\mod_mths.vif'.
Linking 'C:\Program Files\Cypress\Warp\lib\common\stdlogic\mod_genu.vif'.
Linking 'C:\Program Files\Cypress\Warp\lib\common\stdlogic\mcompare.vif'.
pc_remote_bus.vhd (line 572, col 25):  Warning: (W479) 'phase' should be referenced in the sensitivity list.
Note:  Using config. rule 'd(31)' to set attribute 'pin_numbers' on 'd(31)'.
Note:  Using config. rule 'd(30)' to set attribute 'pin_numbers' on 'd(30)'.
Note:  Using config. rule 'd(29)' to set attribute 'pin_numbers' on 'd(29)'.
Note:  Using config. rule 'd(28)' to set attribute 'pin_numbers' on 'd(28)'.
Note:  Using config. rule 'd(27)' to set attribute 'pin_numbers' on 'd(27)'.
Note:  Using config. rule 'd(26)' to set attribute 'pin_numbers' on 'd(26)'.
Note:  Using config. rule 'd(25)' to set attribute 'pin_numbers' on 'd(25)'.
Note:  Using config. rule 'd(24)' to set attribute 'pin_numbers' on 'd(24)'.
Note:  Using config. rule 'd(23)' to set attribute 'pin_numbers' on 'd(23)'.
Note:  Using config. rule 'd(22)' to set attribute 'pin_numbers' on 'd(22)'.
Note:  Using config. rule 'd(21)' to set attribute 'pin_numbers' on 'd(21)'.
Note:  Using config. rule 'd(20)' to set attribute 'pin_numbers' on 'd(20)'.
Note:  Using config. rule 'd(19)' to set attribute 'pin_numbers' on 'd(19)'.
Note:  Using config. rule 'd(18)' to set attribute 'pin_numbers' on 'd(18)'.
Note:  Using config. rule 'd(17)' to set attribute 'pin_numbers' on 'd(17)'.
Note:  Using config. rule 'd(16)' to set attribute 'pin_numbers' on 'd(16)'.
Note:  Using config. rule 'd(15)' to set attribute 'pin_numbers' on 'd(15)'.
Note:  Using config. rule 'd(14)' to set attribute 'pin_numbers' on 'd(14)'.
Note:  Using config. rule 'd(13)' to set attribute 'pin_numbers' on 'd(13)'.
Note:  Using config. rule 'd(12)' to set attribute 'pin_numbers' on 'd(12)'.
Note:  Using config. rule 'd(11)' to set attribute 'pin_numbers' on 'd(11)'.
Note:  Using config. rule 'd(10)' to set attribute 'pin_numbers' on 'd(10)'.
Note:  Using config. rule 'd(9)' to set attribute 'pin_numbers' on 'd(9)'.
Note:  Using config. rule 'd(8)' to set attribute 'pin_numbers' on 'd(8)'.
Note:  Using config. rule 'd(7)' to set attribute 'pin_numbers' on 'd(7)'.
Note:  Using config. rule 'd(6)' to set attribute 'pin_numbers' on 'd(6)'.
Note:  Using config. rule 'd(5)' to set attribute 'pin_numbers' on 'd(5)'.
Note:  Using config. rule 'd(4)' to set attribute 'pin_numbers' on 'd(4)'.
Note:  Using config. rule 'd(3)' to set attribute 'pin_numbers' on 'd(3)'.
Note:  Using config. rule 'd(2)' to set attribute 'pin_numbers' on 'd(2)'.
Note:  Using config. rule 'd(1)' to set attribute 'pin_numbers' on 'd(1)'.
Note:  Using config. rule 'd(0)' to set attribute 'pin_numbers' on 'd(0)'.
Note:  Using config. rule 'bpaddr(7)' to set attribute 'pin_numbers' on 'bpaddr(7)'.
Note:  Using config. rule 'bpaddr(6)' to set attribute 'pin_numbers' on 'bpaddr(6)'.
Note:  Using config. rule 'bpaddr(5)' to set attribute 'pin_numbers' on 'bpaddr(5)'.
Note:  Using config. rule 'bpaddr(4)' to set attribute 'pin_numbers' on 'bpaddr(4)'.
Note:  Using config. rule 'bpaddr(3)' to set attribute 'pin_numbers' on 'bpaddr(3)'.
Note:  Using config. rule 'bpaddr(2)' to set attribute 'pin_numbers' on 'bpaddr(2)'.
Note:  Using config. rule 'bpaddr(1)' to set attribute 'pin_numbers' on 'bpaddr(1)'.
Note:  Using config. rule 'bpaddr(0)' to set attribute 'pin_numbers' on 'bpaddr(0)'.
Note:  Using config. rule 'bpd(15)' to set attribute 'pin_numbers' on 'bpd(15)'.
Note:  Using config. rule 'bpd(14)' to set attribute 'pin_numbers' on 'bpd(14)'.
Note:  Using config. rule 'bpd(13)' to set attribute 'pin_numbers' on 'bpd(13)'.
Note:  Using config. rule 'bpd(12)' to set attribute 'pin_numbers' on 'bpd(12)'.
Note:  Using config. rule 'bpd(11)' to set attribute 'pin_numbers' on 'bpd(11)'.
Note:  Using config. rule 'bpd(10)' to set attribute 'pin_numbers' on 'bpd(10)'.
Note:  Using config. rule 'bpd(9)' to set attribute 'pin_numbers' on 'bpd(9)'.
Note:  Using config. rule 'bpd(8)' to set attribute 'pin_numbers' on 'bpd(8)'.
Note:  Using config. rule 'bpd(7)' to set attribute 'pin_numbers' on 'bpd(7)'.
Note:  Using config. rule 'bpd(6)' to set attribute 'pin_numbers' on 'bpd(6)'.
Note:  Using config. rule 'bpd(5)' to set attribute 'pin_numbers' on 'bpd(5)'.
Note:  Using config. rule 'bpd(4)' to set attribute 'pin_numbers' on 'bpd(4)'.
Note:  Using config. rule 'bpd(3)' to set attribute 'pin_numbers' on 'bpd(3)'.
Note:  Using config. rule 'bpd(2)' to set attribute 'pin_numbers' on 'bpd(2)'.
Note:  Using config. rule 'bpd(1)' to set attribute 'pin_numbers' on 'bpd(1)'.
Note:  Using config. rule 'bpd(0)' to set attribute 'pin_numbers' on 'bpd(0)'.
Note:  Using config. rule 'sw(6)' to set attribute 'pin_numbers' on 'sw(6)'.
Note:  Using config. rule 'sw(5)' to set attribute 'pin_numbers' on 'sw(5)'.
Note:  Using config. rule 'sw(4)' to set attribute 'pin_numbers' on 'sw(4)'.
Note:  Using config. rule 'sw(3)' to set attribute 'pin_numbers' on 'sw(3)'.
Note:  Using config. rule 'sw(2)' to set attribute 'pin_numbers' on 'sw(2)'.
Note:  Using config. rule 'sw(1)' to set attribute 'pin_numbers' on 'sw(1)'.
Note:  Using config. rule 'sw(0)' to set attribute 'pin_numbers' on 'sw(0)'.
pc_remote_bus.vhd (line 837, col 6):  Warning: (W460) 'ao_from_pc_strobe' unassigned in arch. 'tout_arch' of tout.
pc_remote_bus.vhd (line 837, col 6):  Warning: (W460) 'bpctrl(15)' unassigned in arch. 'tout_arch' of tout.
pc_remote_bus.vhd (line 837, col 6):  Warning: (W460) 'bpctrl(14)' unassigned in arch. 'tout_arch' of tout.
pc_remote_bus.vhd (line 837, col 6):  Warning: (W460) 'bpctrl(13)' unassigned in arch. 'tout_arch' of tout.
pc_remote_bus.vhd (line 837, col 6):  Warning: (W460) 'bpctrl(12)' unassigned in arch. 'tout_arch' of tout.
pc_remote_bus.vhd (line 837, col 6):  Warning: (W460) 'bpctrl(9)' unassigned in arch. 'tout_arch' of tout.
pc_remote_bus.vhd (line 837, col 6):  Warning: (W460) 'bpd(9)' unassigned in arch. 'tout_arch' of tout.
pc_remote_bus.vhd (line 837, col 6):  Warning: (W460) 'bpd(8)' unassigned in arch. 'tout_arch' of tout.
pc_remote_bus.vhd (line 837, col 6):  Warning: (W460) 'bpd(7)' unassigned in arch. 'tout_arch' of tout.
pc_remote_bus.vhd (line 837, col 6):  Warning: (W460) 'bpd(6)' unassigned in arch. 'tout_arch' of tout.
pc_remote_bus.vhd (line 837, col 6):  Warning: (W460) 'bpd(5)' unassigned in arch. 'tout_arch' of tout.
pc_remote_bus.vhd (line 837, col 6):  Warning: (W460) 'bpd(4)' unassigned in arch. 'tout_arch' of tout.
pc_remote_bus.vhd (line 837, col 6):  Warning: (W460) 'bpd(3)' unassigned in arch. 'tout_arch' of tout.
pc_remote_bus.vhd (line 837, col 6):  Warning: (W460) 'bpd(2)' unassigned in arch. 'tout_arch' of tout.
pc_remote_bus.vhd (line 837, col 6):  Warning: (W460) 'bpd(1)' unassigned in arch. 'tout_arch' of tout.
pc_remote_bus.vhd (line 837, col 6):  Warning: (W460) 'bpd(0)' unassigned in arch. 'tout_arch' of tout.

tovif:  No errors.  17 warnings.


topld V6.2 IR 27:  Synthesis and optimization
Wed Aug 20 15:40:34 2003

Linking 'C:\Program Files\Cypress\Warp\bin\std.vhd'.
Linking 'C:\Program Files\Cypress\Warp\lib\common\cypress.vhd'.
Linking 'C:\Program Files\Cypress\Warp\lib\common\work\cypress.vif'.
Linking 'C:\Documents and Settings\miket\My Documents\WORK\current_code\pc_remote_bus_rev2.1_reset\pc_remote_bus.ctl'.
Linking 'C:\Program Files\Cypress\Warp\lib\ieee\work\stdlogic.vif'.
Linking 'C:\Program Files\Cypress\Warp\lib\common\stdlogic\lpmpkg.vif'.
Linking 'C:\Program Files\Cypress\Warp\lib\common\stdlogic\rtlpkg.vif'.
Linking 'C:\Program Files\Cypress\Warp\lib\common\stdlogic\mod_cnst.vif'.
Linking 'C:\Program Files\Cypress\Warp\lib\common\stdlogic\mod_mthu.vif'.
Linking 'C:\Program Files\Cypress\Warp\lib\common\stdlogic\mod_mths.vif'.
Linking 'C:\Program Files\Cypress\Warp\lib\common\stdlogic\mod_genu.vif'.
Linking 'C:\Program Files\Cypress\Warp\lib\common\stdlogic\mcompare.vif'.
Note:  Using config. rule 'led1' to set attribute 'pin_numbers' on 'led1'.
Note:  Using config. rule 'led2' to set attribute 'pin_numbers' on 'led2'.
Note:  Using config. rule 'led3' to set attribute 'pin_numbers' on 'led3'.
Note:  Using config. rule 'clk' to set attribute 'pin_numbers' on 'clk'.
Note:  Using config. rule 'fast' to set attribute 'pin_numbers' on 'fast'.
Note:  Using config. rule 'slow' to set attribute 'pin_numbers' on 'slow'.
Note:  Using config. rule 'd(31)' to set attribute 'pin_numbers' on 'd(31)'.
Note:  Using config. rule 'd(30)' to set attribute 'pin_numbers' on 'd(30)'.
Note:  Using config. rule 'd(29)' to set attribute 'pin_numbers' on 'd(29)'.
Note:  Using config. rule 'd(28)' to set attribute 'pin_numbers' on 'd(28)'.
Note:  Using config. rule 'd(27)' to set attribute 'pin_numbers' on 'd(27)'.
Note:  Using config. rule 'd(26)' to set attribute 'pin_numbers' on 'd(26)'.
Note:  Using config. rule 'd(25)' to set attribute 'pin_numbers' on 'd(25)'.
Note:  Using config. rule 'd(24)' to set attribute 'pin_numbers' on 'd(24)'.
Note:  Using config. rule 'd(23)' to set attribute 'pin_numbers' on 'd(23)'.
Note:  Using config. rule 'd(22)' to set attribute 'pin_numbers' on 'd(22)'.
Note:  Using config. rule 'd(21)' to set attribute 'pin_numbers' on 'd(21)'.
Note:  Using config. rule 'd(20)' to set attribute 'pin_numbers' on 'd(20)'.
Note:  Using config. rule 'd(19)' to set attribute 'pin_numbers' on 'd(19)'.
Note:  Using config. rule 'd(18)' to set attribute 'pin_numbers' on 'd(18)'.
Note:  Using config. rule 'd(17)' to set attribute 'pin_numbers' on 'd(17)'.
Note:  Using config. rule 'd(16)' to set attribute 'pin_numbers' on 'd(16)'.
Note:  Using config. rule 'd(15)' to set attribute 'pin_numbers' on 'd(15)'.
Note:  Using config. rule 'd(14)' to set attribute 'pin_numbers' on 'd(14)'.
Note:  Using config. rule 'd(13)' to set attribute 'pin_numbers' on 'd(13)'.
Note:  Using config. rule 'd(12)' to set attribute 'pin_numbers' on 'd(12)'.
Note:  Using config. rule 'd(11)' to set attribute 'pin_numbers' on 'd(11)'.
Note:  Using config. rule 'd(10)' to set attribute 'pin_numbers' on 'd(10)'.
Note:  Using config. rule 'd(9)' to set attribute 'pin_numbers' on 'd(9)'.
Note:  Using config. rule 'd(8)' to set attribute 'pin_numbers' on 'd(8)'.
Note:  Using config. rule 'd(7)' to set attribute 'pin_numbers' on 'd(7)'.
Note:  Using config. rule 'd(6)' to set attribute 'pin_numbers' on 'd(6)'.
Note:  Using config. rule 'd(5)' to set attribute 'pin_numbers' on 'd(5)'.
Note:  Using config. rule 'd(4)' to set attribute 'pin_numbers' on 'd(4)'.
Note:  Using config. rule 'd(3)' to set attribute 'pin_numbers' on 'd(3)'.
Note:  Using config. rule 'd(2)' to set attribute 'pin_numbers' on 'd(2)'.
Note:  Using config. rule 'd(1)' to set attribute 'pin_numbers' on 'd(1)'.
Note:  Using config. rule 'd(0)' to set attribute 'pin_numbers' on 'd(0)'.
Note:  Using config. rule 'reset' to set attribute 'pin_numbers' on 'reset'.
Note:  Using config. rule 'ao_from_pc_strobe' to set attribute 'pin_numbers' on 'ao_from_pc_strobe'.
Note:  Using config. rule 'ao_from_pc_ack' to set attribute 'pin_numbers' on 'ao_from_pc_ack'.
Note:  Using config. rule 'ao_to_pc_strobe' to set attribute 'pin_numbers' on 'ao_to_pc_strobe'.
Note:  Using config. rule 'ao_to_pc_ack' to set attribute 'pin_numbers' on 'ao_to_pc_ack'.
Note:  Using config. rule 'bpaddr(7)' to set attribute 'pin_numbers' on 'bpaddr(7)'.
Note:  Using config. rule 'bpaddr(6)' to set attribute 'pin_numbers' on 'bpaddr(6)'.
Note:  Using config. rule 'bpaddr(5)' to set attribute 'pin_numbers' on 'bpaddr(5)'.
Note:  Using config. rule 'bpaddr(4)' to set attribute 'pin_numbers' on 'bpaddr(4)'.
Note:  Using config. rule 'bpaddr(3)' to set attribute 'pin_numbers' on 'bpaddr(3)'.
Note:  Using config. rule 'bpaddr(2)' to set attribute 'pin_numbers' on 'bpaddr(2)'.
Note:  Using config. rule 'bpaddr(1)' to set attribute 'pin_numbers' on 'bpaddr(1)'.
Note:  Using config. rule 'bpaddr(0)' to set attribute 'pin_numbers' on 'bpaddr(0)'.
Note:  Using config. rule 'bpctrl(15)' to set attribute 'pin_numbers' on 'bpctrl(15)'.
Note:  Using config. rule 'bpctrl(14)' to set attribute 'pin_numbers' on 'bpctrl(14)'.
Note:  Using config. rule 'bpctrl(13)' to set attribute 'pin_numbers' on 'bpctrl(13)'.
Note:  Using config. rule 'bpctrl(12)' to set attribute 'pin_numbers' on 'bpctrl(12)'.
Note:  Using config. rule 'bpctrl(11)' to set attribute 'pin_numbers' on 'bpctrl(11)'.
Note:  Using config. rule 'bpctrl(10)' to set attribute 'pin_numbers' on 'bpctrl(10)'.
Note:  Using config. rule 'bpctrl(9)' to set attribute 'pin_numbers' on 'bpctrl(9)'.
Note:  Using config. rule 'bpctrl(8)' to set attribute 'pin_numbers' on 'bpctrl(8)'.
Note:  Using config. rule 'bpctrl(7)' to set attribute 'pin_numbers' on 'bpctrl(7)'.
Note:  Using config. rule 'bpctrl(6)' to set attribute 'pin_numbers' on 'bpctrl(6)'.
Note:  Using config. rule 'bpctrl(5)' to set attribute 'pin_numbers' on 'bpctrl(5)'.
Note:  Using config. rule 'bpctrl(4)' to set attribute 'pin_numbers' on 'bpctrl(4)'.
Note:  Using config. rule 'bpctrl(3)' to set attribute 'pin_numbers' on 'bpctrl(3)'.
Note:  Using config. rule 'bpctrl(2)' to set attribute 'pin_numbers' on 'bpctrl(2)'.
Note:  Using config. rule 'bpctrl(1)' to set attribute 'pin_numbers' on 'bpctrl(1)'.
Note:  Using config. rule 'bpctrl(0)' to set attribute 'pin_numbers' on 'bpctrl(0)'.
Note:  Using config. rule 'bpd(15)' to set attribute 'pin_numbers' on 'bpd(15)'.
Note:  Using config. rule 'bpd(14)' to set attribute 'pin_numbers' on 'bpd(14)'.
Note:  Using config. rule 'bpd(13)' to set attribute 'pin_numbers' on 'bpd(13)'.
Note:  Using config. rule 'bpd(12)' to set attribute 'pin_numbers' on 'bpd(12)'.
Note:  Using config. rule 'bpd(11)' to set attribute 'pin_numbers' on 'bpd(11)'.
Note:  Using config. rule 'bpd(10)' to set attribute 'pin_numbers' on 'bpd(10)'.
Note:  Using config. rule 'bpd(9)' to set attribute 'pin_numbers' on 'bpd(9)'.
Note:  Using config. rule 'bpd(8)' to set attribute 'pin_numbers' on 'bpd(8)'.
Note:  Using config. rule 'bpd(7)' to set attribute 'pin_numbers' on 'bpd(7)'.
Note:  Using config. rule 'bpd(6)' to set attribute 'pin_numbers' on 'bpd(6)'.
Note:  Using config. rule 'bpd(5)' to set attribute 'pin_numbers' on 'bpd(5)'.
Note:  Using config. rule 'bpd(4)' to set attribute 'pin_numbers' on 'bpd(4)'.
Note:  Using config. rule 'bpd(3)' to set attribute 'pin_numbers' on 'bpd(3)'.
Note:  Using config. rule 'bpd(2)' to set attribute 'pin_numbers' on 'bpd(2)'.
Note:  Using config. rule 'bpd(1)' to set attribute 'pin_numbers' on 'bpd(1)'.
Note:  Using config. rule 'bpd(0)' to set attribute 'pin_numbers' on 'bpd(0)'.
Note:  Using config. rule 'bpd_h_dir' to set attribute 'pin_numbers' on 'bpd_h_dir'.
Note:  Using config. rule 'bpd_h_tristate' to set attribute 'pin_numbers' on 'bpd_h_tristate'.
Note:  Using config. rule 'bpd_l_dir' to set attribute 'pin_numbers' on 'bpd_l_dir'.
Note:  Using config. rule 'bpd_l_tristate' to set attribute 'pin_numbers' on 'bpd_l_tristate'.
Note:  Using config. rule 'bpaddr_dir' to set attribute 'pin_numbers' on 'bpaddr_dir'.
Note:  Using config. rule 'bpaddr_tristate' to set attribute 'pin_numbers' on 'bpaddr_tristate'.
Note:  Using config. rule 'bpctrl_h_dir' to set attribute 'pin_numbers' on 'bpctrl_h_dir'.
Note:  Using config. rule 'bpctrl_l_dir' to set attribute 'pin_numbers' on 'bpctrl_l_dir'.
Note:  Using config. rule 'bpctrl_h_tristate' to set attribute 'pin_numbers' on 'bpctrl_h_tristate'.
Note:  Using config. rule 'bpctrl_l_tristate' to set attribute 'pin_numbers' on 'bpctrl_l_tristate'.
Note:  Using config. rule 'sw(6)' to set attribute 'pin_numbers' on 'sw(6)'.
Note:  Using config. rule 'sw(5)' to set attribute 'pin_numbers' on 'sw(5)'.
Note:  Using config. rule 'sw(4)' to set attribute 'pin_numbers' on 'sw(4)'.
Note:  Using config. rule 'sw(3)' to set attribute 'pin_numbers' on 'sw(3)'.
Note:  Using config. rule 'sw(2)' to set attribute 'pin_numbers' on 'sw(2)'.
Note:  Using config. rule 'sw(1)' to set attribute 'pin_numbers' on 'sw(1)'.
Note:  Using config. rule 'sw(0)' to set attribute 'pin_numbers' on 'sw(0)'.
Note:  Using config. rule 'sinphase_zeros' to set attribute 'pin_numbers' on 'sinphase_zeros'.
Note:  Using config. rule 'hva_chassis_en_l' to set attribute 'pin_numbers' on 'hva_chassis_en_l'.
Linking 'C:\Program Files\Cypress\Warp\lib\lc370\stdlogic\c370.vif'.
State variable 'tristate_state' is represented by a Bit_vector (0 to 0).
State encoding (sequential) for 'tristate_state' is:
	idle :=	b"0";
	active :=	b"1";
State variable 'iu_write' is represented by a Bit_vector (0 to 1).
State encoding (sequential) for 'iu_write' is:
	idle :=	b"00";
	hs :=	b"01";
	iu_hs1 :=	b"10";
	iu_hs2 :=	b"11";
State variable 'il_read_state' is represented by a Bit_vector (0 to 2).
State encoding (sequential) for 'il_read_state' is:
	idle :=	b"000";
	am_i_addressed :=	b"001";
	il_hs_for_address :=	b"010";
	il_hs_for_data :=	b"011";
	il_use_ctrl_data :=	b"100";
	internal_ack1 :=	b"101";
	internal_ack2 :=	b"110";
State variable 'bp_access_state' is represented by a Bit_vector (0 to 2).
State encoding (sequential) for 'bp_access_state' is:
	idle :=	b"000";
	write_wait :=	b"001";
	write_settle :=	b"010";
	write_strobe :=	b"011";
	write_ack :=	b"100";
	read_from_bp :=	b"101";
	read_strobe :=	b"110";
	read_ack :=	b"111";
State variable 'counter_read_state' is represented by a Bit_vector (0 to 3).
State encoding (sequential) for 'counter_read_state' is:
	idle :=	b"0000";
	valid_address :=	b"0001";
	increment_address :=	b"0010";
	test_end :=	b"0011";
	start_fetch :=	b"0100";
	complete_fetch :=	b"0101";
	transfer_to_pc :=	b"0110";
	complete_pc_transfer :=	b"0111";
	do_reset_counters :=	b"1000";
Note:  Using config. rule 'clk' to set attribute 'pin_numbers' on 'clk'.
Note:  Using config. rule 'clk' to set attribute 'pin_numbers' on 'clk'.

----------------------------------------------------------
Detecting unused logic.
----------------------------------------------------------
    User names
	soft_request_reset
	\sp_read:delay_count_9\
	\sp_read:delay_count_8\
	\sp_read:delay_count_7\
	\sp_read:delay_count_6\
	\sp_read:delay_count_5\
	\sp_read:delay_count_4\
	\sp_read:delay_count_3\
	\sp_read:delay_count_2\
	\sp_read:delay_count_1\
	\sp_read:delay_count_0\


Deleted 11 User equations/components.
Deleted 69 Synthesized equations/components.

------------------------------------------------------
Alias Detection
------------------------------------------------------

------------------------------------------------------
Aliased 0 equations, 394 wires.
------------------------------------------------------

----------------------------------------------------------
Circuit simplification
----------------------------------------------------------
Note:  Virtual signal \sp_read:cmp_vv_us_MODGEN_10\ with ( cost: 1073741824 or cost_inv: 1073741824)  > 30000 or with size: 256 > 256 has been made a (soft) node.

----------------------------------------------------------
Circuit simplification results:

	Expanded 101 signals.
	Turned 1 signals into soft nodes.
	Maximum default expansion cost was set at 10.
----------------------------------------------------------

------------------------------------------------------
Alias Detection
------------------------------------------------------

------------------------------------------------------
Aliased 0 equations, 0 wires.
------------------------------------------------------
Created 961 PLD nodes.

topld:  No errors.

----------------------------------------------------------------------------
PLD Optimizer Software:       DSGNOPT.EXE    31/03/2000  [v4.02 ] 6.2 IR 27

DESIGN HEADER INFORMATION  (15:40:38)

Input File(s): pc_remote_bus.pla
Device       : cy37256p160
Package      : cy37256p160-125ac
ReportFile   : pc_remote_bus.rpt

Program Controls:
    COMMAND LANGUAGE_VHDL 
    COMMAND UserCode 0000000000000000 
    COMMAND PROPERTY BUS_HOLD ENABLE 

Signal Requests:
    GROUP DT-OPT ALL
    GROUP USEPOL ALL
    GROUP FAST_SLEW ALL
    GROUP SOFT \sp_read:cmp_vv_us_MODGEN_10\ 

Completed Successfully  
----------------------------------------------------------------------------
PLD Optimizer Software:       DSGNOPT.EXE    31/03/2000  [v4.02 ] 6.2 IR 27

OPTIMIZATION OPTIONS       (15:40:38)

Messages:
  Information: Process virtual '\sp_read:cmp_vv_us_MODGEN_10\' ... converted to NODE.
  Information: Process virtual '\sp_read:counter_address_0\\D\'\sp_read:counter_address_0\\D\ ... expanded.
  Information: Process virtual '\sp_read:counter_address_1\\D\'\sp_read:counter_address_1\\D\ ... expanded.
  Information: Process virtual '\sp_read:counter_address_2\\D\'\sp_read:counter_address_2\\D\ ... expanded.
  Information: Process virtual '\sp_read:counter_address_3\\D\'\sp_read:counter_address_3\\D\ ... expanded.
  Information: Process virtual '\sp_read:counter_address_4\\D\'\sp_read:counter_address_4\\D\ ... expanded.
  Information: Process virtual '\sp_read:counter_address_5\\D\'\sp_read:counter_address_5\\D\ ... expanded.
  Information: Process virtual '\sp_read:counter_address_6\\D\'\sp_read:counter_address_6\\D\ ... expanded.
  Information: Process virtual '\sp_read:counter_address_7\\D\'\sp_read:counter_address_7\\D\ ... expanded.
  Information: Process virtual '\sp_read:reset_count_0\\D\'\sp_read:reset_count_0\\D\ ... expanded.
  Information: Process virtual '\sp_read:reset_count_1\\D\'\sp_read:reset_count_1\\D\ ... expanded.
  Information: Process virtual '\sp_read:reset_count_2\\D\'\sp_read:reset_count_2\\D\ ... expanded.
  Information: Process virtual '\sp_read:counter_read_stateSBV_3\\D\'\sp_read:counter_read_stateSBV_3\\D\ ... expanded.
  Information: Process virtual '\sp_read:counter_read_stateSBV_2\\D\'\sp_read:counter_read_stateSBV_2\\D\ ... expanded.
  Information: Process virtual '\sp_read:counter_read_stateSBV_1\\D\'\sp_read:counter_read_stateSBV_1\\D\ ... expanded.
  Information: Process virtual '\sp_read:counter_read_stateSBV_0\\D\'\sp_read:counter_read_stateSBV_0\\D\ ... expanded.
  Information: Process virtual 'sensor_address_0D'sensor_address_0D ... expanded.
  Information: Process virtual 'sensor_address_1D'sensor_address_1D ... expanded.
  Information: Process virtual 'sensor_address_2D'sensor_address_2D ... expanded.
  Information: Process virtual 'sensor_address_3D'sensor_address_3D ... expanded.
  Information: Process virtual 'sensor_address_4D'sensor_address_4D ... expanded.
  Information: Process virtual 'sensor_address_5D'sensor_address_5D ... expanded.
  Information: Process virtual 'sensor_address_6D'sensor_address_6D ... expanded.
  Information: Process virtual 'sensor_address_7D'sensor_address_7D ... expanded.
  Information: Process virtual '\bp_io:timeout_0\\D\'\bp_io:timeout_0\\D\ ... expanded.
  Information: Process virtual '\bp_io:timeout_1\\D\'\bp_io:timeout_1\\D\ ... expanded.
  Information: Process virtual '\bp_io:timeout_2\\D\'\bp_io:timeout_2\\D\ ... expanded.
  Information: Process virtual 'bp_addr_tristateD'bp_addr_tristateD ... expanded.
  Information: Process virtual 'bp_data_tristateD'bp_data_tristateD ... expanded.
  Information: Process virtual 'sensor_to_bp_read_ackD'sensor_to_bp_read_ackD ... expanded.
  Information: Process virtual '\bp_io:bp_access_stateSBV_2\\D\'\bp_io:bp_access_stateSBV_2\\D\ ... expanded.
  Information: Process virtual '\bp_io:bp_access_stateSBV_1\\D\'\bp_io:bp_access_stateSBV_1\\D\ ... expanded.
  Information: Process virtual '\bp_io:bp_access_stateSBV_0\\D\'\bp_io:bp_access_stateSBV_0\\D\ ... expanded.
  Information: Process virtual 'bp_end_address_7D'bp_end_address_7D ... expanded.
  Information: Process virtual 'bp_start_address_7D'bp_start_address_7D ... expanded.
  Information: Process virtual 'bp_end_address_6D'bp_end_address_6D ... expanded.
  Information: Process virtual 'bp_start_address_6D'bp_start_address_6D ... expanded.
  Information: Process virtual 'bp_end_address_5D'bp_end_address_5D ... expanded.
  Information: Process virtual 'bp_start_address_5D'bp_start_address_5D ... expanded.
  Information: Process virtual 'bp_end_address_4D'bp_end_address_4D ... expanded.
  Information: Process virtual 'bp_start_address_4D'bp_start_address_4D ... expanded.
  Information: Process virtual 'bp_end_address_3D'bp_end_address_3D ... expanded.
  Information: Process virtual 'bp_start_address_3D'bp_start_address_3D ... expanded.
  Information: Process virtual 'bp_end_address_2D'bp_end_address_2D ... expanded.
  Information: Process virtual 'bp_start_address_2D'bp_start_address_2D ... expanded.
  Information: Process virtual 'bp_end_address_1D'bp_end_address_1D ... expanded.
  Information: Process virtual 'bp_start_address_1D'bp_start_address_1D ... expanded.
  Information: Process virtual 'bp_end_address_0D'bp_end_address_0D ... expanded.
  Information: Process virtual 'bp_start_address_0D'bp_start_address_0D ... expanded.
  Information: Process virtual 'address_from_pc_0D'address_from_pc_0D ... expanded.
  Information: Process virtual 'address_from_pc_1D'address_from_pc_1D ... expanded.
  Information: Process virtual 'address_from_pc_2D'address_from_pc_2D ... expanded.
  Information: Process virtual 'address_from_pc_3D'address_from_pc_3D ... expanded.
  Information: Process virtual 'address_from_pc_4D'address_from_pc_4D ... expanded.
  Information: Process virtual 'address_from_pc_5D'address_from_pc_5D ... expanded.
  Information: Process virtual 'address_from_pc_6D'address_from_pc_6D ... expanded.
  Information: Process virtual 'address_from_pc_7D'address_from_pc_7D ... expanded.
  Information: Process virtual '\ibus_reader:timeout_0\\D\'\ibus_reader:timeout_0\\D\ ... expanded.
  Information: Process virtual '\ibus_reader:timeout_1\\D\'\ibus_reader:timeout_1\\D\ ... expanded.
  Information: Process virtual '\ibus_reader:timeout_2\\D\'\ibus_reader:timeout_2\\D\ ... expanded.
  Information: Process virtual '\ibus_reader:timeout_3\\D\'\ibus_reader:timeout_3\\D\ ... expanded.
  Information: Process virtual '\ibus_reader:this_is_a_ctrl_transaction\\D\'\ibus_reader:this_is_a_ctrl_transaction\\D\ ... expanded.
  Information: Process virtual '\ibus_reader:il_read_stateSBV_2\\D\'\ibus_reader:il_read_stateSBV_2\\D\ ... expanded.
  Information: Process virtual '\ibus_reader:il_read_stateSBV_1\\D\'\ibus_reader:il_read_stateSBV_1\\D\ ... expanded.
  Information: Process virtual '\ibus_reader:il_read_stateSBV_0\\D\'\ibus_reader:il_read_stateSBV_0\\D\ ... expanded.
  Information: Process virtual '\ibus_writer:timeout_0\\D\'\ibus_writer:timeout_0\\D\ ... expanded.
  Information: Process virtual '\ibus_writer:timeout_1\\D\'\ibus_writer:timeout_1\\D\ ... expanded.
  Information: Process virtual '\ibus_writer:timeout_2\\D\'\ibus_writer:timeout_2\\D\ ... expanded.
  Information: Process virtual '\ibus_writer:timeout_3\\D\'\ibus_writer:timeout_3\\D\ ... expanded.
  Information: Process virtual '\ibus_writer:iu_writeSBV_1\\D\'\ibus_writer:iu_writeSBV_1\\D\ ... expanded.
  Information: Process virtual '\ibus_writer:iu_writeSBV_0\\D\'\ibus_writer:iu_writeSBV_0\\D\ ... expanded.
  Information: Process virtual 'sensor_data_0D'sensor_data_0D ... expanded.
  Information: Process virtual 'data_from_pc_0D'data_from_pc_0D ... expanded.
  Information: Process virtual 'sensor_data_1D'sensor_data_1D ... expanded.
  Information: Process virtual 'data_from_pc_1D'data_from_pc_1D ... expanded.
  Information: Process virtual 'sensor_data_2D'sensor_data_2D ... expanded.
  Information: Process virtual 'data_from_pc_2D'data_from_pc_2D ... expanded.
  Information: Process virtual 'sensor_data_3D'sensor_data_3D ... expanded.
  Information: Process virtual 'data_from_pc_3D'data_from_pc_3D ... expanded.
  Information: Process virtual 'sensor_data_4D'sensor_data_4D ... expanded.
  Information: Process virtual 'data_from_pc_4D'data_from_pc_4D ... expanded.
  Information: Process virtual 'sensor_data_5D'sensor_data_5D ... expanded.
  Information: Process virtual 'data_from_pc_5D'data_from_pc_5D ... expanded.
  Information: Process virtual 'sensor_data_6D'sensor_data_6D ... expanded.
  Information: Process virtual 'data_from_pc_6D'data_from_pc_6D ... expanded.
  Information: Process virtual 'sensor_data_7D'sensor_data_7D ... expanded.
  Information: Process virtual 'data_from_pc_7D'data_from_pc_7D ... expanded.
  Information: Process virtual 'sensor_data_8D'sensor_data_8D ... expanded.
  Information: Process virtual 'data_from_pc_8D'data_from_pc_8D ... expanded.
  Information: Process virtual 'sensor_data_9D'sensor_data_9D ... expanded.
  Information: Process virtual 'data_from_pc_9D'data_from_pc_9D ... expanded.
  Information: Process virtual 'sensor_data_10D'sensor_data_10D ... expanded.
  Information: Process virtual 'data_from_pc_10D'data_from_pc_10D ... expanded.
  Information: Process virtual 'sensor_data_11D'sensor_data_11D ... expanded.
  Information: Process virtual 'data_from_pc_11D'data_from_pc_11D ... expanded.
  Information: Process virtual 'sensor_data_12D'sensor_data_12D ... expanded.
  Information: Process virtual 'data_from_pc_12D'data_from_pc_12D ... expanded.
  Information: Process virtual 'sensor_data_13D'sensor_data_13D ... expanded.
  Information: Process virtual 'data_from_pc_13D'data_from_pc_13D ... expanded.
  Information: Process virtual 'sensor_data_14D'sensor_data_14D ... expanded.
  Information: Process virtual 'data_from_pc_14D'data_from_pc_14D ... expanded.
  Information: Process virtual 'sensor_data_15D'sensor_data_15D ... expanded.
  Information: Process virtual 'data_from_pc_15D'data_from_pc_15D ... expanded.
  Information: Process virtual 'sensor_to_ibus_reqD'sensor_to_ibus_reqD ... expanded.
  Information: Process virtual 'from_pc_reqD'from_pc_reqD ... expanded.
  Information: Process virtual 'write_to_bp_ackD'write_to_bp_ackD ... expanded.
  Information: Process virtual 'to_pc_ackD'to_pc_ackD ... expanded.
  Information: Process virtual 'loopback_stateD'loopback_stateD ... expanded.
  Information: Process virtual 'il_ackD'il_ackD ... expanded.
  Information: Process virtual 'il_tristateD'il_tristateD ... expanded.
  Information: Process virtual 'this_chip_selectedD'this_chip_selectedD ... expanded.
  Information: Process virtual '\bpctrl(0)D\'\bpctrl(0)D\ ... expanded.
  Information: Process virtual '\bpctrl(2)D\'\bpctrl(2)D\ ... expanded.
  Information: Process virtual '\bpctrl(3)D\'\bpctrl(3)D\ ... expanded.
  Information: Process virtual '\bpaddr(0)D\'\bpaddr(0)D\ ... expanded.
  Information: Process virtual '\bpaddr(1)D\'\bpaddr(1)D\ ... expanded.
  Information: Process virtual '\bpaddr(2)D\'\bpaddr(2)D\ ... expanded.
  Information: Process virtual '\bpaddr(3)D\'\bpaddr(3)D\ ... expanded.
  Information: Process virtual '\bpaddr(4)D\'\bpaddr(4)D\ ... expanded.
  Information: Process virtual '\bpaddr(5)D\'\bpaddr(5)D\ ... expanded.
  Information: Process virtual '\bpaddr(6)D\'\bpaddr(6)D\ ... expanded.
  Information: Process virtual '\bpaddr(7)D\'\bpaddr(7)D\ ... expanded.
  Information: Process virtual 'ao_to_pc_strobeD'ao_to_pc_strobeD ... expanded.
  Information: Process virtual '\d(16)D\'\d(16)D\ ... expanded.
  Information: Process virtual '\d(17)D\'\d(17)D\ ... expanded.
  Information: Process virtual '\d(18)D\'\d(18)D\ ... expanded.
  Information: Process virtual '\d(19)D\'\d(19)D\ ... expanded.
  Information: Process virtual '\d(20)D\'\d(20)D\ ... expanded.
  Information: Process virtual '\d(21)D\'\d(21)D\ ... expanded.
  Information: Process virtual '\d(22)D\'\d(22)D\ ... expanded.
  Information: Process virtual '\d(23)D\'\d(23)D\ ... expanded.
  Information: Process virtual '\d(24)D\'\d(24)D\ ... expanded.
  Information: Process virtual '\d(25)D\'\d(25)D\ ... expanded.
  Information: Process virtual '\d(26)D\'\d(26)D\ ... expanded.
  Information: Process virtual '\d(27)D\'\d(27)D\ ... expanded.
  Information: Process virtual '\d(28)D\'\d(28)D\ ... expanded.
  Information: Process virtual '\d(29)D\'\d(29)D\ ... expanded.
  Information: Process virtual '\d(30)D\'\d(30)D\ ... expanded.
  Information: Process virtual '\d(31)D\'\d(31)D\ ... expanded.
  Information: Process virtual 'led1D'led1D ... expanded.
  Information: Process virtual '\sp_read:old_phase\\S\'\sp_read:old_phase\\S\ ... expanded.
  Information: Process virtual '\sp_read:old_phase\\R\'\sp_read:old_phase\\R\ ... expanded.
  Information: Process virtual '\sp_read:counter_address_0\' ... converted to NODE.
  Information: Process virtual '\sp_read:counter_address_1\' ... converted to NODE.
  Information: Process virtual '\sp_read:counter_address_2\' ... converted to NODE.
  Information: Process virtual '\sp_read:counter_address_3\' ... converted to NODE.
  Information: Process virtual '\sp_read:counter_address_4\' ... converted to NODE.
  Information: Process virtual '\sp_read:counter_address_5\' ... converted to NODE.
  Information: Process virtual '\sp_read:counter_address_6\' ... converted to NODE.
  Information: Process virtual '\sp_read:counter_address_7\' ... converted to NODE.
  Information: Process virtual '\sp_read:reset_count_0\' ... converted to NODE.
  Information: Process virtual '\sp_read:reset_count_1\' ... converted to NODE.
  Information: Process virtual '\sp_read:reset_count_2\' ... converted to NODE.
  Information: Process virtual '\sp_read:old_phase\' ... converted to NODE.
  Information: Process virtual '\sp_read:counter_read_stateSBV_3\' ... converted to NODE.
  Information: Process virtual '\sp_read:counter_read_stateSBV_2\' ... converted to NODE.
  Information: Process virtual '\sp_read:counter_read_stateSBV_1\' ... converted to NODE.
  Information: Process virtual '\sp_read:counter_read_stateSBV_0\' ... converted to NODE.
  Information: Process virtual 'sensor_address_0' ... converted to NODE.
  Information: Process virtual 'sensor_address_1' ... converted to NODE.
  Information: Process virtual 'sensor_address_2' ... converted to NODE.
  Information: Process virtual 'sensor_address_3' ... converted to NODE.
  Information: Process virtual 'sensor_address_4' ... converted to NODE.
  Information: Process virtual 'sensor_address_5' ... converted to NODE.
  Information: Process virtual 'sensor_address_6' ... converted to NODE.
  Information: Process virtual 'sensor_address_7' ... converted to NODE.
  Information: Process virtual '\bp_io:timeout_0\' ... converted to NODE.
  Information: Process virtual '\bp_io:timeout_1\' ... converted to NODE.
  Information: Process virtual '\bp_io:timeout_2\' ... converted to NODE.
  Information: Process virtual 'bp_addr_tristate'bp_addr_tristate ... expanded.
  Information: Process virtual 'sensor_to_bp_read_req' ... converted to NODE.
  Information: Process virtual 'bp_data_tristate'bp_data_tristate ... expanded.
  Information: Process virtual 'sensor_to_bp_read_ack' ... converted to NODE.
  Information: Process virtual '\bp_io:bp_access_stateSBV_2\' ... converted to NODE.
  Information: Process virtual '\bp_io:bp_access_stateSBV_1\' ... converted to NODE.
  Information: Process virtual '\bp_io:bp_access_stateSBV_0\' ... converted to NODE.
  Information: Process virtual 'bp_end_address_7' ... converted to NODE.
  Information: Process virtual 'bp_start_address_7' ... converted to NODE.
  Information: Process virtual 'bp_end_address_6' ... converted to NODE.
  Information: Process virtual 'bp_start_address_6' ... converted to NODE.
  Information: Process virtual 'bp_end_address_5' ... converted to NODE.
  Information: Process virtual 'bp_start_address_5' ... converted to NODE.
  Information: Process virtual 'bp_end_address_4' ... converted to NODE.
  Information: Process virtual 'bp_start_address_4' ... converted to NODE.
  Information: Process virtual 'bp_end_address_3' ... converted to NODE.
  Information: Process virtual 'bp_start_address_3' ... converted to NODE.
  Information: Process virtual 'bp_end_address_2' ... converted to NODE.
  Information: Process virtual 'bp_start_address_2' ... converted to NODE.
  Information: Process virtual 'bp_end_address_1' ... converted to NODE.
  Information: Process virtual 'bp_start_address_1' ... converted to NODE.
  Information: Process virtual 'bp_end_address_0' ... converted to NODE.
  Information: Process virtual 'bp_start_address_0' ... converted to NODE.
  Information: Process virtual 'address_from_pc_0' ... converted to NODE.
  Information: Process virtual 'address_from_pc_1' ... converted to NODE.
  Information: Process virtual 'address_from_pc_2' ... converted to NODE.
  Information: Process virtual 'address_from_pc_3' ... converted to NODE.
  Information: Process virtual 'address_from_pc_4' ... converted to NODE.
  Information: Process virtual 'address_from_pc_5' ... converted to NODE.
  Information: Process virtual 'address_from_pc_6' ... converted to NODE.
  Information: Process virtual 'address_from_pc_7' ... converted to NODE.
  Information: Process virtual '\ibus_reader:timeout_0\' ... converted to NODE.
  Information: Process virtual '\ibus_reader:timeout_1\' ... converted to NODE.
  Information: Process virtual '\ibus_reader:timeout_2\' ... converted to NODE.
  Information: Process virtual '\ibus_reader:timeout_3\' ... converted to NODE.
  Information: Process virtual '\ibus_reader:this_is_a_ctrl_transaction\' ... converted to NODE.
  Information: Process virtual '\ibus_reader:il_read_stateSBV_2\' ... converted to NODE.
  Information: Process virtual '\ibus_reader:il_read_stateSBV_1\' ... converted to NODE.
  Information: Process virtual '\ibus_reader:il_read_stateSBV_0\' ... converted to NODE.
  Information: Process virtual '\ibus_writer:timeout_0\' ... converted to NODE.
  Information: Process virtual '\ibus_writer:timeout_1\' ... converted to NODE.
  Information: Process virtual '\ibus_writer:timeout_2\' ... converted to NODE.
  Information: Process virtual '\ibus_writer:timeout_3\' ... converted to NODE.
  Information: Process virtual '\ibus_writer:iu_writeSBV_1\' ... converted to NODE.
  Information: Process virtual '\ibus_writer:iu_writeSBV_0\' ... converted to NODE.
  Information: Process virtual 'sensor_data_0' ... converted to NODE.
  Information: Process virtual 'data_from_pc_0'data_from_pc_0 ... expanded.
  Information: Process virtual 'sensor_data_1' ... converted to NODE.
  Information: Process virtual 'data_from_pc_1'data_from_pc_1 ... expanded.
  Information: Process virtual 'sensor_data_2' ... converted to NODE.
  Information: Process virtual 'data_from_pc_2'data_from_pc_2 ... expanded.
  Information: Process virtual 'sensor_data_3' ... converted to NODE.
  Information: Process virtual 'data_from_pc_3'data_from_pc_3 ... expanded.
  Information: Process virtual 'sensor_data_4' ... converted to NODE.
  Information: Process virtual 'data_from_pc_4'data_from_pc_4 ... expanded.
  Information: Process virtual 'sensor_data_5' ... converted to NODE.
  Information: Process virtual 'data_from_pc_5'data_from_pc_5 ... expanded.
  Information: Process virtual 'sensor_data_6' ... converted to NODE.
  Information: Process virtual 'data_from_pc_6'data_from_pc_6 ... expanded.
  Information: Process virtual 'sensor_data_7' ... converted to NODE.
  Information: Process virtual 'data_from_pc_7'data_from_pc_7 ... expanded.
  Information: Process virtual 'sensor_data_8' ... converted to NODE.
  Information: Process virtual 'data_from_pc_8'data_from_pc_8 ... expanded.
  Information: Process virtual 'sensor_data_9' ... converted to NODE.
  Information: Process virtual 'data_from_pc_9'data_from_pc_9 ... expanded.
  Information: Process virtual 'sensor_data_10' ... converted to NODE.
  Information: Process virtual 'data_from_pc_10'data_from_pc_10 ... expanded.
  Information: Process virtual 'sensor_data_11' ... converted to NODE.
  Information: Process virtual 'data_from_pc_11'data_from_pc_11 ... expanded.
  Information: Process virtual 'sensor_data_12' ... converted to NODE.
  Information: Process virtual 'data_from_pc_12'data_from_pc_12 ... expanded.
  Information: Process virtual 'sensor_data_13' ... converted to NODE.
  Information: Process virtual 'data_from_pc_13' ... converted to NODE.
  Information: Process virtual 'sensor_data_14' ... converted to NODE.
  Information: Process virtual 'data_from_pc_14' ... converted to NODE.
  Information: Process virtual 'sensor_data_15' ... converted to NODE.
  Information: Process virtual 'data_from_pc_15' ... converted to NODE.
  Information: Process virtual 'sensor_to_ibus_req' ... converted to NODE.
  Information: Process virtual 'from_pc_req' ... converted to NODE.
  Information: Process virtual 'write_to_bp_ack' ... converted to NODE.
  Information: Process virtual 'to_pc_ack' ... converted to NODE.
  Information: Process virtual 'loopback_state' ... converted to NODE.
  Information: Process virtual 'il_tristate' ... converted to NODE.
  Information: Process virtual 'this_chip_selected' ... converted to NODE.
  Information: Process virtual 'tristate_stateSBV_0' ... converted to NODE.
  Information: Process virtual 'sensor_to_bp_read_reqD'sensor_to_bp_read_reqD ... expanded.
  Information: Generating both D & T register equations for signal bpctrl(0).D[11]
  Information: Expanding XOR equation found on signal bpctrl(0).T[11]
  Information: Generating both D & T register equations for signal bpctrl(2).D[13]
  Information: Expanding XOR equation found on signal bpctrl(2).T[13]
  Information: Generating both D & T register equations for signal bpctrl(3).D[14]
  Information: Expanding XOR equation found on signal bpctrl(3).T[14]
  Information: Generating both D & T register equations for signal bpctrl(4).D[15]
  Information: Expanding XOR equation found on signal bpctrl(4).T[15]
  Information: Generating both D & T register equations for signal bpctrl(5).D[16]
  Information: Expanding XOR equation found on signal bpctrl(5).T[16]
  Information: Generating both D & T register equations for signal bpctrl(6).D[17]
  Information: Expanding XOR equation found on signal bpctrl(6).T[17]
  Information: Generating both D & T register equations for signal bpctrl(7).D[18]
  Information: Expanding XOR equation found on signal bpctrl(7).T[18]
  Information: Generating both D & T register equations for signal bpctrl(8).D[23]
  Information: Expanding XOR equation found on signal bpctrl(8).T[23]
  Information: Generating both D & T register equations for signal bpctrl(10).D[25]
  Information: Expanding XOR equation found on signal bpctrl(10).T[25]
  Information: Generating both D & T register equations for signal bpctrl(11).D[26]
  Information: Expanding XOR equation found on signal bpctrl(11).T[26]
  Information: Generating both D & T register equations for signal bpaddr(0).D[32]
  Information: Expanding XOR equation found on signal bpaddr(0).T[32]
  Information: Generating both D & T register equations for signal bpaddr(1).D[33]
  Information: Expanding XOR equation found on signal bpaddr(1).T[33]
  Information: Generating both D & T register equations for signal bpaddr(2).D[34]
  Information: Expanding XOR equation found on signal bpaddr(2).T[34]
  Information: Generating both D & T register equations for signal bpaddr(3).D[35]
  Information: Expanding XOR equation found on signal bpaddr(3).T[35]
  Information: Generating both D & T register equations for signal bpaddr(4).D[36]
  Information: Expanding XOR equation found on signal bpaddr(4).T[36]
  Information: Generating both D & T register equations for signal bpaddr(5).D[37]
  Information: Expanding XOR equation found on signal bpaddr(5).T[37]
  Information: Generating both D & T register equations for signal bpaddr(6).D[38]
  Information: Expanding XOR equation found on signal bpaddr(6).T[38]
  Information: Generating both D & T register equations for signal bpaddr(7).D[39]
  Information: Expanding XOR equation found on signal bpaddr(7).T[39]
  Information: Generating both D & T register equations for signal bpd_h_tristate.D[43]
  Information: Expanding XOR equation found on signal bpd_h_tristate.T[43]
  Information: Generating both D & T register equations for signal bpaddr_tristate.D[44]
  Information: Expanding XOR equation found on signal bpaddr_tristate.T[44]
  Information: Generating both D & T register equations for signal led1.D[47]
  Information: Expanding XOR equation found on signal led1.T[47]
  Information: Generating both D & T register equations for signal ao_to_pc_strobe.D[93]
  Information: Expanding XOR equation found on signal ao_to_pc_strobe.T[93]
  Information: Generating both D & T register equations for signal ao_from_pc_ack.D[94]
  Information: Expanding XOR equation found on signal ao_from_pc_ack.T[94]
  Information: Generating both D & T register equations for signal d(16).D[122]
  Information: Expanding XOR equation found on signal d(16).T[122]
  Information: Generating both D & T register equations for signal d(17).D[123]
  Information: Expanding XOR equation found on signal d(17).T[123]
  Information: Generating both D & T register equations for signal d(18).D[124]
  Information: Expanding XOR equation found on signal d(18).T[124]
  Information: Generating both D & T register equations for signal d(19).D[125]
  Information: Expanding XOR equation found on signal d(19).T[125]
  Information: Generating both D & T register equations for signal d(20).D[126]
  Information: Expanding XOR equation found on signal d(20).T[126]
  Information: Generating both D & T register equations for signal d(21).D[127]
  Information: Expanding XOR equation found on signal d(21).T[127]
  Information: Generating both D & T register equations for signal d(22).D[128]
  Information: Expanding XOR equation found on signal d(22).T[128]
  Information: Generating both D & T register equations for signal d(23).D[129]
  Information: Expanding XOR equation found on signal d(23).T[129]
  Information: Generating both D & T register equations for signal d(24).D[131]
  Information: Expanding XOR equation found on signal d(24).T[131]
  Information: Generating both D & T register equations for signal d(25).D[132]
  Information: Expanding XOR equation found on signal d(25).T[132]
  Information: Generating both D & T register equations for signal d(26).D[133]
  Information: Expanding XOR equation found on signal d(26).T[133]
  Information: Generating both D & T register equations for signal d(27).D[134]
  Information: Expanding XOR equation found on signal d(27).T[134]
  Information: Generating both D & T register equations for signal d(28).D[135]
  Information: Expanding XOR equation found on signal d(28).T[135]
  Information: Generating both D & T register equations for signal d(29).D[136]
  Information: Expanding XOR equation found on signal d(29).T[136]
  Information: Generating both D & T register equations for signal d(30).D[137]
  Information: Expanding XOR equation found on signal d(30).T[137]
  Information: Generating both D & T register equations for signal d(31).D[138]
  Information: Expanding XOR equation found on signal d(31).T[138]
  Information: Generating both D & T register equations for signal bpd(10).D[154]
  Information: Expanding XOR equation found on signal bpd(10).T[154]
  Information: Generating both D & T register equations for signal bpd(11).D[155]
  Information: Expanding XOR equation found on signal bpd(11).T[155]
  Information: Generating both D & T register equations for signal bpd(12).D[156]
  Information: Expanding XOR equation found on signal bpd(12).T[156]
  Information: Generating both D & T register equations for signal bpd(13).D[157]
  Information: Expanding XOR equation found on signal bpd(13).T[157]
  Information: Generating both D & T register equations for signal bpd(14).D[158]
  Information: Expanding XOR equation found on signal bpd(14).T[158]
  Information: Generating both D & T register equations for signal bpd(15).D[159]
  Information: Expanding XOR equation found on signal bpd(15).T[159]
  Information: Generating both D & T register equations for signal \sp_read:counter_address_0\.D
  Information: Expanding XOR equation found on signal \sp_read:counter_address_0\.T
  Information: Generating both D & T register equations for signal \sp_read:counter_address_1\.D
  Information: Expanding XOR equation found on signal \sp_read:counter_address_1\.T
  Information: Generating both D & T register equations for signal \sp_read:counter_address_2\.D
  Information: Expanding XOR equation found on signal \sp_read:counter_address_2\.T
  Information: Generating both D & T register equations for signal \sp_read:counter_address_3\.D
  Information: Expanding XOR equation found on signal \sp_read:counter_address_3\.T
  Information: Generating both D & T register equations for signal \sp_read:counter_address_4\.D
  Information: Expanding XOR equation found on signal \sp_read:counter_address_4\.T
  Information: Generating both D & T register equations for signal \sp_read:counter_address_5\.D
  Information: Expanding XOR equation found on signal \sp_read:counter_address_5\.T
  Information: Generating both D & T register equations for signal \sp_read:counter_address_6\.D
  Information: Expanding XOR equation found on signal \sp_read:counter_address_6\.T
  Information: Generating both D & T register equations for signal \sp_read:counter_address_7\.D
  Information: Expanding XOR equation found on signal \sp_read:counter_address_7\.T
  Information: Generating both D & T register equations for signal \sp_read:reset_count_0\.D
  Information: Expanding XOR equation found on signal \sp_read:reset_count_0\.T
  Information: Generating both D & T register equations for signal \sp_read:reset_count_1\.D
  Information: Expanding XOR equation found on signal \sp_read:reset_count_1\.T
  Information: Generating both D & T register equations for signal \sp_read:reset_count_2\.D
  Information: Expanding XOR equation found on signal \sp_read:reset_count_2\.T
  Information: Generating both D & T register equations for signal \sp_read:old_phase\.D
  Information: Expanding XOR equation found on signal \sp_read:old_phase\.T
  Information: Generating both D & T register equations for signal \sp_read:counter_read_stateSBV_3\.D
  Information: Expanding XOR equation found on signal \sp_read:counter_read_stateSBV_3\.T
  Information: Generating both D & T register equations for signal \sp_read:counter_read_stateSBV_2\.D
  Information: Expanding XOR equation found on signal \sp_read:counter_read_stateSBV_2\.T
  Information: Generating both D & T register equations for signal \sp_read:counter_read_stateSBV_1\.D
  Information: Expanding XOR equation found on signal \sp_read:counter_read_stateSBV_1\.T
  Information: Generating both D & T register equations for signal \sp_read:counter_read_stateSBV_0\.D
  Information: Expanding XOR equation found on signal \sp_read:counter_read_stateSBV_0\.T
  Information: Generating both D & T register equations for signal sensor_address_0.D
  Information: Expanding XOR equation found on signal sensor_address_0.T
  Information: Generating both D & T register equations for signal sensor_address_1.D
  Information: Expanding XOR equation found on signal sensor_address_1.T
  Information: Generating both D & T register equations for signal sensor_address_2.D
  Information: Expanding XOR equation found on signal sensor_address_2.T
  Information: Generating both D & T register equations for signal sensor_address_3.D
  Information: Expanding XOR equation found on signal sensor_address_3.T
  Information: Generating both D & T register equations for signal sensor_address_4.D
  Information: Expanding XOR equation found on signal sensor_address_4.T
  Information: Generating both D & T register equations for signal sensor_address_5.D
  Information: Expanding XOR equation found on signal sensor_address_5.T
  Information: Generating both D & T register equations for signal sensor_address_6.D
  Information: Expanding XOR equation found on signal sensor_address_6.T
  Information: Generating both D & T register equations for signal sensor_address_7.D
  Information: Expanding XOR equation found on signal sensor_address_7.T
  Information: Generating both D & T register equations for signal \bp_io:timeout_0\.D
  Information: Expanding XOR equation found on signal \bp_io:timeout_0\.T
  Information: Generating both D & T register equations for signal \bp_io:timeout_1\.D
  Information: Expanding XOR equation found on signal \bp_io:timeout_1\.T
  Information: Generating both D & T register equations for signal \bp_io:timeout_2\.D
  Information: Expanding XOR equation found on signal \bp_io:timeout_2\.T
  Information: Generating both D & T register equations for signal sensor_to_bp_read_req.D
  Information: Expanding XOR equation found on signal sensor_to_bp_read_req.T
  Information: Generating both D & T register equations for signal sensor_to_bp_read_ack.D
  Information: Expanding XOR equation found on signal sensor_to_bp_read_ack.T
  Information: Generating both D & T register equations for signal \bp_io:bp_access_stateSBV_2\.D
  Information: Expanding XOR equation found on signal \bp_io:bp_access_stateSBV_2\.T
  Information: Generating both D & T register equations for signal \bp_io:bp_access_stateSBV_1\.D
  Information: Expanding XOR equation found on signal \bp_io:bp_access_stateSBV_1\.T
  Information: Generating both D & T register equations for signal \bp_io:bp_access_stateSBV_0\.D
  Information: Expanding XOR equation found on signal \bp_io:bp_access_stateSBV_0\.T
  Information: Generating both D & T register equations for signal bp_end_address_7.D
  Information: Expanding XOR equation found on signal bp_end_address_7.T
  Information: Generating both D & T register equations for signal bp_start_address_7.D
  Information: Expanding XOR equation found on signal bp_start_address_7.T
  Information: Generating both D & T register equations for signal bp_end_address_6.D
  Information: Expanding XOR equation found on signal bp_end_address_6.T
  Information: Generating both D & T register equations for signal bp_start_address_6.D
  Information: Expanding XOR equation found on signal bp_start_address_6.T
  Information: Generating both D & T register equations for signal bp_end_address_5.D
  Information: Expanding XOR equation found on signal bp_end_address_5.T
  Information: Generating both D & T register equations for signal bp_start_address_5.D
  Information: Expanding XOR equation found on signal bp_start_address_5.T
  Information: Generating both D & T register equations for signal bp_end_address_4.D
  Information: Expanding XOR equation found on signal bp_end_address_4.T
  Information: Generating both D & T register equations for signal bp_start_address_4.D
  Information: Expanding XOR equation found on signal bp_start_address_4.T
  Information: Generating both D & T register equations for signal bp_end_address_3.D
  Information: Expanding XOR equation found on signal bp_end_address_3.T
  Information: Generating both D & T register equations for signal bp_start_address_3.D
  Information: Expanding XOR equation found on signal bp_start_address_3.T
  Information: Generating both D & T register equations for signal bp_end_address_2.D
  Information: Expanding XOR equation found on signal bp_end_address_2.T
  Information: Generating both D & T register equations for signal bp_start_address_2.D
  Information: Expanding XOR equation found on signal bp_start_address_2.T
  Information: Generating both D & T register equations for signal bp_end_address_1.D
  Information: Expanding XOR equation found on signal bp_end_address_1.T
  Information: Generating both D & T register equations for signal bp_start_address_1.D
  Information: Expanding XOR equation found on signal bp_start_address_1.T
  Information: Generating both D & T register equations for signal bp_end_address_0.D
  Information: Expanding XOR equation found on signal bp_end_address_0.T
  Information: Generating both D & T register equations for signal bp_start_address_0.D
  Information: Expanding XOR equation found on signal bp_start_address_0.T
  Information: Generating both D & T register equations for signal address_from_pc_0.D
  Information: Expanding XOR equation found on signal address_from_pc_0.T
  Information: Generating both D & T register equations for signal address_from_pc_1.D
  Information: Expanding XOR equation found on signal address_from_pc_1.T
  Information: Generating both D & T register equations for signal address_from_pc_2.D
  Information: Expanding XOR equation found on signal address_from_pc_2.T
  Information: Generating both D & T register equations for signal address_from_pc_3.D
  Information: Expanding XOR equation found on signal address_from_pc_3.T
  Information: Generating both D & T register equations for signal address_from_pc_4.D
  Information: Expanding XOR equation found on signal address_from_pc_4.T
  Information: Generating both D & T register equations for signal address_from_pc_5.D
  Information: Expanding XOR equation found on signal address_from_pc_5.T
  Information: Generating both D & T register equations for signal address_from_pc_6.D
  Information: Expanding XOR equation found on signal address_from_pc_6.T
  Information: Generating both D & T register equations for signal address_from_pc_7.D
  Information: Expanding XOR equation found on signal address_from_pc_7.T
  Information: Generating both D & T register equations for signal \ibus_reader:timeout_0\.D
  Information: Expanding XOR equation found on signal \ibus_reader:timeout_0\.T
  Information: Generating both D & T register equations for signal \ibus_reader:timeout_1\.D
  Information: Expanding XOR equation found on signal \ibus_reader:timeout_1\.T
  Information: Generating both D & T register equations for signal \ibus_reader:timeout_2\.D
  Information: Expanding XOR equation found on signal \ibus_reader:timeout_2\.T
  Information: Generating both D & T register equations for signal \ibus_reader:timeout_3\.D
  Information: Expanding XOR equation found on signal \ibus_reader:timeout_3\.T
  Information: Generating both D & T register equations for signal \ibus_reader:this_is_a_ctrl_transaction\.D
  Information: Expanding XOR equation found on signal \ibus_reader:this_is_a_ctrl_transaction\.T
  Information: Generating both D & T register equations for signal \ibus_reader:il_read_stateSBV_2\.D
  Information: Expanding XOR equation found on signal \ibus_reader:il_read_stateSBV_2\.T
  Information: Generating both D & T register equations for signal \ibus_reader:il_read_stateSBV_1\.D
  Information: Expanding XOR equation found on signal \ibus_reader:il_read_stateSBV_1\.T
  Information: Generating both D & T register equations for signal \ibus_reader:il_read_stateSBV_0\.D
  Information: Expanding XOR equation found on signal \ibus_reader:il_read_stateSBV_0\.T
  Information: Generating both D & T register equations for signal \ibus_writer:timeout_0\.D
  Information: Expanding XOR equation found on signal \ibus_writer:timeout_0\.T
  Information: Generating both D & T register equations for signal \ibus_writer:timeout_1\.D
  Information: Expanding XOR equation found on signal \ibus_writer:timeout_1\.T
  Information: Generating both D & T register equations for signal \ibus_writer:timeout_2\.D
  Information: Expanding XOR equation found on signal \ibus_writer:timeout_2\.T
  Information: Generating both D & T register equations for signal \ibus_writer:timeout_3\.D
  Information: Expanding XOR equation found on signal \ibus_writer:timeout_3\.T
  Information: Generating both D & T register equations for signal \ibus_writer:iu_writeSBV_1\.D
  Information: Expanding XOR equation found on signal \ibus_writer:iu_writeSBV_1\.T
  Information: Generating both D & T register equations for signal \ibus_writer:iu_writeSBV_0\.D
  Information: Expanding XOR equation found on signal \ibus_writer:iu_writeSBV_0\.T
  Information: Generating both D & T register equations for signal sensor_data_0.D
  Information: Expanding XOR equation found on signal sensor_data_0.T
  Information: Generating both D & T register equations for signal sensor_data_1.D
  Information: Expanding XOR equation found on signal sensor_data_1.T
  Information: Generating both D & T register equations for signal sensor_data_2.D
  Information: Expanding XOR equation found on signal sensor_data_2.T
  Information: Generating both D & T register equations for signal sensor_data_3.D
  Information: Expanding XOR equation found on signal sensor_data_3.T
  Information: Generating both D & T register equations for signal sensor_data_4.D
  Information: Expanding XOR equation found on signal sensor_data_4.T
  Information: Generating both D & T register equations for signal sensor_data_5.D
  Information: Expanding XOR equation found on signal sensor_data_5.T
  Information: Generating both D & T register equations for signal sensor_data_6.D
  Information: Expanding XOR equation found on signal sensor_data_6.T
  Information: Generating both D & T register equations for signal sensor_data_7.D
  Information: Expanding XOR equation found on signal sensor_data_7.T
  Information: Generating both D & T register equations for signal sensor_data_8.D
  Information: Expanding XOR equation found on signal sensor_data_8.T
  Information: Generating both D & T register equations for signal sensor_data_9.D
  Information: Expanding XOR equation found on signal sensor_data_9.T
  Information: Generating both D & T register equations for signal sensor_data_10.D
  Information: Expanding XOR equation found on signal sensor_data_10.T
  Information: Generating both D & T register equations for signal sensor_data_11.D
  Information: Expanding XOR equation found on signal sensor_data_11.T
  Information: Generating both D & T register equations for signal sensor_data_12.D
  Information: Expanding XOR equation found on signal sensor_data_12.T
  Information: Generating both D & T register equations for signal sensor_data_13.D
  Information: Expanding XOR equation found on signal sensor_data_13.T
  Information: Generating both D & T register equations for signal data_from_pc_13.D
  Information: Expanding XOR equation found on signal data_from_pc_13.T
  Information: Generating both D & T register equations for signal sensor_data_14.D
  Information: Expanding XOR equation found on signal sensor_data_14.T
  Information: Generating both D & T register equations for signal data_from_pc_14.D
  Information: Expanding XOR equation found on signal data_from_pc_14.T
  Information: Generating both D & T register equations for signal sensor_data_15.D
  Information: Expanding XOR equation found on signal sensor_data_15.T
  Information: Generating both D & T register equations for signal data_from_pc_15.D
  Information: Expanding XOR equation found on signal data_from_pc_15.T
  Information: Generating both D & T register equations for signal sensor_to_ibus_req.D
  Information: Expanding XOR equation found on signal sensor_to_ibus_req.T
  Information: Generating both D & T register equations for signal from_pc_req.D
  Information: Expanding XOR equation found on signal from_pc_req.T
  Information: Generating both D & T register equations for signal write_to_bp_ack.D
  Information: Expanding XOR equation found on signal write_to_bp_ack.T
  Information: Generating both D & T register equations for signal to_pc_ack.D
  Information: Expanding XOR equation found on signal to_pc_ack.T
  Information: Generating both D & T register equations for signal loopback_state.D
  Information: Expanding XOR equation found on signal loopback_state.T
  Information: Generating both D & T register equations for signal il_tristate.D
  Information: Expanding XOR equation found on signal il_tristate.T
  Information: Generating both D & T register equations for signal this_chip_selected.D
  Information: Expanding XOR equation found on signal this_chip_selected.T
  Information: Generating both D & T register equations for signal tristate_stateSBV_0.D
  Information: Expanding XOR equation found on signal tristate_stateSBV_0.T
  Information: Optimizing logic without changing polarity for signals:
         \bp_io:bp_access_stateSBV_0\.T \bp_io:bp_access_stateSBV_1\.T
         \bp_io:bp_access_stateSBV_2\.T \bp_io:timeout_0\.T
         \bp_io:timeout_1\.T \bp_io:timeout_2\.T
         \ibus_reader:il_read_stateSBV_0\.T \ibus_reader:il_read_stateSBV_1\.T
         \ibus_reader:il_read_stateSBV_2\.T
         \ibus_reader:this_is_a_ctrl_transaction\.T \ibus_reader:timeout_0\.T
         \ibus_reader:timeout_1\.T \ibus_reader:timeout_2\.T
         \ibus_reader:timeout_3\.T \ibus_writer:iu_writeSBV_0\.T
         \ibus_writer:iu_writeSBV_1\.T \ibus_writer:timeout_0\.T
         \ibus_writer:timeout_1\.T \ibus_writer:timeout_2\.T
         \ibus_writer:timeout_3\.T \sp_read:counter_address_0\.T
         \sp_read:counter_address_1\.T \sp_read:counter_address_2\.T
         \sp_read:counter_address_3\.T \sp_read:counter_address_4\.T
         \sp_read:counter_address_5\.T \sp_read:counter_address_6\.T
         \sp_read:counter_address_7\.T \sp_read:counter_read_stateSBV_0\.T
         \sp_read:counter_read_stateSBV_1\.T
         \sp_read:counter_read_stateSBV_2\.T
         \sp_read:counter_read_stateSBV_3\.T \sp_read:old_phase\.T
         \sp_read:reset_count_0\.T \sp_read:reset_count_1\.T
         \sp_read:reset_count_2\.T address_from_pc_0.T address_from_pc_1.T
         address_from_pc_2.T address_from_pc_3.T address_from_pc_4.T
         address_from_pc_5.T address_from_pc_6.T address_from_pc_7.T
         ao_from_pc_ack.T ao_to_pc_strobe.T bp_end_address_0.T
         bp_end_address_1.T bp_end_address_2.T bp_end_address_3.T
         bp_end_address_4.T bp_end_address_5.T bp_end_address_6.T
         bp_end_address_7.T bp_start_address_0.T bp_start_address_1.T
         bp_start_address_2.T bp_start_address_3.T bp_start_address_4.T
         bp_start_address_5.T bp_start_address_6.T bp_start_address_7.T
         bpaddr(0).T bpaddr(1).T bpaddr(2).T bpaddr(3).T bpaddr(4).T
         bpaddr(5).T bpaddr(6).T bpaddr(7).T bpaddr_tristate.T bpctrl(0).T
         bpctrl(10).T bpctrl(11).T bpctrl(2).T bpctrl(3).T bpctrl(4).T
         bpctrl(5).T bpctrl(6).T bpctrl(7).T bpctrl(8).T bpd(10).T bpd(11).T
         bpd(12).T bpd(13).T bpd(14).T bpd(15).T bpd_h_tristate.T d(16).T
         d(17).T d(18).T d(19).T d(20).T d(21).T d(22).T d(23).T d(24).T
         d(25).T d(26).T d(27).T d(28).T d(29).T d(30).T d(31).T
         data_from_pc_13.T data_from_pc_14.T data_from_pc_15.T from_pc_req.T
         il_tristate.T led1.T sensor_address_0.T sensor_address_1.T
         sensor_address_2.T sensor_address_3.T sensor_address_4.T
         sensor_address_5.T sensor_address_6.T sensor_address_7.T
         sensor_data_0.T sensor_data_1.T sensor_data_10.T sensor_data_11.T
         sensor_data_12.T sensor_data_13.T sensor_data_14.T sensor_data_15.T
         sensor_data_2.T sensor_data_3.T sensor_data_4.T sensor_data_5.T
         sensor_data_6.T sensor_data_7.T sensor_data_8.T sensor_data_9.T
         sensor_to_bp_read_ack.T sensor_to_bp_read_req.T sensor_to_ibus_req.T
         this_chip_selected.T to_pc_ack.T tristate_stateSBV_0.T
         write_to_bp_ack.T

  Information: Optimizing logic using best output polarity for signals:
         \bp_io:bp_access_stateSBV_0\.D \bp_io:bp_access_stateSBV_1\.D
         \bp_io:bp_access_stateSBV_2\.D \bp_io:timeout_0\.D
         \bp_io:timeout_1\.D \bp_io:timeout_2\.D
         \ibus_reader:il_read_stateSBV_0\.D \ibus_reader:il_read_stateSBV_1\.D
         \ibus_reader:il_read_stateSBV_2\.D
         \ibus_reader:this_is_a_ctrl_transaction\.D \ibus_reader:timeout_0\.D
         \ibus_reader:timeout_1\.D \ibus_reader:timeout_2\.D
         \ibus_reader:timeout_3\.D \ibus_writer:iu_writeSBV_0\.D
         \ibus_writer:iu_writeSBV_1\.D \ibus_writer:timeout_0\.D
         \ibus_writer:timeout_1\.D \ibus_writer:timeout_2\.D
         \ibus_writer:timeout_3\.D \sp_read:cmp_vv_us_MODGEN_10\
         \sp_read:counter_address_0\.D \sp_read:counter_address_1\.D
         \sp_read:counter_address_2\.D \sp_read:counter_address_3\.D
         \sp_read:counter_address_4\.D \sp_read:counter_address_5\.D
         \sp_read:counter_address_6\.D \sp_read:counter_address_7\.D
         \sp_read:counter_read_stateSBV_0\.D
         \sp_read:counter_read_stateSBV_1\.D
         \sp_read:counter_read_stateSBV_2\.D
         \sp_read:counter_read_stateSBV_3\.D \sp_read:reset_count_1\.D
         \sp_read:reset_count_2\.D address_from_pc_0.D address_from_pc_1.D
         address_from_pc_2.D address_from_pc_3.D address_from_pc_4.D
         address_from_pc_5.D address_from_pc_6.D address_from_pc_7.D
         ao_to_pc_strobe.D bp_end_address_0.D bp_end_address_1.D
         bp_end_address_2.D bp_end_address_3.D bp_end_address_4.D
         bp_end_address_5.D bp_end_address_6.D bp_end_address_7.D
         bp_start_address_0.D bp_start_address_1.D bp_start_address_2.D
         bp_start_address_3.D bp_start_address_4.D bp_start_address_5.D
         bp_start_address_6.D bp_start_address_7.D bpaddr(0).D bpaddr(1).D
         bpaddr(2).D bpaddr(3).D bpaddr(4).D bpaddr(5).D bpaddr(6).D
         bpaddr(7).D bpaddr_tristate.D bpctrl(0).D bpctrl(10).D bpctrl(11).D
         bpctrl(2).D bpctrl(3).D bpctrl(4).D bpctrl(5).D bpctrl(6).D
         bpctrl(7).D bpctrl(8).D bpd(10).D bpd(11).D bpd(12).D bpd(13).D
         bpd(14).D bpd(15).D bpd_h_tristate.D d(16).D d(17).D d(18).D d(19).D
         d(20).D d(21).D d(22).D d(23).D d(24).D d(25).D d(26).D d(27).D
         d(28).D d(29).D d(30).D d(31).D data_from_pc_13.D data_from_pc_14.D
         data_from_pc_15.D from_pc_req.D il_tristate.D led1.D loopback_state.D
         sensor_address_0.D sensor_address_1.D sensor_address_2.D
         sensor_address_3.D sensor_address_4.D sensor_address_5.D
         sensor_address_6.D sensor_address_7.D sensor_data_0.D sensor_data_1.D
         sensor_data_10.D sensor_data_11.D sensor_data_12.D sensor_data_13.D
         sensor_data_14.D sensor_data_15.D sensor_data_2.D sensor_data_3.D
         sensor_data_4.D sensor_data_5.D sensor_data_6.D sensor_data_7.D
         sensor_data_8.D sensor_data_9.D sensor_to_bp_read_ack.D
         sensor_to_ibus_req.D this_chip_selected.D to_pc_ack.D
         write_to_bp_ack.D

  Information: Selected logic optimization OFF for signals:
         \bp_io:bp_access_stateSBV_0\.AR \bp_io:bp_access_stateSBV_0\.C
         \bp_io:bp_access_stateSBV_1\.AR \bp_io:bp_access_stateSBV_1\.C
         \bp_io:bp_access_stateSBV_2\.AR \bp_io:bp_access_stateSBV_2\.C
         \bp_io:timeout_0\.AR \bp_io:timeout_0\.C \bp_io:timeout_1\.AR
         \bp_io:timeout_1\.C \bp_io:timeout_2\.AR \bp_io:timeout_2\.C
         \ibus_reader:il_read_stateSBV_0\.AR
         \ibus_reader:il_read_stateSBV_0\.C
         \ibus_reader:il_read_stateSBV_1\.AR
         \ibus_reader:il_read_stateSBV_1\.C
         \ibus_reader:il_read_stateSBV_2\.AR
         \ibus_reader:il_read_stateSBV_2\.C
         \ibus_reader:this_is_a_ctrl_transaction\.AR
         \ibus_reader:this_is_a_ctrl_transaction\.C \ibus_reader:timeout_0\.AR
         \ibus_reader:timeout_0\.C \ibus_reader:timeout_1\.AR
         \ibus_reader:timeout_1\.C \ibus_reader:timeout_2\.AR
         \ibus_reader:timeout_2\.C \ibus_reader:timeout_3\.AR
         \ibus_reader:timeout_3\.C \ibus_writer:iu_writeSBV_0\.AR
         \ibus_writer:iu_writeSBV_0\.C \ibus_writer:iu_writeSBV_1\.AR
         \ibus_writer:iu_writeSBV_1\.C \ibus_writer:timeout_0\.AR
         \ibus_writer:timeout_0\.C \ibus_writer:timeout_1\.AR
         \ibus_writer:timeout_1\.C \ibus_writer:timeout_2\.AR
         \ibus_writer:timeout_2\.C \ibus_writer:timeout_3\.AR
         \ibus_writer:timeout_3\.C \sp_read:counter_address_0\.AR
         \sp_read:counter_address_0\.C \sp_read:counter_address_1\.AR
         \sp_read:counter_address_1\.C \sp_read:counter_address_2\.AR
         \sp_read:counter_address_2\.C \sp_read:counter_address_3\.AR
         \sp_read:counter_address_3\.C \sp_read:counter_address_4\.AR
         \sp_read:counter_address_4\.C \sp_read:counter_address_5\.AR
         \sp_read:counter_address_5\.C \sp_read:counter_address_6\.AR
         \sp_read:counter_address_6\.C \sp_read:counter_address_7\.AR
         \sp_read:counter_address_7\.C \sp_read:counter_read_stateSBV_0\.AR
         \sp_read:counter_read_stateSBV_0\.C
         \sp_read:counter_read_stateSBV_1\.AR
         \sp_read:counter_read_stateSBV_1\.C
         \sp_read:counter_read_stateSBV_2\.AR
         \sp_read:counter_read_stateSBV_2\.C
         \sp_read:counter_read_stateSBV_3\.AR
         \sp_read:counter_read_stateSBV_3\.C \sp_read:old_phase\.D
         \sp_read:old_phase\.AP \sp_read:old_phase\.AR \sp_read:old_phase\.C
         \sp_read:reset_count_0\.D \sp_read:reset_count_0\.AR
         \sp_read:reset_count_0\.C \sp_read:reset_count_1\.AR
         \sp_read:reset_count_1\.C \sp_read:reset_count_2\.AR
         \sp_read:reset_count_2\.C address_from_pc_0.AR address_from_pc_0.C
         address_from_pc_1.AR address_from_pc_1.C address_from_pc_2.AR
         address_from_pc_2.C address_from_pc_3.AR address_from_pc_3.C
         address_from_pc_4.AR address_from_pc_4.C address_from_pc_5.AR
         address_from_pc_5.C address_from_pc_6.AR address_from_pc_6.C
         address_from_pc_7.AR address_from_pc_7.C ao_from_pc_ack.D
         ao_from_pc_ack.AR ao_from_pc_ack.C ao_from_pc_ack.OE
         ao_to_pc_strobe.AR ao_to_pc_strobe.C bp_end_address_0.AP
         bp_end_address_0.C bp_end_address_1.AP bp_end_address_1.C
         bp_end_address_2.AP bp_end_address_2.C bp_end_address_3.AP
         bp_end_address_3.C bp_end_address_4.AP bp_end_address_4.C
         bp_end_address_5.AP bp_end_address_5.C bp_end_address_6.AP
         bp_end_address_6.C bp_end_address_7.AP bp_end_address_7.C
         bp_start_address_0.AP bp_start_address_0.C bp_start_address_1.AP
         bp_start_address_1.C bp_start_address_2.AP bp_start_address_2.C
         bp_start_address_3.AP bp_start_address_3.C bp_start_address_4.AP
         bp_start_address_4.C bp_start_address_5.AP bp_start_address_5.C
         bp_start_address_6.AP bp_start_address_6.C bp_start_address_7.AP
         bp_start_address_7.C bpaddr(0).AR bpaddr(0).C bpaddr(1).AR
         bpaddr(1).C bpaddr(2).AR bpaddr(2).C bpaddr(3).AR bpaddr(3).C
         bpaddr(4).AR bpaddr(4).C bpaddr(5).AR bpaddr(5).C bpaddr(6).AR
         bpaddr(6).C bpaddr(7).AR bpaddr(7).C bpaddr_dir bpaddr_tristate.AP
         bpaddr_tristate.C bpctrl(0).AR bpctrl(0).C bpctrl(1) bpctrl(10).AR
         bpctrl(10).C bpctrl(10).OE bpctrl(11).AR bpctrl(11).C bpctrl(11).OE
         bpctrl(2).AR bpctrl(2).C bpctrl(3).AR bpctrl(3).C bpctrl(4).AR
         bpctrl(4).C bpctrl(4).OE bpctrl(5).AR bpctrl(5).C bpctrl(5).OE
         bpctrl(6).AR bpctrl(6).C bpctrl(6).OE bpctrl(7).AR bpctrl(7).C
         bpctrl(7).OE bpctrl(8).AR bpctrl(8).C bpctrl(8).OE bpctrl_h_dir
         bpctrl_h_tristate bpctrl_l_dir bpctrl_l_tristate bpd(10).AR bpd(10).C
         bpd(10).OE bpd(11).AR bpd(11).C bpd(11).OE bpd(12).AR bpd(12).C
         bpd(12).OE bpd(13).AR bpd(13).C bpd(13).OE bpd(14).AR bpd(14).C
         bpd(14).OE bpd(15).AR bpd(15).C bpd(15).OE bpd_h_dir
         bpd_h_tristate.AP bpd_h_tristate.C bpd_l_dir bpd_l_tristate d(16).AR
         d(16).C d(17).AR d(17).C d(18).AR d(18).C d(19).AR d(19).C d(20).AR
         d(20).C d(21).AR d(21).C d(22).AR d(22).C d(23).AR d(23).C d(24).AR
         d(24).C d(25).AR d(25).C d(26).AR d(26).C d(27).AR d(27).C d(28).AR
         d(28).C d(29).AR d(29).C d(30).AR d(30).C d(31).AR d(31).C
         data_from_pc_13.AR data_from_pc_13.C data_from_pc_14.AR
         data_from_pc_14.C data_from_pc_15.AR data_from_pc_15.C from_pc_req.AR
         from_pc_req.C il_tristate.AP il_tristate.C led1.AP led1.C led2 led3
         loopback_state.T loopback_state.AR loopback_state.C reset
         sensor_address_0.AR sensor_address_0.C sensor_address_1.AR
         sensor_address_1.C sensor_address_2.AR sensor_address_2.C
         sensor_address_3.AR sensor_address_3.C sensor_address_4.AR
         sensor_address_4.C sensor_address_5.AR sensor_address_5.C
         sensor_address_6.AR sensor_address_6.C sensor_address_7.AR
         sensor_address_7.C sensor_data_0.AR sensor_data_0.C sensor_data_1.AR
         sensor_data_1.C sensor_data_10.AR sensor_data_10.C sensor_data_11.AR
         sensor_data_11.C sensor_data_12.AR sensor_data_12.C sensor_data_13.AR
         sensor_data_13.C sensor_data_14.AR sensor_data_14.C sensor_data_15.AR
         sensor_data_15.C sensor_data_2.AR sensor_data_2.C sensor_data_3.AR
         sensor_data_3.C sensor_data_4.AR sensor_data_4.C sensor_data_5.AR
         sensor_data_5.C sensor_data_6.AR sensor_data_6.C sensor_data_7.AR
         sensor_data_7.C sensor_data_8.AR sensor_data_8.C sensor_data_9.AR
         sensor_data_9.C sensor_to_bp_read_ack.AR sensor_to_bp_read_ack.C
         sensor_to_bp_read_req.D sensor_to_bp_read_req.AR
         sensor_to_bp_read_req.C sensor_to_ibus_req.AR sensor_to_ibus_req.C
         this_chip_selected.AR this_chip_selected.C to_pc_ack.AR to_pc_ack.C
         tristate_stateSBV_0.D tristate_stateSBV_0.AR tristate_stateSBV_0.C
         write_to_bp_ack.AR write_to_bp_ack.C



Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully  
----------------------------------------------------------------------------
PLD Optimizer Software:       MINOPT.EXE     01/NOV/1999  [v4.02 ] 6.2 IR 27

LOGIC MINIMIZATION         ()

Messages:


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully
----------------------------------------------------------------------------
PLD Optimizer Software:       DSGNOPT.EXE    31/03/2000  [v4.02 ] 6.2 IR 27

OPTIMIZATION OPTIONS       (15:40:39)

Messages:
  Information: Optimizing Banked Preset/Reset requirements.
  Information: Selecting T register equation as minimal for signal \bp_io:bp_access_stateSBV_0\
  Information: Selecting D register equation as minimal for signal \bp_io:timeout_0\
  Information: Selecting D register equation as minimal for signal \ibus_reader:this_is_a_ctrl_transaction\
  Information: Selecting D register equation as minimal for signal \ibus_reader:timeout_0\
  Information: Selecting D register equation as minimal for signal \ibus_reader:timeout_1\
  Information: Selecting D register equation as minimal for signal \ibus_reader:timeout_3\
  Information: Selecting T register equation as minimal for signal \ibus_writer:iu_writeSBV_0\
  Information: Selecting D register equation as minimal for signal \ibus_writer:timeout_0\
  Information: Selecting T register equation as minimal for signal \ibus_writer:timeout_1\
  Information: Selecting D register equation as minimal for signal \sp_read:counter_address_0\
  Information: Selecting D register equation as minimal for signal \sp_read:counter_address_1\
  Information: Selecting D register equation as minimal for signal \sp_read:counter_address_2\
  Information: Selecting D register equation as minimal for signal \sp_read:counter_address_3\
  Information: Selecting D register equation as minimal for signal \sp_read:counter_address_4\
  Information: Selecting D register equation as minimal for signal \sp_read:counter_address_5\
  Information: Selecting D register equation as minimal for signal \sp_read:counter_address_6\
  Information: Selecting D register equation as minimal for signal \sp_read:counter_address_7\
  Information: Selecting D register equation as minimal for signal \sp_read:counter_read_stateSBV_0\
  Information: Selecting T register equation as minimal for signal \sp_read:counter_read_stateSBV_1\
  Information: Selecting D register equation as minimal for signal \sp_read:counter_read_stateSBV_2\
  Information: Selecting D register equation as minimal for signal \sp_read:counter_read_stateSBV_3\
  Information: Selecting D register equation as minimal for signal \sp_read:reset_count_0\
  Information: Selecting D register equation as minimal for signal \sp_read:reset_count_1\
  Information: Selecting T register equation as minimal for signal \sp_read:reset_count_2\
  Information: Selecting T register equation as minimal for signal address_from_pc_0
  Information: Selecting T register equation as minimal for signal address_from_pc_1
  Information: Selecting T register equation as minimal for signal address_from_pc_2
  Information: Selecting T register equation as minimal for signal address_from_pc_3
  Information: Selecting T register equation as minimal for signal address_from_pc_4
  Information: Selecting T register equation as minimal for signal address_from_pc_5
  Information: Selecting T register equation as minimal for signal address_from_pc_6
  Information: Selecting T register equation as minimal for signal address_from_pc_7
  Information: Selecting T register equation as minimal for signal data_from_pc_13
  Information: Selecting T register equation as minimal for signal data_from_pc_14
  Information: Selecting T register equation as minimal for signal data_from_pc_15
  Information: Selecting D register equation as minimal for signal from_pc_req
  Information: Selecting T register equation as minimal for signal sensor_address_0
  Information: Selecting T register equation as minimal for signal sensor_address_1
  Information: Selecting T register equation as minimal for signal sensor_address_2
  Information: Selecting T register equation as minimal for signal sensor_address_3
  Information: Selecting T register equation as minimal for signal sensor_address_4
  Information: Selecting T register equation as minimal for signal sensor_address_5
  Information: Selecting T register equation as minimal for signal sensor_address_6
  Information: Selecting T register equation as minimal for signal sensor_address_7
  Information: Selecting T register equation as minimal for signal sensor_data_0
  Information: Selecting T register equation as minimal for signal sensor_data_1
  Information: Selecting T register equation as minimal for signal sensor_data_10
  Information: Selecting T register equation as minimal for signal sensor_data_11
  Information: Selecting T register equation as minimal for signal sensor_data_12
  Information: Selecting T register equation as minimal for signal sensor_data_13
  Information: Selecting T register equation as minimal for signal sensor_data_14
  Information: Selecting T register equation as minimal for signal sensor_data_15
  Information: Selecting T register equation as minimal for signal sensor_data_2
  Information: Selecting T register equation as minimal for signal sensor_data_3
  Information: Selecting T register equation as minimal for signal sensor_data_4
  Information: Selecting T register equation as minimal for signal sensor_data_5
  Information: Selecting T register equation as minimal for signal sensor_data_6
  Information: Selecting T register equation as minimal for signal sensor_data_7
  Information: Selecting T register equation as minimal for signal sensor_data_8
  Information: Selecting T register equation as minimal for signal sensor_data_9
  Information: Selecting D register equation as minimal for signal sensor_to_bp_read_ack
  Information: Selecting D register equation as minimal for signal sensor_to_bp_read_req
  Information: Selecting D register equation as minimal for signal sensor_to_ibus_req
  Information: Selecting D register equation as minimal for signal this_chip_selected
  Information: Selecting D register equation as minimal for signal to_pc_ack
  Information: Selecting D register equation as minimal for signal tristate_stateSBV_0
  Information: Selecting D register equation as minimal for signal write_to_bp_ack
  Information: Selecting T register equation as minimal for signal bpd(15)
  Information: Selecting T register equation as minimal for signal bpd(14)
  Information: Selecting T register equation as minimal for signal bpd(13)
  Information: Selecting T register equation as minimal for signal bpd(12)
  Information: Selecting T register equation as minimal for signal bpd(11)
  Information: Selecting T register equation as minimal for signal bpd(10)
  Information: Selecting T register equation as minimal for signal d(31)
  Information: Selecting T register equation as minimal for signal d(30)
  Information: Selecting T register equation as minimal for signal d(29)
  Information: Selecting T register equation as minimal for signal d(28)
  Information: Selecting T register equation as minimal for signal d(27)
  Information: Selecting T register equation as minimal for signal d(26)
  Information: Selecting T register equation as minimal for signal d(25)
  Information: Selecting T register equation as minimal for signal d(24)
  Information: Selecting T register equation as minimal for signal d(23)
  Information: Selecting T register equation as minimal for signal d(22)
  Information: Selecting T register equation as minimal for signal d(21)
  Information: Selecting T register equation as minimal for signal d(20)
  Information: Selecting T register equation as minimal for signal d(19)
  Information: Selecting T register equation as minimal for signal d(18)
  Information: Selecting T register equation as minimal for signal d(17)
  Information: Selecting T register equation as minimal for signal d(16)
  Information: Selecting D register equation as minimal for signal ao_from_pc_ack
  Information: Selecting D register equation as minimal for signal ao_to_pc_strobe
  Information: Selecting D register equation as minimal for signal led1
  Information: Selecting T register equation as minimal for signal bpaddr(7)
  Information: Selecting T register equation as minimal for signal bpaddr(6)
  Information: Selecting T register equation as minimal for signal bpaddr(5)
  Information: Selecting T register equation as minimal for signal bpaddr(4)
  Information: Selecting T register equation as minimal for signal bpaddr(3)
  Information: Selecting T register equation as minimal for signal bpaddr(2)
  Information: Selecting T register equation as minimal for signal bpaddr(1)
  Information: Selecting T register equation as minimal for signal bpaddr(0)
  Information: Selecting T register equation as minimal for signal bpctrl(11)
  Information: Selecting T register equation as minimal for signal bpctrl(10)
  Information: Selecting T register equation as minimal for signal bpctrl(8)
  Information: Selecting T register equation as minimal for signal bpctrl(7)
  Information: Selecting T register equation as minimal for signal bpctrl(6)
  Information: Selecting T register equation as minimal for signal bpctrl(5)
  Information: Selecting T register equation as minimal for signal bpctrl(4)
  Information: Selecting D register equation as minimal for signal bpctrl(2)
  Information: Selecting D register equation as minimal for signal bpctrl(0)
  Information: Inverting Preset/Reset & output logic polarity for \bp_io:bp_access_stateSBV_1\.
  Information: Selecting T register equation as minimal for signal \bp_io:bp_access_stateSBV_1\
  Information: Inverting Preset/Reset & output logic polarity for \bp_io:bp_access_stateSBV_2\.
  Information: Selecting T register equation as minimal for signal \bp_io:bp_access_stateSBV_2\
  Information: Inverting Preset/Reset & output logic polarity for \bp_io:timeout_1\.
  Information: Selecting T register equation as minimal for signal \bp_io:timeout_1\
  Information: Inverting Preset/Reset & output logic polarity for \bp_io:timeout_2\.
  Information: Selecting T register equation as minimal for signal \bp_io:timeout_2\
  Information: Inverting Preset/Reset & output logic polarity for \ibus_reader:il_read_stateSBV_0\.
  Information: Selecting T register equation as minimal for signal \ibus_reader:il_read_stateSBV_0\
  Information: Inverting Preset/Reset & output logic polarity for \ibus_reader:il_read_stateSBV_1\.
  Information: Selecting T register equation as minimal for signal \ibus_reader:il_read_stateSBV_1\
  Information: Inverting Preset/Reset & output logic polarity for \ibus_reader:il_read_stateSBV_2\.
  Information: Selecting T register equation as minimal for signal \ibus_reader:il_read_stateSBV_2\
  Information: Inverting Preset/Reset & output logic polarity for \ibus_reader:timeout_2\.
  Information: Selecting T register equation as minimal for signal \ibus_reader:timeout_2\
  Information: Inverting Preset/Reset & output logic polarity for \ibus_writer:iu_writeSBV_1\.
  Information: Selecting T register equation as minimal for signal \ibus_writer:iu_writeSBV_1\
  Information: Inverting Preset/Reset & output logic polarity for \ibus_writer:timeout_2\.
  Information: Selecting T register equation as minimal for signal \ibus_writer:timeout_2\
  Information: Inverting Preset/Reset & output logic polarity for \ibus_writer:timeout_3\.
  Information: Selecting T register equation as minimal for signal \ibus_writer:timeout_3\
  Information: Inverting Preset/Reset & output logic polarity for bp_end_address_0.
  Information: Selecting T register equation as minimal for signal bp_end_address_0
  Information: Inverting Preset/Reset & output logic polarity for bp_end_address_1.
  Information: Selecting T register equation as minimal for signal bp_end_address_1
  Information: Inverting Preset/Reset & output logic polarity for bp_end_address_2.
  Information: Selecting T register equation as minimal for signal bp_end_address_2
  Information: Inverting Preset/Reset & output logic polarity for bp_end_address_3.
  Information: Selecting T register equation as minimal for signal bp_end_address_3
  Information: Inverting Preset/Reset & output logic polarity for bp_end_address_4.
  Information: Selecting T register equation as minimal for signal bp_end_address_4
  Information: Inverting Preset/Reset & output logic polarity for bp_end_address_5.
  Information: Selecting T register equation as minimal for signal bp_end_address_5
  Information: Inverting Preset/Reset & output logic polarity for bp_end_address_6.
  Information: Selecting T register equation as minimal for signal bp_end_address_6
  Information: Inverting Preset/Reset & output logic polarity for bp_end_address_7.
  Information: Selecting T register equation as minimal for signal bp_end_address_7
  Information: Inverting Preset/Reset & output logic polarity for bp_start_address_0.
  Information: Selecting T register equation as minimal for signal bp_start_address_0
  Information: Inverting Preset/Reset & output logic polarity for bp_start_address_1.
  Information: Selecting T register equation as minimal for signal bp_start_address_1
  Information: Inverting Preset/Reset & output logic polarity for bp_start_address_2.
  Information: Selecting T register equation as minimal for signal bp_start_address_2
  Information: Inverting Preset/Reset & output logic polarity for bp_start_address_3.
  Information: Selecting T register equation as minimal for signal bp_start_address_3
  Information: Inverting Preset/Reset & output logic polarity for bp_start_address_4.
  Information: Selecting T register equation as minimal for signal bp_start_address_4
  Information: Inverting Preset/Reset & output logic polarity for bp_start_address_5.
  Information: Selecting T register equation as minimal for signal bp_start_address_5
  Information: Inverting Preset/Reset & output logic polarity for bp_start_address_6.
  Information: Selecting T register equation as minimal for signal bp_start_address_6
  Information: Inverting Preset/Reset & output logic polarity for bp_start_address_7.
  Information: Selecting T register equation as minimal for signal bp_start_address_7
  Information: Inverting Preset/Reset & output logic polarity for il_tristate.
  Information: Selecting D register equation as minimal for signal il_tristate
  Information: Inverting Preset/Reset & output logic polarity for loopback_state.
  Information: Selecting T register equation as minimal for signal loopback_state
  Information: Inverting Preset/Reset & output logic polarity for bpaddr_tristate.
  Information: Selecting D register equation as minimal for signal bpaddr_tristate
  Information: Inverting Preset/Reset & output logic polarity for bpd_h_tristate.
  Information: Selecting D register equation as minimal for signal bpd_h_tristate
  Information: Inverting Preset/Reset & output logic polarity for bpctrl(3).
  Information: Selecting D register equation as minimal for signal bpctrl(3)
  Information: Selecting D register equation as minimal for signal \sp_read:old_phase\
  Information: Optimizing logic without changing polarity for signals:
         \bp_io:bp_access_stateSBV_0\.T \bp_io:bp_access_stateSBV_1\.T
         \bp_io:bp_access_stateSBV_2\.T \bp_io:timeout_0\.D
         \bp_io:timeout_1\.T \bp_io:timeout_2\.T
         \ibus_reader:il_read_stateSBV_0\.T \ibus_reader:il_read_stateSBV_1\.T
         \ibus_reader:il_read_stateSBV_2\.T
         \ibus_reader:this_is_a_ctrl_transaction\.D \ibus_reader:timeout_0\.D
         \ibus_reader:timeout_1\.D \ibus_reader:timeout_2\.T
         \ibus_reader:timeout_3\.D \ibus_writer:iu_writeSBV_0\.T
         \ibus_writer:iu_writeSBV_1\.T \ibus_writer:timeout_0\.D
         \ibus_writer:timeout_1\.T \ibus_writer:timeout_2\.T
         \ibus_writer:timeout_3\.T \sp_read:cmp_vv_us_MODGEN_10\
         \sp_read:counter_address_0\.D \sp_read:counter_address_1\.D
         \sp_read:counter_address_2\.D \sp_read:counter_address_3\.D
         \sp_read:counter_address_4\.D \sp_read:counter_address_5\.D
         \sp_read:counter_address_6\.D \sp_read:counter_address_7\.D
         \sp_read:counter_read_stateSBV_0\.D
         \sp_read:counter_read_stateSBV_1\.T
         \sp_read:counter_read_stateSBV_2\.D
         \sp_read:counter_read_stateSBV_3\.D \sp_read:reset_count_1\.D
         \sp_read:reset_count_2\.T address_from_pc_0.T address_from_pc_1.T
         address_from_pc_2.T address_from_pc_3.T address_from_pc_4.T
         address_from_pc_5.T address_from_pc_6.T address_from_pc_7.T
         ao_to_pc_strobe.D bp_end_address_0.T bp_end_address_1.T
         bp_end_address_2.T bp_end_address_3.T bp_end_address_4.T
         bp_end_address_5.T bp_end_address_6.T bp_end_address_7.T
         bp_start_address_0.T bp_start_address_1.T bp_start_address_2.T
         bp_start_address_3.T bp_start_address_4.T bp_start_address_5.T
         bp_start_address_6.T bp_start_address_7.T bpaddr(0).T bpaddr(1).T
         bpaddr(2).T bpaddr(3).T bpaddr(4).T bpaddr(5).T bpaddr(6).T
         bpaddr(7).T bpaddr_tristate.D bpctrl(0).D bpctrl(10).T bpctrl(11).T
         bpctrl(2).D bpctrl(3).D bpctrl(4).T bpctrl(5).T bpctrl(6).T
         bpctrl(7).T bpctrl(8).T bpd(10).T bpd(11).T bpd(12).T bpd(13).T
         bpd(14).T bpd(15).T bpd_h_tristate.D d(16).T d(17).T d(18).T d(19).T
         d(20).T d(21).T d(22).T d(23).T d(24).T d(25).T d(26).T d(27).T
         d(28).T d(29).T d(30).T d(31).T data_from_pc_13.T data_from_pc_14.T
         data_from_pc_15.T from_pc_req.D il_tristate.D led1.D
         sensor_address_0.T sensor_address_1.T sensor_address_2.T
         sensor_address_3.T sensor_address_4.T sensor_address_5.T
         sensor_address_6.T sensor_address_7.T sensor_data_0.T sensor_data_1.T
         sensor_data_10.T sensor_data_11.T sensor_data_12.T sensor_data_13.T
         sensor_data_14.T sensor_data_15.T sensor_data_2.T sensor_data_3.T
         sensor_data_4.T sensor_data_5.T sensor_data_6.T sensor_data_7.T
         sensor_data_8.T sensor_data_9.T sensor_to_bp_read_ack.D
         sensor_to_ibus_req.D this_chip_selected.D to_pc_ack.D
         write_to_bp_ack.D

  Information: Selected logic optimization OFF for signals:
         \bp_io:bp_access_stateSBV_0\.AP \bp_io:bp_access_stateSBV_0\.AR
         \bp_io:bp_access_stateSBV_0\.C \bp_io:bp_access_stateSBV_1\.AP
         \bp_io:bp_access_stateSBV_1\.AR \bp_io:bp_access_stateSBV_1\.C
         \bp_io:bp_access_stateSBV_2\.AP \bp_io:bp_access_stateSBV_2\.AR
         \bp_io:bp_access_stateSBV_2\.C \bp_io:timeout_0\.AP
         \bp_io:timeout_0\.AR \bp_io:timeout_0\.C \bp_io:timeout_1\.AP
         \bp_io:timeout_1\.AR \bp_io:timeout_1\.C \bp_io:timeout_2\.AP
         \bp_io:timeout_2\.AR \bp_io:timeout_2\.C
         \ibus_reader:il_read_stateSBV_0\.AP
         \ibus_reader:il_read_stateSBV_0\.AR
         \ibus_reader:il_read_stateSBV_0\.C
         \ibus_reader:il_read_stateSBV_1\.AP
         \ibus_reader:il_read_stateSBV_1\.AR
         \ibus_reader:il_read_stateSBV_1\.C
         \ibus_reader:il_read_stateSBV_2\.AP
         \ibus_reader:il_read_stateSBV_2\.AR
         \ibus_reader:il_read_stateSBV_2\.C
         \ibus_reader:this_is_a_ctrl_transaction\.AP
         \ibus_reader:this_is_a_ctrl_transaction\.AR
         \ibus_reader:this_is_a_ctrl_transaction\.C \ibus_reader:timeout_0\.AP
         \ibus_reader:timeout_0\.AR \ibus_reader:timeout_0\.C
         \ibus_reader:timeout_1\.AP \ibus_reader:timeout_1\.AR
         \ibus_reader:timeout_1\.C \ibus_reader:timeout_2\.AP
         \ibus_reader:timeout_2\.AR \ibus_reader:timeout_2\.C
         \ibus_reader:timeout_3\.AP \ibus_reader:timeout_3\.AR
         \ibus_reader:timeout_3\.C \ibus_writer:iu_writeSBV_0\.AP
         \ibus_writer:iu_writeSBV_0\.AR \ibus_writer:iu_writeSBV_0\.C
         \ibus_writer:iu_writeSBV_1\.AP \ibus_writer:iu_writeSBV_1\.AR
         \ibus_writer:iu_writeSBV_1\.C \ibus_writer:timeout_0\.AP
         \ibus_writer:timeout_0\.AR \ibus_writer:timeout_0\.C
         \ibus_writer:timeout_1\.AP \ibus_writer:timeout_1\.AR
         \ibus_writer:timeout_1\.C \ibus_writer:timeout_2\.AP
         \ibus_writer:timeout_2\.AR \ibus_writer:timeout_2\.C
         \ibus_writer:timeout_3\.AP \ibus_writer:timeout_3\.AR
         \ibus_writer:timeout_3\.C \sp_read:counter_address_0\.AP
         \sp_read:counter_address_0\.AR \sp_read:counter_address_0\.C
         \sp_read:counter_address_1\.AP \sp_read:counter_address_1\.AR
         \sp_read:counter_address_1\.C \sp_read:counter_address_2\.AP
         \sp_read:counter_address_2\.AR \sp_read:counter_address_2\.C
         \sp_read:counter_address_3\.AP \sp_read:counter_address_3\.AR
         \sp_read:counter_address_3\.C \sp_read:counter_address_4\.AP
         \sp_read:counter_address_4\.AR \sp_read:counter_address_4\.C
         \sp_read:counter_address_5\.AP \sp_read:counter_address_5\.AR
         \sp_read:counter_address_5\.C \sp_read:counter_address_6\.AP
         \sp_read:counter_address_6\.AR \sp_read:counter_address_6\.C
         \sp_read:counter_address_7\.AP \sp_read:counter_address_7\.AR
         \sp_read:counter_address_7\.C \sp_read:counter_read_stateSBV_0\.AP
         \sp_read:counter_read_stateSBV_0\.AR
         \sp_read:counter_read_stateSBV_0\.C
         \sp_read:counter_read_stateSBV_1\.AP
         \sp_read:counter_read_stateSBV_1\.AR
         \sp_read:counter_read_stateSBV_1\.C
         \sp_read:counter_read_stateSBV_2\.AP
         \sp_read:counter_read_stateSBV_2\.AR
         \sp_read:counter_read_stateSBV_2\.C
         \sp_read:counter_read_stateSBV_3\.AP
         \sp_read:counter_read_stateSBV_3\.AR
         \sp_read:counter_read_stateSBV_3\.C \sp_read:old_phase\.D
         \sp_read:old_phase\.AP \sp_read:old_phase\.AR \sp_read:old_phase\.C
         \sp_read:reset_count_0\.D \sp_read:reset_count_0\.AP
         \sp_read:reset_count_0\.AR \sp_read:reset_count_0\.C
         \sp_read:reset_count_1\.AP \sp_read:reset_count_1\.AR
         \sp_read:reset_count_1\.C \sp_read:reset_count_2\.AP
         \sp_read:reset_count_2\.AR \sp_read:reset_count_2\.C
         address_from_pc_0.AP address_from_pc_0.AR address_from_pc_0.C
         address_from_pc_1.AP address_from_pc_1.AR address_from_pc_1.C
         address_from_pc_2.AP address_from_pc_2.AR address_from_pc_2.C
         address_from_pc_3.AP address_from_pc_3.AR address_from_pc_3.C
         address_from_pc_4.AP address_from_pc_4.AR address_from_pc_4.C
         address_from_pc_5.AP address_from_pc_5.AR address_from_pc_5.C
         address_from_pc_6.AP address_from_pc_6.AR address_from_pc_6.C
         address_from_pc_7.AP address_from_pc_7.AR address_from_pc_7.C
         ao_from_pc_ack.D ao_from_pc_ack.AP ao_from_pc_ack.AR ao_from_pc_ack.C
         ao_from_pc_ack.OE ao_to_pc_strobe.AP ao_to_pc_strobe.AR
         ao_to_pc_strobe.C bp_end_address_0.AP bp_end_address_0.AR
         bp_end_address_0.C bp_end_address_1.AP bp_end_address_1.AR
         bp_end_address_1.C bp_end_address_2.AP bp_end_address_2.AR
         bp_end_address_2.C bp_end_address_3.AP bp_end_address_3.AR
         bp_end_address_3.C bp_end_address_4.AP bp_end_address_4.AR
         bp_end_address_4.C bp_end_address_5.AP bp_end_address_5.AR
         bp_end_address_5.C bp_end_address_6.AP bp_end_address_6.AR
         bp_end_address_6.C bp_end_address_7.AP bp_end_address_7.AR
         bp_end_address_7.C bp_start_address_0.AP bp_start_address_0.AR
         bp_start_address_0.C bp_start_address_1.AP bp_start_address_1.AR
         bp_start_address_1.C bp_start_address_2.AP bp_start_address_2.AR
         bp_start_address_2.C bp_start_address_3.AP bp_start_address_3.AR
         bp_start_address_3.C bp_start_address_4.AP bp_start_address_4.AR
         bp_start_address_4.C bp_start_address_5.AP bp_start_address_5.AR
         bp_start_address_5.C bp_start_address_6.AP bp_start_address_6.AR
         bp_start_address_6.C bp_start_address_7.AP bp_start_address_7.AR
         bp_start_address_7.C bpaddr(0).AP bpaddr(0).AR bpaddr(0).C
         bpaddr(1).AP bpaddr(1).AR bpaddr(1).C bpaddr(2).AP bpaddr(2).AR
         bpaddr(2).C bpaddr(3).AP bpaddr(3).AR bpaddr(3).C bpaddr(4).AP
         bpaddr(4).AR bpaddr(4).C bpaddr(5).AP bpaddr(5).AR bpaddr(5).C
         bpaddr(6).AP bpaddr(6).AR bpaddr(6).C bpaddr(7).AP bpaddr(7).AR
         bpaddr(7).C bpaddr_dir bpaddr_tristate.AP bpaddr_tristate.AR
         bpaddr_tristate.C bpctrl(0).AP bpctrl(0).AR bpctrl(0).C bpctrl(1)
         bpctrl(10).AP bpctrl(10).AR bpctrl(10).C bpctrl(10).OE bpctrl(11).AP
         bpctrl(11).AR bpctrl(11).C bpctrl(11).OE bpctrl(2).AP bpctrl(2).AR
         bpctrl(2).C bpctrl(3).AP bpctrl(3).AR bpctrl(3).C bpctrl(4).AP
         bpctrl(4).AR bpctrl(4).C bpctrl(4).OE bpctrl(5).AP bpctrl(5).AR
         bpctrl(5).C bpctrl(5).OE bpctrl(6).AP bpctrl(6).AR bpctrl(6).C
         bpctrl(6).OE bpctrl(7).AP bpctrl(7).AR bpctrl(7).C bpctrl(7).OE
         bpctrl(8).AP bpctrl(8).AR bpctrl(8).C bpctrl(8).OE bpctrl_h_dir
         bpctrl_h_tristate bpctrl_l_dir bpctrl_l_tristate bpd(10).AP
         bpd(10).AR bpd(10).C bpd(10).OE bpd(11).AP bpd(11).AR bpd(11).C
         bpd(11).OE bpd(12).AP bpd(12).AR bpd(12).C bpd(12).OE bpd(13).AP
         bpd(13).AR bpd(13).C bpd(13).OE bpd(14).AP bpd(14).AR bpd(14).C
         bpd(14).OE bpd(15).AP bpd(15).AR bpd(15).C bpd(15).OE bpd_h_dir
         bpd_h_tristate.AP bpd_h_tristate.AR bpd_h_tristate.C bpd_l_dir
         bpd_l_tristate d(16).AP d(16).AR d(16).C d(17).AP d(17).AR d(17).C
         d(18).AP d(18).AR d(18).C d(19).AP d(19).AR d(19).C d(20).AP d(20).AR
         d(20).C d(21).AP d(21).AR d(21).C d(22).AP d(22).AR d(22).C d(23).AP
         d(23).AR d(23).C d(24).AP d(24).AR d(24).C d(25).AP d(25).AR d(25).C
         d(26).AP d(26).AR d(26).C d(27).AP d(27).AR d(27).C d(28).AP d(28).AR
         d(28).C d(29).AP d(29).AR d(29).C d(30).AP d(30).AR d(30).C d(31).AP
         d(31).AR d(31).C data_from_pc_13.AP data_from_pc_13.AR
         data_from_pc_13.C data_from_pc_14.AP data_from_pc_14.AR
         data_from_pc_14.C data_from_pc_15.AP data_from_pc_15.AR
         data_from_pc_15.C from_pc_req.AP from_pc_req.AR from_pc_req.C
         il_tristate.AP il_tristate.AR il_tristate.C led1.AP led1.AR led1.C
         led2 led3 loopback_state.T loopback_state.AP loopback_state.AR
         loopback_state.C reset sensor_address_0.AP sensor_address_0.AR
         sensor_address_0.C sensor_address_1.AP sensor_address_1.AR
         sensor_address_1.C sensor_address_2.AP sensor_address_2.AR
         sensor_address_2.C sensor_address_3.AP sensor_address_3.AR
         sensor_address_3.C sensor_address_4.AP sensor_address_4.AR
         sensor_address_4.C sensor_address_5.AP sensor_address_5.AR
         sensor_address_5.C sensor_address_6.AP sensor_address_6.AR
         sensor_address_6.C sensor_address_7.AP sensor_address_7.AR
         sensor_address_7.C sensor_data_0.AP sensor_data_0.AR sensor_data_0.C
         sensor_data_1.AP sensor_data_1.AR sensor_data_1.C sensor_data_10.AP
         sensor_data_10.AR sensor_data_10.C sensor_data_11.AP
         sensor_data_11.AR sensor_data_11.C sensor_data_12.AP
         sensor_data_12.AR sensor_data_12.C sensor_data_13.AP
         sensor_data_13.AR sensor_data_13.C sensor_data_14.AP
         sensor_data_14.AR sensor_data_14.C sensor_data_15.AP
         sensor_data_15.AR sensor_data_15.C sensor_data_2.AP sensor_data_2.AR
         sensor_data_2.C sensor_data_3.AP sensor_data_3.AR sensor_data_3.C
         sensor_data_4.AP sensor_data_4.AR sensor_data_4.C sensor_data_5.AP
         sensor_data_5.AR sensor_data_5.C sensor_data_6.AP sensor_data_6.AR
         sensor_data_6.C sensor_data_7.AP sensor_data_7.AR sensor_data_7.C
         sensor_data_8.AP sensor_data_8.AR sensor_data_8.C sensor_data_9.AP
         sensor_data_9.AR sensor_data_9.C sensor_to_bp_read_ack.AP
         sensor_to_bp_read_ack.AR sensor_to_bp_read_ack.C
         sensor_to_bp_read_req.D sensor_to_bp_read_req.AP
         sensor_to_bp_read_req.AR sensor_to_bp_read_req.C
         sensor_to_ibus_req.AP sensor_to_ibus_req.AR sensor_to_ibus_req.C
         this_chip_selected.AP this_chip_selected.AR this_chip_selected.C
         to_pc_ack.AP to_pc_ack.AR to_pc_ack.C tristate_stateSBV_0.D
         tristate_stateSBV_0.AP tristate_stateSBV_0.AR tristate_stateSBV_0.C
         write_to_bp_ack.AP write_to_bp_ack.AR write_to_bp_ack.C



Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully  
----------------------------------------------------------------------------
PLD Optimizer Software:       MINOPT.EXE     01/NOV/1999  [v4.02 ] 6.2 IR 27

LOGIC MINIMIZATION         ()

Messages:


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully
----------------------------------------------------------------------------
PLD Optimizer Software:       DSGNOPT.EXE    31/03/2000  [v4.02 ] 6.2 IR 27

OPTIMIZATION OPTIONS       (15:40:39)

Messages:
  Information: Sum-Splitting output logic for signal \sp_read:counter_address_7\.
  Information: Sum-Splitting output logic for signal \sp_read:counter_address_6\.
  Information: Sum-Splitting output logic for signal \sp_read:counter_address_5\.
  Information: Sum-Splitting output logic for signal \sp_read:counter_address_4\.
  Information: Sum-Splitting output logic for signal \sp_read:counter_address_3\.
  Information: Sum-Splitting output logic for signal \sp_read:counter_address_2\.
  Information: Sum-Splitting output logic for signal \sp_read:counter_address_1\.
  Information: Sum-Splitting output logic for signal \sp_read:counter_address_0\.
  Information: Sum-Splitting output logic for signal \ibus_reader:timeout_1\.
  Information: Optimizing Banked Preset/Reset requirements.
  Information: Selecting T register equation as minimal for signal \bp_io:bp_access_stateSBV_0\
  Information: Selecting T register equation as minimal for signal \bp_io:bp_access_stateSBV_1\
  Information: Selecting T register equation as minimal for signal \bp_io:bp_access_stateSBV_2\
  Information: Selecting D register equation as minimal for signal \bp_io:timeout_0\
  Information: Selecting T register equation as minimal for signal \bp_io:timeout_1\
  Information: Selecting T register equation as minimal for signal \bp_io:timeout_2\
  Information: Selecting T register equation as minimal for signal \ibus_reader:il_read_stateSBV_0\
  Information: Selecting T register equation as minimal for signal \ibus_reader:il_read_stateSBV_1\
  Information: Selecting T register equation as minimal for signal \ibus_reader:il_read_stateSBV_2\
  Information: Selecting D register equation as minimal for signal \ibus_reader:this_is_a_ctrl_transaction\
  Information: Selecting D register equation as minimal for signal \ibus_reader:timeout_0\
  Information: Selecting D register equation as minimal for signal \ibus_reader:timeout_1\
  Information: Selecting T register equation as minimal for signal \ibus_reader:timeout_2\
  Information: Selecting D register equation as minimal for signal \ibus_reader:timeout_3\
  Information: Selecting T register equation as minimal for signal \ibus_writer:iu_writeSBV_0\
  Information: Selecting T register equation as minimal for signal \ibus_writer:iu_writeSBV_1\
  Information: Selecting D register equation as minimal for signal \ibus_writer:timeout_0\
  Information: Selecting T register equation as minimal for signal \ibus_writer:timeout_1\
  Information: Selecting T register equation as minimal for signal \ibus_writer:timeout_2\
  Information: Selecting T register equation as minimal for signal \ibus_writer:timeout_3\
  Information: Selecting D register equation as minimal for signal \sp_read:counter_address_0\
  Information: Selecting D register equation as minimal for signal \sp_read:counter_address_1\
  Information: Selecting D register equation as minimal for signal \sp_read:counter_address_2\
  Information: Selecting D register equation as minimal for signal \sp_read:counter_address_3\
  Information: Selecting D register equation as minimal for signal \sp_read:counter_address_4\
  Information: Selecting D register equation as minimal for signal \sp_read:counter_address_5\
  Information: Selecting D register equation as minimal for signal \sp_read:counter_address_6\
  Information: Selecting D register equation as minimal for signal \sp_read:counter_address_7\
  Information: Selecting D register equation as minimal for signal \sp_read:counter_read_stateSBV_0\
  Information: Selecting T register equation as minimal for signal \sp_read:counter_read_stateSBV_1\
  Information: Selecting D register equation as minimal for signal \sp_read:counter_read_stateSBV_2\
  Information: Selecting D register equation as minimal for signal \sp_read:counter_read_stateSBV_3\
  Information: Selecting D register equation as minimal for signal \sp_read:reset_count_1\
  Information: Selecting T register equation as minimal for signal \sp_read:reset_count_2\
  Information: Selecting T register equation as minimal for signal address_from_pc_0
  Information: Selecting T register equation as minimal for signal address_from_pc_1
  Information: Selecting T register equation as minimal for signal address_from_pc_2
  Information: Selecting T register equation as minimal for signal address_from_pc_3
  Information: Selecting T register equation as minimal for signal address_from_pc_4
  Information: Selecting T register equation as minimal for signal address_from_pc_5
  Information: Selecting T register equation as minimal for signal address_from_pc_6
  Information: Selecting T register equation as minimal for signal address_from_pc_7
  Information: Selecting T register equation as minimal for signal bp_end_address_0
  Information: Selecting T register equation as minimal for signal bp_end_address_1
  Information: Selecting T register equation as minimal for signal bp_end_address_2
  Information: Selecting T register equation as minimal for signal bp_end_address_3
  Information: Selecting T register equation as minimal for signal bp_end_address_4
  Information: Selecting T register equation as minimal for signal bp_end_address_5
  Information: Selecting T register equation as minimal for signal bp_end_address_6
  Information: Selecting T register equation as minimal for signal bp_end_address_7
  Information: Selecting T register equation as minimal for signal bp_start_address_0
  Information: Selecting T register equation as minimal for signal bp_start_address_1
  Information: Selecting T register equation as minimal for signal bp_start_address_2
  Information: Selecting T register equation as minimal for signal bp_start_address_3
  Information: Selecting T register equation as minimal for signal bp_start_address_4
  Information: Selecting T register equation as minimal for signal bp_start_address_5
  Information: Selecting T register equation as minimal for signal bp_start_address_6
  Information: Selecting T register equation as minimal for signal bp_start_address_7
  Information: Selecting T register equation as minimal for signal data_from_pc_13
  Information: Selecting T register equation as minimal for signal data_from_pc_14
  Information: Selecting T register equation as minimal for signal data_from_pc_15
  Information: Selecting D register equation as minimal for signal from_pc_req
  Information: Selecting D register equation as minimal for signal il_tristate
  Information: Selecting T register equation as minimal for signal sensor_address_0
  Information: Selecting T register equation as minimal for signal sensor_address_1
  Information: Selecting T register equation as minimal for signal sensor_address_2
  Information: Selecting T register equation as minimal for signal sensor_address_3
  Information: Selecting T register equation as minimal for signal sensor_address_4
  Information: Selecting T register equation as minimal for signal sensor_address_5
  Information: Selecting T register equation as minimal for signal sensor_address_6
  Information: Selecting T register equation as minimal for signal sensor_address_7
  Information: Selecting T register equation as minimal for signal sensor_data_0
  Information: Selecting T register equation as minimal for signal sensor_data_1
  Information: Selecting T register equation as minimal for signal sensor_data_10
  Information: Selecting T register equation as minimal for signal sensor_data_11
  Information: Selecting T register equation as minimal for signal sensor_data_12
  Information: Selecting T register equation as minimal for signal sensor_data_13
  Information: Selecting T register equation as minimal for signal sensor_data_14
  Information: Selecting T register equation as minimal for signal sensor_data_15
  Information: Selecting T register equation as minimal for signal sensor_data_2
  Information: Selecting T register equation as minimal for signal sensor_data_3
  Information: Selecting T register equation as minimal for signal sensor_data_4
  Information: Selecting T register equation as minimal for signal sensor_data_5
  Information: Selecting T register equation as minimal for signal sensor_data_6
  Information: Selecting T register equation as minimal for signal sensor_data_7
  Information: Selecting T register equation as minimal for signal sensor_data_8
  Information: Selecting T register equation as minimal for signal sensor_data_9
  Information: Selecting D register equation as minimal for signal sensor_to_bp_read_ack
  Information: Selecting D register equation as minimal for signal sensor_to_ibus_req
  Information: Selecting D register equation as minimal for signal this_chip_selected
  Information: Selecting D register equation as minimal for signal to_pc_ack
  Information: Selecting D register equation as minimal for signal write_to_bp_ack
  Information: Selecting D register equation as minimal for signal \sp_read:reset_count_0\
  Information: Selecting T register equation as minimal for signal loopback_state
  Information: Selecting D register equation as minimal for signal sensor_to_bp_read_req
  Information: Selecting D register equation as minimal for signal tristate_stateSBV_0
  Information: Selecting T register equation as minimal for signal bpd(15)
  Information: Selecting T register equation as minimal for signal bpd(14)
  Information: Selecting T register equation as minimal for signal bpd(13)
  Information: Selecting T register equation as minimal for signal bpd(12)
  Information: Selecting T register equation as minimal for signal bpd(11)
  Information: Selecting T register equation as minimal for signal bpd(10)
  Information: Selecting T register equation as minimal for signal d(31)
  Information: Selecting T register equation as minimal for signal d(30)
  Information: Selecting T register equation as minimal for signal d(29)
  Information: Selecting T register equation as minimal for signal d(28)
  Information: Selecting T register equation as minimal for signal d(27)
  Information: Selecting T register equation as minimal for signal d(26)
  Information: Selecting T register equation as minimal for signal d(25)
  Information: Selecting T register equation as minimal for signal d(24)
  Information: Selecting T register equation as minimal for signal d(23)
  Information: Selecting T register equation as minimal for signal d(22)
  Information: Selecting T register equation as minimal for signal d(21)
  Information: Selecting T register equation as minimal for signal d(20)
  Information: Selecting T register equation as minimal for signal d(19)
  Information: Selecting T register equation as minimal for signal d(18)
  Information: Selecting T register equation as minimal for signal d(17)
  Information: Selecting T register equation as minimal for signal d(16)
  Information: Selecting D register equation as minimal for signal ao_from_pc_ack
  Information: Selecting D register equation as minimal for signal ao_to_pc_strobe
  Information: Selecting D register equation as minimal for signal led1
  Information: Selecting D register equation as minimal for signal bpaddr_tristate
  Information: Selecting D register equation as minimal for signal bpd_h_tristate
  Information: Selecting T register equation as minimal for signal bpaddr(7)
  Information: Selecting T register equation as minimal for signal bpaddr(6)
  Information: Selecting T register equation as minimal for signal bpaddr(5)
  Information: Selecting T register equation as minimal for signal bpaddr(4)
  Information: Selecting T register equation as minimal for signal bpaddr(3)
  Information: Selecting T register equation as minimal for signal bpaddr(2)
  Information: Selecting T register equation as minimal for signal bpaddr(1)
  Information: Selecting T register equation as minimal for signal bpaddr(0)
  Information: Selecting T register equation as minimal for signal bpctrl(11)
  Information: Selecting T register equation as minimal for signal bpctrl(10)
  Information: Selecting T register equation as minimal for signal bpctrl(8)
  Information: Selecting T register equation as minimal for signal bpctrl(7)
  Information: Selecting T register equation as minimal for signal bpctrl(6)
  Information: Selecting T register equation as minimal for signal bpctrl(5)
  Information: Selecting T register equation as minimal for signal bpctrl(4)
  Information: Selecting D register equation as minimal for signal bpctrl(3)
  Information: Selecting D register equation as minimal for signal bpctrl(2)
  Information: Selecting D register equation as minimal for signal bpctrl(0)
  Information: Selecting D register equation as minimal for signal \sp_read:old_phase\
  Information: Optimizing logic without changing polarity for signals:
         \bp_io:bp_access_stateSBV_0\.T \bp_io:bp_access_stateSBV_1\.T
         \bp_io:bp_access_stateSBV_2\.T \bp_io:timeout_0\.D
         \bp_io:timeout_1\.T \bp_io:timeout_2\.T
         \ibus_reader:il_read_stateSBV_0\.T \ibus_reader:il_read_stateSBV_1\.T
         \ibus_reader:il_read_stateSBV_2\.T
         \ibus_reader:this_is_a_ctrl_transaction\.D \ibus_reader:timeout_0\.D
         \ibus_reader:timeout_1\.D \ibus_reader:timeout_2\.T
         \ibus_reader:timeout_3\.D \ibus_writer:iu_writeSBV_0\.T
         \ibus_writer:iu_writeSBV_1\.T \ibus_writer:timeout_0\.D
         \ibus_writer:timeout_1\.T \ibus_writer:timeout_2\.T
         \ibus_writer:timeout_3\.T \sp_read:cmp_vv_us_MODGEN_10\
         \sp_read:counter_address_0\.D \sp_read:counter_address_1\.D
         \sp_read:counter_address_2\.D \sp_read:counter_address_3\.D
         \sp_read:counter_address_4\.D \sp_read:counter_address_5\.D
         \sp_read:counter_address_6\.D \sp_read:counter_address_7\.D
         \sp_read:counter_read_stateSBV_0\.D
         \sp_read:counter_read_stateSBV_1\.T
         \sp_read:counter_read_stateSBV_2\.D
         \sp_read:counter_read_stateSBV_3\.D \sp_read:old_phase\.D
         \sp_read:reset_count_0\.D \sp_read:reset_count_1\.D
         \sp_read:reset_count_2\.T address_from_pc_0.T address_from_pc_1.T
         address_from_pc_2.T address_from_pc_3.T address_from_pc_4.T
         address_from_pc_5.T address_from_pc_6.T address_from_pc_7.T
         ao_from_pc_ack.D ao_to_pc_strobe.D bp_end_address_0.T
         bp_end_address_1.T bp_end_address_2.T bp_end_address_3.T
         bp_end_address_4.T bp_end_address_5.T bp_end_address_6.T
         bp_end_address_7.T bp_start_address_0.T bp_start_address_1.T
         bp_start_address_2.T bp_start_address_3.T bp_start_address_4.T
         bp_start_address_5.T bp_start_address_6.T bp_start_address_7.T
         bpaddr(0).T bpaddr(1).T bpaddr(2).T bpaddr(3).T bpaddr(4).T
         bpaddr(5).T bpaddr(6).T bpaddr(7).T bpaddr_tristate.D bpctrl(0).D
         bpctrl(10).T bpctrl(11).T bpctrl(2).D bpctrl(3).D bpctrl(4).T
         bpctrl(5).T bpctrl(6).T bpctrl(7).T bpctrl(8).T bpd(10).T bpd(11).T
         bpd(12).T bpd(13).T bpd(14).T bpd(15).T bpd_h_tristate.D d(16).T
         d(17).T d(18).T d(19).T d(20).T d(21).T d(22).T d(23).T d(24).T
         d(25).T d(26).T d(27).T d(28).T d(29).T d(30).T d(31).T
         data_from_pc_13.T data_from_pc_14.T data_from_pc_15.T from_pc_req.D
         il_tristate.D led1.D loopback_state.T sensor_address_0.T
         sensor_address_1.T sensor_address_2.T sensor_address_3.T
         sensor_address_4.T sensor_address_5.T sensor_address_6.T
         sensor_address_7.T sensor_data_0.T sensor_data_1.T sensor_data_10.T
         sensor_data_11.T sensor_data_12.T sensor_data_13.T sensor_data_14.T
         sensor_data_15.T sensor_data_2.T sensor_data_3.T sensor_data_4.T
         sensor_data_5.T sensor_data_6.T sensor_data_7.T sensor_data_8.T
         sensor_data_9.T sensor_to_bp_read_ack.D sensor_to_bp_read_req.D
         sensor_to_ibus_req.D this_chip_selected.D to_pc_ack.D
         tristate_stateSBV_0.D write_to_bp_ack.D

  Information: Optimizing logic using best output polarity for signals:
         S_1 S_10 S_11 S_12 S_13 S_14 S_15 S_16 S_17 S_18 S_2 S_3 S_4 S_5 S_6
         S_7 S_8 S_9

  Information: Selected logic optimization OFF for signals:
         \bp_io:bp_access_stateSBV_0\.AP \bp_io:bp_access_stateSBV_0\.AR
         \bp_io:bp_access_stateSBV_0\.C \bp_io:bp_access_stateSBV_1\.AP
         \bp_io:bp_access_stateSBV_1\.AR \bp_io:bp_access_stateSBV_1\.C
         \bp_io:bp_access_stateSBV_2\.AP \bp_io:bp_access_stateSBV_2\.AR
         \bp_io:bp_access_stateSBV_2\.C \bp_io:timeout_0\.AP
         \bp_io:timeout_0\.AR \bp_io:timeout_0\.C \bp_io:timeout_1\.AP
         \bp_io:timeout_1\.AR \bp_io:timeout_1\.C \bp_io:timeout_2\.AP
         \bp_io:timeout_2\.AR \bp_io:timeout_2\.C
         \ibus_reader:il_read_stateSBV_0\.AP
         \ibus_reader:il_read_stateSBV_0\.AR
         \ibus_reader:il_read_stateSBV_0\.C
         \ibus_reader:il_read_stateSBV_1\.AP
         \ibus_reader:il_read_stateSBV_1\.AR
         \ibus_reader:il_read_stateSBV_1\.C
         \ibus_reader:il_read_stateSBV_2\.AP
         \ibus_reader:il_read_stateSBV_2\.AR
         \ibus_reader:il_read_stateSBV_2\.C
         \ibus_reader:this_is_a_ctrl_transaction\.AP
         \ibus_reader:this_is_a_ctrl_transaction\.AR
         \ibus_reader:this_is_a_ctrl_transaction\.C \ibus_reader:timeout_0\.AP
         \ibus_reader:timeout_0\.AR \ibus_reader:timeout_0\.C
         \ibus_reader:timeout_1\.AP \ibus_reader:timeout_1\.AR
         \ibus_reader:timeout_1\.C \ibus_reader:timeout_2\.AP
         \ibus_reader:timeout_2\.AR \ibus_reader:timeout_2\.C
         \ibus_reader:timeout_3\.AP \ibus_reader:timeout_3\.AR
         \ibus_reader:timeout_3\.C \ibus_writer:iu_writeSBV_0\.AP
         \ibus_writer:iu_writeSBV_0\.AR \ibus_writer:iu_writeSBV_0\.C
         \ibus_writer:iu_writeSBV_1\.AP \ibus_writer:iu_writeSBV_1\.AR
         \ibus_writer:iu_writeSBV_1\.C \ibus_writer:timeout_0\.AP
         \ibus_writer:timeout_0\.AR \ibus_writer:timeout_0\.C
         \ibus_writer:timeout_1\.AP \ibus_writer:timeout_1\.AR
         \ibus_writer:timeout_1\.C \ibus_writer:timeout_2\.AP
         \ibus_writer:timeout_2\.AR \ibus_writer:timeout_2\.C
         \ibus_writer:timeout_3\.AP \ibus_writer:timeout_3\.AR
         \ibus_writer:timeout_3\.C \sp_read:counter_address_0\.AP
         \sp_read:counter_address_0\.AR \sp_read:counter_address_0\.C
         \sp_read:counter_address_1\.AP \sp_read:counter_address_1\.AR
         \sp_read:counter_address_1\.C \sp_read:counter_address_2\.AP
         \sp_read:counter_address_2\.AR \sp_read:counter_address_2\.C
         \sp_read:counter_address_3\.AP \sp_read:counter_address_3\.AR
         \sp_read:counter_address_3\.C \sp_read:counter_address_4\.AP
         \sp_read:counter_address_4\.AR \sp_read:counter_address_4\.C
         \sp_read:counter_address_5\.AP \sp_read:counter_address_5\.AR
         \sp_read:counter_address_5\.C \sp_read:counter_address_6\.AP
         \sp_read:counter_address_6\.AR \sp_read:counter_address_6\.C
         \sp_read:counter_address_7\.AP \sp_read:counter_address_7\.AR
         \sp_read:counter_address_7\.C \sp_read:counter_read_stateSBV_0\.AP
         \sp_read:counter_read_stateSBV_0\.AR
         \sp_read:counter_read_stateSBV_0\.C
         \sp_read:counter_read_stateSBV_1\.AP
         \sp_read:counter_read_stateSBV_1\.AR
         \sp_read:counter_read_stateSBV_1\.C
         \sp_read:counter_read_stateSBV_2\.AP
         \sp_read:counter_read_stateSBV_2\.AR
         \sp_read:counter_read_stateSBV_2\.C
         \sp_read:counter_read_stateSBV_3\.AP
         \sp_read:counter_read_stateSBV_3\.AR
         \sp_read:counter_read_stateSBV_3\.C \sp_read:old_phase\.AP
         \sp_read:old_phase\.AR \sp_read:old_phase\.C
         \sp_read:reset_count_0\.AP \sp_read:reset_count_0\.AR
         \sp_read:reset_count_0\.C \sp_read:reset_count_1\.AP
         \sp_read:reset_count_1\.AR \sp_read:reset_count_1\.C
         \sp_read:reset_count_2\.AP \sp_read:reset_count_2\.AR
         \sp_read:reset_count_2\.C address_from_pc_0.AP address_from_pc_0.AR
         address_from_pc_0.C address_from_pc_1.AP address_from_pc_1.AR
         address_from_pc_1.C address_from_pc_2.AP address_from_pc_2.AR
         address_from_pc_2.C address_from_pc_3.AP address_from_pc_3.AR
         address_from_pc_3.C address_from_pc_4.AP address_from_pc_4.AR
         address_from_pc_4.C address_from_pc_5.AP address_from_pc_5.AR
         address_from_pc_5.C address_from_pc_6.AP address_from_pc_6.AR
         address_from_pc_6.C address_from_pc_7.AP address_from_pc_7.AR
         address_from_pc_7.C ao_from_pc_ack.AP ao_from_pc_ack.AR
         ao_from_pc_ack.C ao_from_pc_ack.OE ao_to_pc_strobe.AP
         ao_to_pc_strobe.AR ao_to_pc_strobe.C bp_end_address_0.AP
         bp_end_address_0.AR bp_end_address_0.C bp_end_address_1.AP
         bp_end_address_1.AR bp_end_address_1.C bp_end_address_2.AP
         bp_end_address_2.AR bp_end_address_2.C bp_end_address_3.AP
         bp_end_address_3.AR bp_end_address_3.C bp_end_address_4.AP
         bp_end_address_4.AR bp_end_address_4.C bp_end_address_5.AP
         bp_end_address_5.AR bp_end_address_5.C bp_end_address_6.AP
         bp_end_address_6.AR bp_end_address_6.C bp_end_address_7.AP
         bp_end_address_7.AR bp_end_address_7.C bp_start_address_0.AP
         bp_start_address_0.AR bp_start_address_0.C bp_start_address_1.AP
         bp_start_address_1.AR bp_start_address_1.C bp_start_address_2.AP
         bp_start_address_2.AR bp_start_address_2.C bp_start_address_3.AP
         bp_start_address_3.AR bp_start_address_3.C bp_start_address_4.AP
         bp_start_address_4.AR bp_start_address_4.C bp_start_address_5.AP
         bp_start_address_5.AR bp_start_address_5.C bp_start_address_6.AP
         bp_start_address_6.AR bp_start_address_6.C bp_start_address_7.AP
         bp_start_address_7.AR bp_start_address_7.C bpaddr(0).AP bpaddr(0).AR
         bpaddr(0).C bpaddr(1).AP bpaddr(1).AR bpaddr(1).C bpaddr(2).AP
         bpaddr(2).AR bpaddr(2).C bpaddr(3).AP bpaddr(3).AR bpaddr(3).C
         bpaddr(4).AP bpaddr(4).AR bpaddr(4).C bpaddr(5).AP bpaddr(5).AR
         bpaddr(5).C bpaddr(6).AP bpaddr(6).AR bpaddr(6).C bpaddr(7).AP
         bpaddr(7).AR bpaddr(7).C bpaddr_dir bpaddr_tristate.AP
         bpaddr_tristate.AR bpaddr_tristate.C bpctrl(0).AP bpctrl(0).AR
         bpctrl(0).C bpctrl(1) bpctrl(10).AP bpctrl(10).AR bpctrl(10).C
         bpctrl(10).OE bpctrl(11).AP bpctrl(11).AR bpctrl(11).C bpctrl(11).OE
         bpctrl(2).AP bpctrl(2).AR bpctrl(2).C bpctrl(3).AP bpctrl(3).AR
         bpctrl(3).C bpctrl(4).AP bpctrl(4).AR bpctrl(4).C bpctrl(4).OE
         bpctrl(5).AP bpctrl(5).AR bpctrl(5).C bpctrl(5).OE bpctrl(6).AP
         bpctrl(6).AR bpctrl(6).C bpctrl(6).OE bpctrl(7).AP bpctrl(7).AR
         bpctrl(7).C bpctrl(7).OE bpctrl(8).AP bpctrl(8).AR bpctrl(8).C
         bpctrl(8).OE bpctrl_h_dir bpctrl_h_tristate bpctrl_l_dir
         bpctrl_l_tristate bpd(10).AP bpd(10).AR bpd(10).C bpd(10).OE
         bpd(11).AP bpd(11).AR bpd(11).C bpd(11).OE bpd(12).AP bpd(12).AR
         bpd(12).C bpd(12).OE bpd(13).AP bpd(13).AR bpd(13).C bpd(13).OE
         bpd(14).AP bpd(14).AR bpd(14).C bpd(14).OE bpd(15).AP bpd(15).AR
         bpd(15).C bpd(15).OE bpd_h_dir bpd_h_tristate.AP bpd_h_tristate.AR
         bpd_h_tristate.C bpd_l_dir bpd_l_tristate d(16).AP d(16).AR d(16).C
         d(17).AP d(17).AR d(17).C d(18).AP d(18).AR d(18).C d(19).AP d(19).AR
         d(19).C d(20).AP d(20).AR d(20).C d(21).AP d(21).AR d(21).C d(22).AP
         d(22).AR d(22).C d(23).AP d(23).AR d(23).C d(24).AP d(24).AR d(24).C
         d(25).AP d(25).AR d(25).C d(26).AP d(26).AR d(26).C d(27).AP d(27).AR
         d(27).C d(28).AP d(28).AR d(28).C d(29).AP d(29).AR d(29).C d(30).AP
         d(30).AR d(30).C d(31).AP d(31).AR d(31).C data_from_pc_13.AP
         data_from_pc_13.AR data_from_pc_13.C data_from_pc_14.AP
         data_from_pc_14.AR data_from_pc_14.C data_from_pc_15.AP
         data_from_pc_15.AR data_from_pc_15.C from_pc_req.AP from_pc_req.AR
         from_pc_req.C il_tristate.AP il_tristate.AR il_tristate.C led1.AP
         led1.AR led1.C led2 led3 loopback_state.AP loopback_state.AR
         loopback_state.C reset sensor_address_0.AP sensor_address_0.AR
         sensor_address_0.C sensor_address_1.AP sensor_address_1.AR
         sensor_address_1.C sensor_address_2.AP sensor_address_2.AR
         sensor_address_2.C sensor_address_3.AP sensor_address_3.AR
         sensor_address_3.C sensor_address_4.AP sensor_address_4.AR
         sensor_address_4.C sensor_address_5.AP sensor_address_5.AR
         sensor_address_5.C sensor_address_6.AP sensor_address_6.AR
         sensor_address_6.C sensor_address_7.AP sensor_address_7.AR
         sensor_address_7.C sensor_data_0.AP sensor_data_0.AR sensor_data_0.C
         sensor_data_1.AP sensor_data_1.AR sensor_data_1.C sensor_data_10.AP
         sensor_data_10.AR sensor_data_10.C sensor_data_11.AP
         sensor_data_11.AR sensor_data_11.C sensor_data_12.AP
         sensor_data_12.AR sensor_data_12.C sensor_data_13.AP
         sensor_data_13.AR sensor_data_13.C sensor_data_14.AP
         sensor_data_14.AR sensor_data_14.C sensor_data_15.AP
         sensor_data_15.AR sensor_data_15.C sensor_data_2.AP sensor_data_2.AR
         sensor_data_2.C sensor_data_3.AP sensor_data_3.AR sensor_data_3.C
         sensor_data_4.AP sensor_data_4.AR sensor_data_4.C sensor_data_5.AP
         sensor_data_5.AR sensor_data_5.C sensor_data_6.AP sensor_data_6.AR
         sensor_data_6.C sensor_data_7.AP sensor_data_7.AR sensor_data_7.C
         sensor_data_8.AP sensor_data_8.AR sensor_data_8.C sensor_data_9.AP
         sensor_data_9.AR sensor_data_9.C sensor_to_bp_read_ack.AP
         sensor_to_bp_read_ack.AR sensor_to_bp_read_ack.C
         sensor_to_bp_read_req.AP sensor_to_bp_read_req.AR
         sensor_to_bp_read_req.C sensor_to_ibus_req.AP sensor_to_ibus_req.AR
         sensor_to_ibus_req.C this_chip_selected.AP this_chip_selected.AR
         this_chip_selected.C to_pc_ack.AP to_pc_ack.AR to_pc_ack.C
         tristate_stateSBV_0.AP tristate_stateSBV_0.AR tristate_stateSBV_0.C
         write_to_bp_ack.AP write_to_bp_ack.AR write_to_bp_ack.C



Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully  
----------------------------------------------------------------------------
PLD Optimizer Software:       MINOPT.EXE     01/NOV/1999  [v4.02 ] 6.2 IR 27

LOGIC MINIMIZATION         ()

Messages:


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully
----------------------------------------------------------------------------
PLD Optimizer Software:       DSGNOPT.EXE    31/03/2000  [v4.02 ] 6.2 IR 27

OPTIMIZATION OPTIONS       (15:40:39)

Messages:


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully  
----------------------------------------------------------------------------
PLD Compiler Software:        C37KFIT.EXE    22/DEC/2000  [v4.02 ] 6.2 IR 27

DESIGN EQUATIONS           (15:40:39)


    S_1 =
          \sp_read:counter_address_0\.Q * \sp_read:counter_address_1\.Q * 
          \sp_read:counter_address_2\.Q * \sp_read:counter_address_3\.Q * 
          \sp_read:counter_address_4\.Q * \sp_read:counter_address_5\.Q * 
          \sp_read:counter_address_6\.Q * /\sp_read:counter_address_7\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          \sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q 
        + \sp_read:counter_address_7\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * /bp_end_address_0.Q * 
          /bp_end_address_1.Q * /bp_end_address_2.Q * /bp_end_address_3.Q * 
          /bp_end_address_4.Q * /bp_end_address_5.Q * /bp_end_address_6.Q * 
          /bp_end_address_7.Q 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          bp_end_address_7.Q * bp_start_address_7.Q * hva_chassis_en_l * 
          sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          bp_end_address_6.Q * bp_start_address_7.Q * hva_chassis_en_l * 
          sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          bp_end_address_5.Q * bp_start_address_7.Q * hva_chassis_en_l * 
          sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          bp_end_address_4.Q * bp_start_address_7.Q * hva_chassis_en_l * 
          sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          bp_end_address_3.Q * bp_start_address_7.Q * hva_chassis_en_l * 
          sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          bp_end_address_0.Q * bp_start_address_7.Q * hva_chassis_en_l * 
          sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          bp_end_address_7.Q * bp_start_address_7.Q * hva_chassis_en_l * 
          /sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          bp_end_address_6.Q * bp_start_address_7.Q * hva_chassis_en_l * 
          /sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          bp_end_address_5.Q * bp_start_address_7.Q * hva_chassis_en_l * 
          /sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          bp_end_address_4.Q * bp_start_address_7.Q * hva_chassis_en_l * 
          /sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          bp_end_address_3.Q * bp_start_address_7.Q * hva_chassis_en_l * 
          /sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          bp_end_address_2.Q * bp_start_address_7.Q * hva_chassis_en_l * 
          /sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          bp_end_address_1.Q * bp_start_address_7.Q * hva_chassis_en_l * 
          /sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          bp_end_address_0.Q * bp_start_address_7.Q * hva_chassis_en_l * 
          /sinphase_zeros 

    S_10 =
          /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          bp_end_address_6.Q * bp_start_address_3.Q * hva_chassis_en_l * 
          sinphase_zeros 
        + \sp_read:counter_address_0\.Q * \sp_read:counter_address_1\.Q * 
          \sp_read:counter_address_2\.Q * /\sp_read:counter_address_3\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          \sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q 
        + \sp_read:counter_address_3\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * \sp_read:old_phase\.Q * 
          sinphase_zeros 
        + \sp_read:counter_address_3\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * /\sp_read:old_phase\.Q * 
          /sinphase_zeros 
        + /\sp_read:counter_address_0\.Q * \sp_read:counter_address_3\.Q * 
          \sp_read:counter_read_stateSBV_2\.Q 
        + /\sp_read:counter_address_1\.Q * \sp_read:counter_address_3\.Q * 
          \sp_read:counter_read_stateSBV_2\.Q 
        + /\sp_read:counter_address_2\.Q * \sp_read:counter_address_3\.Q * 
          \sp_read:counter_read_stateSBV_2\.Q 
        + \sp_read:counter_address_3\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * /hva_chassis_en_l 
        + \sp_read:counter_address_3\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q 
        + \sp_read:counter_address_3\.Q * 
          \sp_read:counter_read_stateSBV_1\.Q 
        + \sp_read:counter_address_3\.Q * 
          \sp_read:counter_read_stateSBV_0\.Q 

    S_11 =
          \sp_read:counter_address_2\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * /bp_end_address_0.Q * 
          /bp_end_address_1.Q * /bp_end_address_2.Q * /bp_end_address_3.Q * 
          /bp_end_address_4.Q * /bp_end_address_5.Q * /bp_end_address_6.Q * 
          /bp_end_address_7.Q 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          bp_end_address_6.Q * bp_start_address_2.Q * hva_chassis_en_l * 
          sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          bp_end_address_5.Q * bp_start_address_2.Q * hva_chassis_en_l * 
          sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          bp_end_address_4.Q * bp_start_address_2.Q * hva_chassis_en_l * 
          sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          bp_end_address_3.Q * bp_start_address_2.Q * hva_chassis_en_l * 
          sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          bp_end_address_2.Q * bp_start_address_2.Q * hva_chassis_en_l * 
          sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          bp_end_address_1.Q * bp_start_address_2.Q * hva_chassis_en_l * 
          sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          bp_end_address_0.Q * bp_start_address_2.Q * hva_chassis_en_l * 
          sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          bp_end_address_7.Q * bp_start_address_2.Q * hva_chassis_en_l * 
          /sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          bp_end_address_6.Q * bp_start_address_2.Q * hva_chassis_en_l * 
          /sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          bp_end_address_5.Q * bp_start_address_2.Q * hva_chassis_en_l * 
          /sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          bp_end_address_4.Q * bp_start_address_2.Q * hva_chassis_en_l * 
          /sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          bp_end_address_3.Q * bp_start_address_2.Q * hva_chassis_en_l * 
          /sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          bp_end_address_2.Q * bp_start_address_2.Q * hva_chassis_en_l * 
          /sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          bp_end_address_1.Q * bp_start_address_2.Q * hva_chassis_en_l * 
          /sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          bp_end_address_0.Q * bp_start_address_2.Q * hva_chassis_en_l * 
          /sinphase_zeros 

    S_12 =
          /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          bp_end_address_7.Q * bp_start_address_2.Q * hva_chassis_en_l * 
          sinphase_zeros 
        + \sp_read:counter_address_0\.Q * \sp_read:counter_address_1\.Q * 
          /\sp_read:counter_address_2\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          \sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q 
        + \sp_read:counter_address_2\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * \sp_read:old_phase\.Q * 
          sinphase_zeros 
        + \sp_read:counter_address_2\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * /\sp_read:old_phase\.Q * 
          /sinphase_zeros 
        + /\sp_read:counter_address_0\.Q * \sp_read:counter_address_2\.Q * 
          \sp_read:counter_read_stateSBV_2\.Q 
        + /\sp_read:counter_address_1\.Q * \sp_read:counter_address_2\.Q * 
          \sp_read:counter_read_stateSBV_2\.Q 
        + \sp_read:counter_address_2\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * /hva_chassis_en_l 
        + \sp_read:counter_address_2\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q 
        + \sp_read:counter_address_2\.Q * 
          \sp_read:counter_read_stateSBV_1\.Q 
        + \sp_read:counter_address_2\.Q * 
          \sp_read:counter_read_stateSBV_0\.Q 

    S_13 =
          \sp_read:counter_address_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * /bp_end_address_0.Q * 
          /bp_end_address_1.Q * /bp_end_address_2.Q * /bp_end_address_3.Q * 
          /bp_end_address_4.Q * /bp_end_address_5.Q * /bp_end_address_6.Q * 
          /bp_end_address_7.Q 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          bp_end_address_6.Q * bp_start_address_1.Q * hva_chassis_en_l * 
          sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          bp_end_address_5.Q * bp_start_address_1.Q * hva_chassis_en_l * 
          sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          bp_end_address_4.Q * bp_start_address_1.Q * hva_chassis_en_l * 
          sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          bp_end_address_3.Q * bp_start_address_1.Q * hva_chassis_en_l * 
          sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          bp_end_address_2.Q * bp_start_address_1.Q * hva_chassis_en_l * 
          sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          bp_end_address_1.Q * bp_start_address_1.Q * hva_chassis_en_l * 
          sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          bp_end_address_0.Q * bp_start_address_1.Q * hva_chassis_en_l * 
          sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          bp_end_address_7.Q * bp_start_address_1.Q * hva_chassis_en_l * 
          /sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          bp_end_address_6.Q * bp_start_address_1.Q * hva_chassis_en_l * 
          /sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          bp_end_address_5.Q * bp_start_address_1.Q * hva_chassis_en_l * 
          /sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          bp_end_address_4.Q * bp_start_address_1.Q * hva_chassis_en_l * 
          /sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          bp_end_address_3.Q * bp_start_address_1.Q * hva_chassis_en_l * 
          /sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          bp_end_address_2.Q * bp_start_address_1.Q * hva_chassis_en_l * 
          /sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          bp_end_address_1.Q * bp_start_address_1.Q * hva_chassis_en_l * 
          /sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          bp_end_address_0.Q * bp_start_address_1.Q * hva_chassis_en_l * 
          /sinphase_zeros 

    S_14 =
          /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          bp_end_address_7.Q * bp_start_address_1.Q * hva_chassis_en_l * 
          sinphase_zeros 
        + \sp_read:counter_address_0\.Q * /\sp_read:counter_address_1\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          \sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q 
        + \sp_read:counter_address_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * \sp_read:old_phase\.Q * 
          sinphase_zeros 
        + \sp_read:counter_address_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * /\sp_read:old_phase\.Q * 
          /sinphase_zeros 
        + /\sp_read:counter_address_0\.Q * \sp_read:counter_address_1\.Q * 
          \sp_read:counter_read_stateSBV_2\.Q 
        + \sp_read:counter_address_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * /hva_chassis_en_l 
        + \sp_read:counter_address_1\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q 
        + \sp_read:counter_address_1\.Q * 
          \sp_read:counter_read_stateSBV_1\.Q 
        + \sp_read:counter_address_1\.Q * 
          \sp_read:counter_read_stateSBV_0\.Q 

    S_15 =
          \sp_read:counter_address_0\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * /bp_end_address_0.Q * 
          /bp_end_address_1.Q * /bp_end_address_2.Q * /bp_end_address_3.Q * 
          /bp_end_address_4.Q * /bp_end_address_5.Q * /bp_end_address_6.Q * 
          /bp_end_address_7.Q 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          bp_end_address_7.Q * bp_start_address_0.Q * hva_chassis_en_l * 
          sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          bp_end_address_6.Q * bp_start_address_0.Q * hva_chassis_en_l * 
          sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          bp_end_address_5.Q * bp_start_address_0.Q * hva_chassis_en_l * 
          sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          bp_end_address_4.Q * bp_start_address_0.Q * hva_chassis_en_l * 
          sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          bp_end_address_2.Q * bp_start_address_0.Q * hva_chassis_en_l * 
          sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          bp_end_address_1.Q * bp_start_address_0.Q * hva_chassis_en_l * 
          sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          bp_end_address_0.Q * bp_start_address_0.Q * hva_chassis_en_l * 
          sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          bp_end_address_7.Q * bp_start_address_0.Q * hva_chassis_en_l * 
          /sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          bp_end_address_6.Q * bp_start_address_0.Q * hva_chassis_en_l * 
          /sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          bp_end_address_5.Q * bp_start_address_0.Q * hva_chassis_en_l * 
          /sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          bp_end_address_4.Q * bp_start_address_0.Q * hva_chassis_en_l * 
          /sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          bp_end_address_3.Q * bp_start_address_0.Q * hva_chassis_en_l * 
          /sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          bp_end_address_2.Q * bp_start_address_0.Q * hva_chassis_en_l * 
          /sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          bp_end_address_1.Q * bp_start_address_0.Q * hva_chassis_en_l * 
          /sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          bp_end_address_0.Q * bp_start_address_0.Q * hva_chassis_en_l * 
          /sinphase_zeros 

    S_16 =
          /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          bp_end_address_3.Q * bp_start_address_0.Q * hva_chassis_en_l * 
          sinphase_zeros 
        + \sp_read:counter_address_0\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * \sp_read:old_phase\.Q * 
          sinphase_zeros 
        + /\sp_read:counter_address_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          \sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q 
        + \sp_read:counter_address_0\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * /\sp_read:old_phase\.Q * 
          /sinphase_zeros 
        + \sp_read:counter_address_0\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * /hva_chassis_en_l 
        + \sp_read:counter_address_0\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q 
        + \sp_read:counter_address_0\.Q * 
          \sp_read:counter_read_stateSBV_1\.Q 
        + \sp_read:counter_address_0\.Q * 
          \sp_read:counter_read_stateSBV_0\.Q 

    S_17 =
          \ibus_reader:il_read_stateSBV_0\.Q * 
          \ibus_reader:il_read_stateSBV_1\.Q * \ibus_reader:timeout_0\.Q * 
          /\ibus_reader:timeout_1\.Q * loopback_state.Q * to_pc_ack.Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          \ibus_reader:il_read_stateSBV_1\.Q * \ibus_reader:timeout_0\.Q * 
          /\ibus_reader:timeout_1\.Q * /loopback_state.Q * 
          write_to_bp_ack.Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * \ibus_reader:timeout_1\.Q * 
          \ibus_reader:timeout_2\.Q * \ibus_reader:timeout_3\.Q * 
          loopback_state.Q * /to_pc_ack.Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          \ibus_reader:il_read_stateSBV_2\.Q * \ibus_reader:timeout_0\.Q * 
          /\ibus_reader:timeout_1\.Q * loopback_state.Q * /to_pc_ack.Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * \ibus_reader:timeout_1\.Q * 
          \ibus_reader:timeout_2\.Q * \ibus_reader:timeout_3\.Q * 
          /loopback_state.Q * /write_to_bp_ack.Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          \ibus_reader:il_read_stateSBV_2\.Q * \ibus_reader:timeout_0\.Q * 
          /\ibus_reader:timeout_1\.Q * /loopback_state.Q * 
          /write_to_bp_ack.Q 
        + \ibus_reader:il_read_stateSBV_1\.Q * \ibus_reader:timeout_1\.Q * 
          \ibus_reader:timeout_2\.Q * \ibus_reader:timeout_3\.Q * 
          ao_from_pc_strobe 
        + /\ibus_reader:il_read_stateSBV_0\.Q * 
          \ibus_reader:il_read_stateSBV_1\.Q * \ibus_reader:timeout_0\.Q * 
          /\ibus_reader:timeout_1\.Q * ao_from_pc_strobe 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * \ibus_reader:timeout_1\.Q * 
          loopback_state.Q * /to_pc_ack.Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * /\ibus_reader:timeout_0\.Q * 
          \ibus_reader:timeout_1\.Q * loopback_state.Q * /to_pc_ack.Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * \ibus_reader:timeout_1\.Q * 
          /loopback_state.Q * /write_to_bp_ack.Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * /\ibus_reader:timeout_0\.Q * 
          \ibus_reader:timeout_1\.Q * /loopback_state.Q * 
          /write_to_bp_ack.Q 
        + /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          \ibus_reader:il_read_stateSBV_2\.Q * \ibus_reader:timeout_1\.Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * \ibus_reader:timeout_1\.Q 
        + \ibus_reader:il_read_stateSBV_1\.Q * /\ibus_reader:timeout_0\.Q * 
          \ibus_reader:timeout_1\.Q * ao_from_pc_strobe 
        + /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * \ibus_reader:timeout_1\.Q * 
          /ao_from_pc_strobe 

    S_18 =
          /\ibus_reader:il_read_stateSBV_2\.Q * \ibus_reader:timeout_1\.Q * 
          \ibus_reader:timeout_2\.Q * \ibus_reader:timeout_3\.Q * 
          /ao_from_pc_strobe 
        + /\ibus_reader:il_read_stateSBV_0\.Q * 
          \ibus_reader:this_is_a_ctrl_transaction\.Q * 
          \ibus_reader:timeout_1\.Q * /ao_from_pc_strobe 
        + /\ibus_reader:il_read_stateSBV_2\.Q * /\ibus_reader:timeout_0\.Q * 
          \ibus_reader:timeout_1\.Q * /ao_from_pc_strobe 

    /S_2 =
          \sp_read:counter_address_0\.Q * \sp_read:counter_address_1\.Q * 
          \sp_read:counter_address_2\.Q * \sp_read:counter_address_3\.Q * 
          \sp_read:counter_address_4\.Q * \sp_read:counter_address_5\.Q * 
          \sp_read:counter_address_6\.Q * 
          /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          \sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          /bp_end_address_1.Q * /bp_end_address_2.Q * hva_chassis_en_l * 
          sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          /bp_start_address_7.Q * hva_chassis_en_l * sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          hva_chassis_en_l * /sinphase_zeros 
        + /\sp_read:counter_address_7\.Q * \sp_read:old_phase\.Q 
        + /\sp_read:counter_address_7\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q 
        + /\sp_read:counter_address_7\.Q * 
          \sp_read:counter_read_stateSBV_2\.Q 
        + /\sp_read:counter_address_7\.Q * 
          \sp_read:counter_read_stateSBV_1\.Q 
        + /\sp_read:counter_address_7\.Q * 
          \sp_read:counter_read_stateSBV_0\.Q 
        + /\sp_read:counter_address_7\.Q * /hva_chassis_en_l 
        + /\sp_read:counter_address_7\.Q * /sinphase_zeros 

    S_3 =
          \sp_read:counter_address_0\.Q * \sp_read:counter_address_1\.Q * 
          \sp_read:counter_address_2\.Q * \sp_read:counter_address_3\.Q * 
          \sp_read:counter_address_4\.Q * \sp_read:counter_address_5\.Q * 
          /\sp_read:counter_address_6\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          \sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q 
        + \sp_read:counter_address_6\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * /bp_end_address_0.Q * 
          /bp_end_address_1.Q * /bp_end_address_2.Q * /bp_end_address_3.Q * 
          /bp_end_address_4.Q * /bp_end_address_5.Q * /bp_end_address_6.Q * 
          /bp_end_address_7.Q 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          bp_end_address_7.Q * bp_start_address_6.Q * hva_chassis_en_l * 
          sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          bp_end_address_6.Q * bp_start_address_6.Q * hva_chassis_en_l * 
          sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          bp_end_address_5.Q * bp_start_address_6.Q * hva_chassis_en_l * 
          sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          bp_end_address_4.Q * bp_start_address_6.Q * hva_chassis_en_l * 
          sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          bp_end_address_1.Q * bp_start_address_6.Q * hva_chassis_en_l * 
          sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          bp_end_address_0.Q * bp_start_address_6.Q * hva_chassis_en_l * 
          sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          bp_end_address_7.Q * bp_start_address_6.Q * hva_chassis_en_l * 
          /sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          bp_end_address_6.Q * bp_start_address_6.Q * hva_chassis_en_l * 
          /sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          bp_end_address_5.Q * bp_start_address_6.Q * hva_chassis_en_l * 
          /sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          bp_end_address_4.Q * bp_start_address_6.Q * hva_chassis_en_l * 
          /sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          bp_end_address_3.Q * bp_start_address_6.Q * hva_chassis_en_l * 
          /sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          bp_end_address_2.Q * bp_start_address_6.Q * hva_chassis_en_l * 
          /sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          bp_end_address_1.Q * bp_start_address_6.Q * hva_chassis_en_l * 
          /sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          bp_end_address_0.Q * bp_start_address_6.Q * hva_chassis_en_l * 
          /sinphase_zeros 

    /S_4 =
          \sp_read:counter_address_0\.Q * \sp_read:counter_address_1\.Q * 
          \sp_read:counter_address_2\.Q * \sp_read:counter_address_3\.Q * 
          \sp_read:counter_address_4\.Q * \sp_read:counter_address_5\.Q * 
          /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          \sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          /bp_end_address_2.Q * /bp_end_address_3.Q * hva_chassis_en_l * 
          sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          /bp_start_address_6.Q * hva_chassis_en_l * sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          hva_chassis_en_l * /sinphase_zeros 
        + /\sp_read:counter_address_6\.Q * \sp_read:old_phase\.Q 
        + /\sp_read:counter_address_6\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q 
        + /\sp_read:counter_address_6\.Q * 
          \sp_read:counter_read_stateSBV_2\.Q 
        + /\sp_read:counter_address_6\.Q * 
          \sp_read:counter_read_stateSBV_1\.Q 
        + /\sp_read:counter_address_6\.Q * 
          \sp_read:counter_read_stateSBV_0\.Q 
        + /\sp_read:counter_address_6\.Q * /hva_chassis_en_l 
        + /\sp_read:counter_address_6\.Q * /sinphase_zeros 

    S_5 =
          \sp_read:counter_address_5\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * /bp_end_address_0.Q * 
          /bp_end_address_1.Q * /bp_end_address_2.Q * /bp_end_address_3.Q * 
          /bp_end_address_4.Q * /bp_end_address_5.Q * /bp_end_address_6.Q * 
          /bp_end_address_7.Q 
        + \sp_read:counter_address_0\.Q * \sp_read:counter_address_1\.Q * 
          \sp_read:counter_address_2\.Q * \sp_read:counter_address_3\.Q * 
          \sp_read:counter_address_4\.Q * /\sp_read:counter_address_5\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          \sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          bp_end_address_7.Q * bp_start_address_5.Q * hva_chassis_en_l * 
          sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          bp_end_address_6.Q * bp_start_address_5.Q * hva_chassis_en_l * 
          sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          bp_end_address_3.Q * bp_start_address_5.Q * hva_chassis_en_l * 
          sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          bp_end_address_2.Q * bp_start_address_5.Q * hva_chassis_en_l * 
          sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          bp_end_address_1.Q * bp_start_address_5.Q * hva_chassis_en_l * 
          sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          bp_end_address_0.Q * bp_start_address_5.Q * hva_chassis_en_l * 
          sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          bp_end_address_7.Q * bp_start_address_5.Q * hva_chassis_en_l * 
          /sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          bp_end_address_6.Q * bp_start_address_5.Q * hva_chassis_en_l * 
          /sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          bp_end_address_5.Q * bp_start_address_5.Q * hva_chassis_en_l * 
          /sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          bp_end_address_4.Q * bp_start_address_5.Q * hva_chassis_en_l * 
          /sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          bp_end_address_3.Q * bp_start_address_5.Q * hva_chassis_en_l * 
          /sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          bp_end_address_2.Q * bp_start_address_5.Q * hva_chassis_en_l * 
          /sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          bp_end_address_1.Q * bp_start_address_5.Q * hva_chassis_en_l * 
          /sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          bp_end_address_0.Q * bp_start_address_5.Q * hva_chassis_en_l * 
          /sinphase_zeros 

    /S_6 =
          \sp_read:counter_address_0\.Q * \sp_read:counter_address_1\.Q * 
          \sp_read:counter_address_2\.Q * \sp_read:counter_address_3\.Q * 
          \sp_read:counter_address_4\.Q * 
          /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          \sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          /bp_end_address_4.Q * /bp_end_address_5.Q * hva_chassis_en_l * 
          sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          /bp_start_address_5.Q * hva_chassis_en_l * sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          hva_chassis_en_l * /sinphase_zeros 
        + /\sp_read:counter_address_5\.Q * \sp_read:old_phase\.Q 
        + /\sp_read:counter_address_5\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q 
        + /\sp_read:counter_address_5\.Q * 
          \sp_read:counter_read_stateSBV_2\.Q 
        + /\sp_read:counter_address_5\.Q * 
          \sp_read:counter_read_stateSBV_1\.Q 
        + /\sp_read:counter_address_5\.Q * 
          \sp_read:counter_read_stateSBV_0\.Q 
        + /\sp_read:counter_address_5\.Q * /hva_chassis_en_l 
        + /\sp_read:counter_address_5\.Q * /sinphase_zeros 

    S_7 =
          \sp_read:counter_address_4\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * /bp_end_address_0.Q * 
          /bp_end_address_1.Q * /bp_end_address_2.Q * /bp_end_address_3.Q * 
          /bp_end_address_4.Q * /bp_end_address_5.Q * /bp_end_address_6.Q * 
          /bp_end_address_7.Q 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          bp_end_address_7.Q * bp_start_address_4.Q * hva_chassis_en_l * 
          sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          bp_end_address_6.Q * bp_start_address_4.Q * hva_chassis_en_l * 
          sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          bp_end_address_4.Q * bp_start_address_4.Q * hva_chassis_en_l * 
          sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          bp_end_address_3.Q * bp_start_address_4.Q * hva_chassis_en_l * 
          sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          bp_end_address_2.Q * bp_start_address_4.Q * hva_chassis_en_l * 
          sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          bp_end_address_1.Q * bp_start_address_4.Q * hva_chassis_en_l * 
          sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          bp_end_address_0.Q * bp_start_address_4.Q * hva_chassis_en_l * 
          sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          bp_end_address_7.Q * bp_start_address_4.Q * hva_chassis_en_l * 
          /sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          bp_end_address_6.Q * bp_start_address_4.Q * hva_chassis_en_l * 
          /sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          bp_end_address_5.Q * bp_start_address_4.Q * hva_chassis_en_l * 
          /sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          bp_end_address_4.Q * bp_start_address_4.Q * hva_chassis_en_l * 
          /sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          bp_end_address_3.Q * bp_start_address_4.Q * hva_chassis_en_l * 
          /sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          bp_end_address_2.Q * bp_start_address_4.Q * hva_chassis_en_l * 
          /sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          bp_end_address_1.Q * bp_start_address_4.Q * hva_chassis_en_l * 
          /sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          bp_end_address_0.Q * bp_start_address_4.Q * hva_chassis_en_l * 
          /sinphase_zeros 

    S_8 =
          /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          bp_end_address_5.Q * bp_start_address_4.Q * hva_chassis_en_l * 
          sinphase_zeros 
        + \sp_read:counter_address_0\.Q * \sp_read:counter_address_1\.Q * 
          \sp_read:counter_address_2\.Q * \sp_read:counter_address_3\.Q * 
          /\sp_read:counter_address_4\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          \sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q 
        + \sp_read:counter_address_4\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * \sp_read:old_phase\.Q * 
          sinphase_zeros 
        + \sp_read:counter_address_4\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * /\sp_read:old_phase\.Q * 
          /sinphase_zeros 
        + /\sp_read:counter_address_0\.Q * \sp_read:counter_address_4\.Q * 
          \sp_read:counter_read_stateSBV_2\.Q 
        + /\sp_read:counter_address_1\.Q * \sp_read:counter_address_4\.Q * 
          \sp_read:counter_read_stateSBV_2\.Q 
        + /\sp_read:counter_address_2\.Q * \sp_read:counter_address_4\.Q * 
          \sp_read:counter_read_stateSBV_2\.Q 
        + /\sp_read:counter_address_3\.Q * \sp_read:counter_address_4\.Q * 
          \sp_read:counter_read_stateSBV_2\.Q 
        + \sp_read:counter_address_4\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * /hva_chassis_en_l 
        + \sp_read:counter_address_4\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q 
        + \sp_read:counter_address_4\.Q * 
          \sp_read:counter_read_stateSBV_1\.Q 
        + \sp_read:counter_address_4\.Q * 
          \sp_read:counter_read_stateSBV_0\.Q 

    S_9 =
          \sp_read:counter_address_3\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * /bp_end_address_0.Q * 
          /bp_end_address_1.Q * /bp_end_address_2.Q * /bp_end_address_3.Q * 
          /bp_end_address_4.Q * /bp_end_address_5.Q * /bp_end_address_6.Q * 
          /bp_end_address_7.Q 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          bp_end_address_7.Q * bp_start_address_3.Q * hva_chassis_en_l * 
          sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          bp_end_address_5.Q * bp_start_address_3.Q * hva_chassis_en_l * 
          sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          bp_end_address_4.Q * bp_start_address_3.Q * hva_chassis_en_l * 
          sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          bp_end_address_3.Q * bp_start_address_3.Q * hva_chassis_en_l * 
          sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          bp_end_address_2.Q * bp_start_address_3.Q * hva_chassis_en_l * 
          sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          bp_end_address_1.Q * bp_start_address_3.Q * hva_chassis_en_l * 
          sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          bp_end_address_0.Q * bp_start_address_3.Q * hva_chassis_en_l * 
          sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          bp_end_address_7.Q * bp_start_address_3.Q * hva_chassis_en_l * 
          /sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          bp_end_address_6.Q * bp_start_address_3.Q * hva_chassis_en_l * 
          /sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          bp_end_address_5.Q * bp_start_address_3.Q * hva_chassis_en_l * 
          /sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          bp_end_address_4.Q * bp_start_address_3.Q * hva_chassis_en_l * 
          /sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          bp_end_address_3.Q * bp_start_address_3.Q * hva_chassis_en_l * 
          /sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          bp_end_address_2.Q * bp_start_address_3.Q * hva_chassis_en_l * 
          /sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          bp_end_address_1.Q * bp_start_address_3.Q * hva_chassis_en_l * 
          /sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          bp_end_address_0.Q * bp_start_address_3.Q * hva_chassis_en_l * 
          /sinphase_zeros 

    \bp_io:bp_access_stateSBV_0\.T =
          \bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_1\.Q * 
          \bp_io:bp_access_stateSBV_2\.Q * \bp_io:timeout_0\.Q * 
          \bp_io:timeout_1\.Q * \bp_io:timeout_2\.Q 
        + \bp_io:bp_access_stateSBV_0\.Q * /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * \bp_io:timeout_0\.Q * 
          \bp_io:timeout_1\.Q * \bp_io:timeout_2\.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_1\.Q * 
          \bp_io:bp_access_stateSBV_2\.Q * /\bp_io:timeout_0\.Q * 
          \bp_io:timeout_1\.Q * /\bp_io:timeout_2\.Q 
        + /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * loopback_state.Q * 
          sensor_to_bp_read_req.Q 
        + \bp_io:bp_access_stateSBV_0\.Q * /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * loopback_state.Q 
        + /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /from_pc_req.Q * 
          sensor_to_bp_read_req.Q 
        + \bp_io:bp_access_stateSBV_0\.Q * /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /from_pc_req.Q 
        + \bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_1\.Q * 
          \bp_io:bp_access_stateSBV_2\.Q * /sensor_to_bp_read_req.Q 

    \bp_io:bp_access_stateSBV_0\.AP =
          GND

    \bp_io:bp_access_stateSBV_0\.AR =
          reset.CMB 

    \bp_io:bp_access_stateSBV_0\.C =
          clk 

    \bp_io:bp_access_stateSBV_1\.T =
          \bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_1\.Q * 
          \bp_io:bp_access_stateSBV_2\.Q * \bp_io:timeout_0\.Q * 
          \bp_io:timeout_1\.Q * \bp_io:timeout_2\.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_2\.Q * 
          /\bp_io:timeout_0\.Q * \bp_io:timeout_1\.Q * 
          /\bp_io:timeout_2\.Q 
        + /\bp_io:bp_access_stateSBV_1\.Q * \bp_io:bp_access_stateSBV_2\.Q * 
          /\bp_io:timeout_0\.Q * \bp_io:timeout_1\.Q * 
          /\bp_io:timeout_2\.Q 
        + \bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_1\.Q * 
          \bp_io:bp_access_stateSBV_2\.Q * /sensor_to_bp_read_req.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_1\.Q * \bp_io:bp_access_stateSBV_2\.Q 

    \bp_io:bp_access_stateSBV_1\.AP =
          GND

    \bp_io:bp_access_stateSBV_1\.AR =
          reset.CMB 

    \bp_io:bp_access_stateSBV_1\.C =
          clk 

    \bp_io:bp_access_stateSBV_2\.T =
          \bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_1\.Q * 
          \bp_io:bp_access_stateSBV_2\.Q * \bp_io:timeout_0\.Q * 
          \bp_io:timeout_1\.Q * \bp_io:timeout_2\.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_2\.Q * 
          /\bp_io:timeout_0\.Q * \bp_io:timeout_1\.Q * 
          /\bp_io:timeout_2\.Q 
        + /\bp_io:bp_access_stateSBV_1\.Q * \bp_io:bp_access_stateSBV_2\.Q * 
          /\bp_io:timeout_0\.Q * \bp_io:timeout_1\.Q * 
          /\bp_io:timeout_2\.Q 
        + \bp_io:bp_access_stateSBV_1\.Q * /\bp_io:bp_access_stateSBV_2\.Q * 
          /\bp_io:timeout_0\.Q * \bp_io:timeout_1\.Q * 
          /\bp_io:timeout_2\.Q 
        + \bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_1\.Q * 
          \bp_io:bp_access_stateSBV_2\.Q * /sensor_to_bp_read_req.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_1\.Q * from_pc_req.Q * 
          /loopback_state.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_1\.Q * \bp_io:bp_access_stateSBV_2\.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_1\.Q * sensor_to_bp_read_req.Q 

    \bp_io:bp_access_stateSBV_2\.AP =
          GND

    \bp_io:bp_access_stateSBV_2\.AR =
          reset.CMB 

    \bp_io:bp_access_stateSBV_2\.C =
          clk 

    \bp_io:timeout_0\.D =
          \bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_1\.Q * 
          \bp_io:bp_access_stateSBV_2\.Q * \bp_io:timeout_1\.Q * 
          \bp_io:timeout_2\.Q * sensor_to_bp_read_req.Q 
        + \bp_io:bp_access_stateSBV_0\.Q * /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * \bp_io:timeout_0\.Q * 
          \bp_io:timeout_1\.Q * \bp_io:timeout_2\.Q 
        + \bp_io:bp_access_stateSBV_0\.Q * /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * \bp_io:timeout_0\.Q * 
          loopback_state.Q 
        + \bp_io:bp_access_stateSBV_0\.Q * /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * \bp_io:timeout_0\.Q * 
          /from_pc_req.Q 
        + \bp_io:bp_access_stateSBV_0\.Q * /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:timeout_0\.Q * from_pc_req.Q * /loopback_state.Q 
        + \bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_1\.Q * 
          \bp_io:bp_access_stateSBV_2\.Q * \bp_io:timeout_0\.Q * 
          /sensor_to_bp_read_req.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_1\.Q * \bp_io:bp_access_stateSBV_2\.Q * 
          \bp_io:timeout_0\.Q 
        + \bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_2\.Q * 
          /\bp_io:timeout_0\.Q * sensor_to_bp_read_req.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:timeout_0\.Q * \bp_io:timeout_2\.Q 
        + \bp_io:bp_access_stateSBV_0\.Q * /\bp_io:bp_access_stateSBV_1\.Q * 
          \bp_io:bp_access_stateSBV_2\.Q * /\bp_io:timeout_0\.Q 
        + \bp_io:bp_access_stateSBV_1\.Q * /\bp_io:bp_access_stateSBV_2\.Q * 
          /\bp_io:timeout_0\.Q * \bp_io:timeout_2\.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:timeout_0\.Q * /\bp_io:timeout_1\.Q 
        + \bp_io:bp_access_stateSBV_1\.Q * /\bp_io:bp_access_stateSBV_2\.Q * 
          /\bp_io:timeout_0\.Q * /\bp_io:timeout_1\.Q 

    \bp_io:timeout_0\.AP =
          GND

    \bp_io:timeout_0\.AR =
          reset.CMB 

    \bp_io:timeout_0\.C =
          clk 

    \bp_io:timeout_1\.T =
          \bp_io:bp_access_stateSBV_0\.Q * /\bp_io:bp_access_stateSBV_2\.Q * 
          \bp_io:timeout_0\.Q * /\bp_io:timeout_1\.Q * from_pc_req.Q * 
          /loopback_state.Q 
        + \bp_io:bp_access_stateSBV_0\.Q * /\bp_io:bp_access_stateSBV_2\.Q * 
          \bp_io:timeout_0\.Q * /\bp_io:timeout_2\.Q * from_pc_req.Q * 
          /loopback_state.Q 
        + \bp_io:bp_access_stateSBV_0\.Q * /\bp_io:bp_access_stateSBV_1\.Q * 
          \bp_io:bp_access_stateSBV_2\.Q * \bp_io:timeout_0\.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * \bp_io:timeout_1\.Q 
        + \bp_io:bp_access_stateSBV_1\.Q * \bp_io:timeout_0\.Q * 
          /\bp_io:timeout_1\.Q * sensor_to_bp_read_req.Q 
        + \bp_io:bp_access_stateSBV_1\.Q * \bp_io:timeout_0\.Q * 
          /\bp_io:timeout_2\.Q * sensor_to_bp_read_req.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_1\.Q * 
          \bp_io:timeout_1\.Q * /\bp_io:timeout_2\.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_1\.Q * 
          \bp_io:timeout_0\.Q 
        + \bp_io:bp_access_stateSBV_1\.Q * /\bp_io:bp_access_stateSBV_2\.Q * 
          \bp_io:timeout_0\.Q 

    \bp_io:timeout_1\.AP =
          GND

    \bp_io:timeout_1\.AR =
          reset.CMB 

    \bp_io:timeout_1\.C =
          clk 

    \bp_io:timeout_2\.T =
          \bp_io:bp_access_stateSBV_0\.Q * /\bp_io:bp_access_stateSBV_2\.Q * 
          \bp_io:timeout_0\.Q * \bp_io:timeout_1\.Q * /\bp_io:timeout_2\.Q * 
          from_pc_req.Q * /loopback_state.Q 
        + \bp_io:bp_access_stateSBV_0\.Q * /\bp_io:bp_access_stateSBV_1\.Q * 
          \bp_io:bp_access_stateSBV_2\.Q * \bp_io:timeout_0\.Q * 
          \bp_io:timeout_1\.Q 
        + \bp_io:bp_access_stateSBV_1\.Q * \bp_io:timeout_0\.Q * 
          \bp_io:timeout_1\.Q * /\bp_io:timeout_2\.Q * 
          sensor_to_bp_read_req.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_1\.Q * 
          \bp_io:timeout_0\.Q * \bp_io:timeout_1\.Q 
        + \bp_io:bp_access_stateSBV_1\.Q * /\bp_io:bp_access_stateSBV_2\.Q * 
          \bp_io:timeout_0\.Q * \bp_io:timeout_1\.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * \bp_io:timeout_2\.Q 

    \bp_io:timeout_2\.AP =
          GND

    \bp_io:timeout_2\.AR =
          reset.CMB 

    \bp_io:timeout_2\.C =
          clk 

    \ibus_reader:il_read_stateSBV_0\.T =
          \ibus_reader:il_read_stateSBV_0\.Q * 
          \ibus_reader:il_read_stateSBV_2\.Q * \ibus_reader:timeout_0\.Q * 
          \ibus_reader:timeout_1\.Q * \ibus_reader:timeout_2\.Q * 
          \ibus_reader:timeout_3\.Q * ao_from_pc_strobe * loopback_state.Q * 
          /to_pc_ack.Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          \ibus_reader:il_read_stateSBV_2\.Q * \ibus_reader:timeout_0\.Q * 
          \ibus_reader:timeout_1\.Q * \ibus_reader:timeout_2\.Q * 
          \ibus_reader:timeout_3\.Q * loopback_state.Q * /to_pc_ack.Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * \ibus_reader:timeout_0\.Q * 
          \ibus_reader:timeout_1\.Q * \ibus_reader:timeout_2\.Q * 
          \ibus_reader:timeout_3\.Q * ao_from_pc_strobe * 
          /loopback_state.Q * /write_to_bp_ack.Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * \ibus_reader:timeout_0\.Q * 
          \ibus_reader:timeout_1\.Q * \ibus_reader:timeout_2\.Q * 
          \ibus_reader:timeout_3\.Q * /loopback_state.Q * 
          /write_to_bp_ack.Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          \ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * \ibus_reader:timeout_0\.Q * 
          \ibus_reader:timeout_1\.Q * \ibus_reader:timeout_2\.Q * 
          \ibus_reader:timeout_3\.Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          \ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * loopback_state.Q * 
          /to_pc_ack.Q 
        + /\ibus_reader:il_read_stateSBV_0\.Q * 
          \ibus_reader:il_read_stateSBV_1\.Q * /ao_from_pc_strobe * 
          loopback_state.Q 
        + /\ibus_reader:il_read_stateSBV_0\.Q * 
          \ibus_reader:il_read_stateSBV_1\.Q * 
          \ibus_reader:il_read_stateSBV_2\.Q * /ao_from_pc_strobe 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * /loopback_state.Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * /loopback_state.Q * 
          /write_to_bp_ack.Q 

    \ibus_reader:il_read_stateSBV_0\.AP =
          GND

    \ibus_reader:il_read_stateSBV_0\.AR =
          reset.CMB 

    \ibus_reader:il_read_stateSBV_0\.C =
          clk 

    \ibus_reader:il_read_stateSBV_1\.T =
          /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          \ibus_reader:il_read_stateSBV_2\.Q * /bpctrl(10).Q * 
          bpctrl(11).Q * /bpctrl(7).Q * /bpctrl(8).Q * data_from_pc_15.Q 
        + /\ibus_reader:il_read_stateSBV_0\.Q * 
          \ibus_reader:il_read_stateSBV_1\.Q * \ibus_reader:timeout_0\.Q * 
          \ibus_reader:timeout_1\.Q * \ibus_reader:timeout_2\.Q * 
          \ibus_reader:timeout_3\.Q 
        + \ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * \ibus_reader:timeout_0\.Q * 
          \ibus_reader:timeout_1\.Q * \ibus_reader:timeout_2\.Q * 
          \ibus_reader:timeout_3\.Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          \ibus_reader:il_read_stateSBV_2\.Q * loopback_state.Q * 
          to_pc_ack.Q 
        + /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          \ibus_reader:il_read_stateSBV_2\.Q * /data_from_pc_15.Q * 
          this_chip_selected.Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          \ibus_reader:il_read_stateSBV_2\.Q * /loopback_state.Q * 
          write_to_bp_ack.Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          \ibus_reader:il_read_stateSBV_1\.Q * loopback_state.Q * 
          /to_pc_ack.Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          \ibus_reader:il_read_stateSBV_1\.Q * /loopback_state.Q * 
          /write_to_bp_ack.Q 
        + /\ibus_reader:il_read_stateSBV_0\.Q * 
          \ibus_reader:il_read_stateSBV_1\.Q * /ao_from_pc_strobe 

    \ibus_reader:il_read_stateSBV_1\.AP =
          GND

    \ibus_reader:il_read_stateSBV_1\.AR =
          reset.CMB 

    \ibus_reader:il_read_stateSBV_1\.C =
          clk 

    \ibus_reader:il_read_stateSBV_2\.T =
          \ibus_reader:il_read_stateSBV_1\.Q * 
          \ibus_reader:il_read_stateSBV_2\.Q * \ibus_reader:timeout_0\.Q * 
          \ibus_reader:timeout_1\.Q * \ibus_reader:timeout_2\.Q * 
          \ibus_reader:timeout_3\.Q * ao_from_pc_strobe 
        + \ibus_reader:il_read_stateSBV_1\.Q * 
          \ibus_reader:il_read_stateSBV_2\.Q * 
          \ibus_reader:this_is_a_ctrl_transaction\.Q * 
          \ibus_reader:timeout_0\.Q * \ibus_reader:timeout_1\.Q * 
          \ibus_reader:timeout_2\.Q * \ibus_reader:timeout_3\.Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          \ibus_reader:il_read_stateSBV_2\.Q * \ibus_reader:timeout_0\.Q * 
          \ibus_reader:timeout_1\.Q * \ibus_reader:timeout_2\.Q * 
          \ibus_reader:timeout_3\.Q 
        + \ibus_reader:il_read_stateSBV_1\.Q * 
          \ibus_reader:il_read_stateSBV_2\.Q * 
          \ibus_reader:this_is_a_ctrl_transaction\.Q * /ao_from_pc_strobe * 
          loopback_state.Q * to_pc_ack.Q 
        + \ibus_reader:il_read_stateSBV_1\.Q * 
          \ibus_reader:il_read_stateSBV_2\.Q * 
          \ibus_reader:this_is_a_ctrl_transaction\.Q * /ao_from_pc_strobe * 
          /loopback_state.Q * write_to_bp_ack.Q 
        + /\ibus_reader:il_read_stateSBV_0\.Q * 
          \ibus_reader:il_read_stateSBV_1\.Q * 
          \ibus_reader:il_read_stateSBV_2\.Q * 
          \ibus_reader:this_is_a_ctrl_transaction\.Q * /ao_from_pc_strobe 
        + /\ibus_reader:il_read_stateSBV_0\.Q * 
          \ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * /ao_from_pc_strobe * 
          loopback_state.Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          \ibus_reader:il_read_stateSBV_2\.Q * /loopback_state.Q * 
          write_to_bp_ack.Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * loopback_state.Q * 
          to_pc_ack.Q 
        + /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          \ibus_reader:il_read_stateSBV_2\.Q * data_from_pc_15.Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * loopback_state.Q 
        + /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * ao_from_pc_strobe 
        + /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          \ibus_reader:il_read_stateSBV_2\.Q * /this_chip_selected.Q 

    \ibus_reader:il_read_stateSBV_2\.AP =
          GND

    \ibus_reader:il_read_stateSBV_2\.AR =
          reset.CMB 

    \ibus_reader:il_read_stateSBV_2\.C =
          clk 

    \ibus_reader:this_is_a_ctrl_transaction\.D =
          /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          \ibus_reader:il_read_stateSBV_2\.Q * /bpctrl(10).Q * 
          bpctrl(11).Q * bpctrl(6).Q * /bpctrl(7).Q * /bpctrl(8).Q * 
          data_from_pc_15.Q 
        + \ibus_reader:il_read_stateSBV_1\.Q * 
          \ibus_reader:this_is_a_ctrl_transaction\.Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          \ibus_reader:this_is_a_ctrl_transaction\.Q 
        + /\ibus_reader:il_read_stateSBV_2\.Q * 
          \ibus_reader:this_is_a_ctrl_transaction\.Q 
        + \ibus_reader:this_is_a_ctrl_transaction\.Q * /data_from_pc_15.Q 

    \ibus_reader:this_is_a_ctrl_transaction\.AP =
          GND

    \ibus_reader:this_is_a_ctrl_transaction\.AR =
          reset.CMB 

    \ibus_reader:this_is_a_ctrl_transaction\.C =
          clk 

    \ibus_reader:timeout_0\.D =
          \ibus_reader:il_read_stateSBV_0\.Q * \ibus_reader:timeout_0\.Q * 
          \ibus_reader:timeout_1\.Q * \ibus_reader:timeout_2\.Q * 
          \ibus_reader:timeout_3\.Q * loopback_state.Q * /to_pc_ack.Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * \ibus_reader:timeout_0\.Q * 
          \ibus_reader:timeout_1\.Q * \ibus_reader:timeout_2\.Q * 
          \ibus_reader:timeout_3\.Q * /loopback_state.Q * 
          /write_to_bp_ack.Q 
        + \ibus_reader:il_read_stateSBV_1\.Q * \ibus_reader:timeout_0\.Q * 
          \ibus_reader:timeout_1\.Q * \ibus_reader:timeout_2\.Q * 
          \ibus_reader:timeout_3\.Q * ao_from_pc_strobe 
        + /\ibus_reader:il_read_stateSBV_2\.Q * \ibus_reader:timeout_0\.Q * 
          \ibus_reader:timeout_1\.Q * \ibus_reader:timeout_2\.Q * 
          \ibus_reader:timeout_3\.Q * /ao_from_pc_strobe 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          \ibus_reader:il_read_stateSBV_1\.Q * /\ibus_reader:timeout_0\.Q * 
          loopback_state.Q * to_pc_ack.Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          \ibus_reader:il_read_stateSBV_1\.Q * /\ibus_reader:timeout_0\.Q * 
          /loopback_state.Q * write_to_bp_ack.Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * \ibus_reader:timeout_0\.Q * 
          loopback_state.Q * /to_pc_ack.Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          \ibus_reader:il_read_stateSBV_2\.Q * /\ibus_reader:timeout_0\.Q * 
          loopback_state.Q * /to_pc_ack.Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * \ibus_reader:timeout_0\.Q * 
          /loopback_state.Q * /write_to_bp_ack.Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          \ibus_reader:il_read_stateSBV_2\.Q * /\ibus_reader:timeout_0\.Q * 
          /loopback_state.Q * /write_to_bp_ack.Q 
        + /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          \ibus_reader:il_read_stateSBV_2\.Q * \ibus_reader:timeout_0\.Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * \ibus_reader:timeout_0\.Q 
        + /\ibus_reader:il_read_stateSBV_0\.Q * 
          \ibus_reader:il_read_stateSBV_1\.Q * /\ibus_reader:timeout_0\.Q * 
          ao_from_pc_strobe 
        + /\ibus_reader:il_read_stateSBV_0\.Q * 
          \ibus_reader:this_is_a_ctrl_transaction\.Q * 
          \ibus_reader:timeout_0\.Q * /ao_from_pc_strobe 
        + /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * \ibus_reader:timeout_0\.Q * 
          /ao_from_pc_strobe 

    \ibus_reader:timeout_0\.AP =
          GND

    \ibus_reader:timeout_0\.AR =
          reset.CMB 

    \ibus_reader:timeout_0\.C =
          clk 

    \ibus_reader:timeout_1\.D =
          S_18.CMB 
        + S_17.CMB 

    \ibus_reader:timeout_1\.AP =
          GND

    \ibus_reader:timeout_1\.AR =
          reset.CMB 

    \ibus_reader:timeout_1\.C =
          clk 

    \ibus_reader:timeout_2\.T =
          \ibus_reader:il_read_stateSBV_0\.Q * 
          \ibus_reader:il_read_stateSBV_1\.Q * \ibus_reader:timeout_0\.Q * 
          \ibus_reader:timeout_1\.Q * /\ibus_reader:timeout_2\.Q * 
          loopback_state.Q * to_pc_ack.Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          \ibus_reader:il_read_stateSBV_1\.Q * \ibus_reader:timeout_0\.Q * 
          \ibus_reader:timeout_1\.Q * /\ibus_reader:timeout_3\.Q * 
          loopback_state.Q * to_pc_ack.Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          \ibus_reader:il_read_stateSBV_1\.Q * \ibus_reader:timeout_0\.Q * 
          \ibus_reader:timeout_1\.Q * /\ibus_reader:timeout_2\.Q * 
          /loopback_state.Q * write_to_bp_ack.Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          \ibus_reader:il_read_stateSBV_1\.Q * \ibus_reader:timeout_0\.Q * 
          \ibus_reader:timeout_1\.Q * /\ibus_reader:timeout_3\.Q * 
          /loopback_state.Q * write_to_bp_ack.Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          \ibus_reader:il_read_stateSBV_2\.Q * \ibus_reader:timeout_0\.Q * 
          \ibus_reader:timeout_1\.Q * /\ibus_reader:timeout_2\.Q * 
          loopback_state.Q * /to_pc_ack.Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          \ibus_reader:il_read_stateSBV_2\.Q * \ibus_reader:timeout_0\.Q * 
          \ibus_reader:timeout_1\.Q * /\ibus_reader:timeout_2\.Q * 
          /loopback_state.Q * /write_to_bp_ack.Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          \ibus_reader:il_read_stateSBV_2\.Q * \ibus_reader:timeout_2\.Q * 
          loopback_state.Q * to_pc_ack.Q 
        + /\ibus_reader:il_read_stateSBV_0\.Q * 
          \ibus_reader:il_read_stateSBV_1\.Q * \ibus_reader:timeout_0\.Q * 
          \ibus_reader:timeout_1\.Q * /\ibus_reader:timeout_2\.Q * 
          ao_from_pc_strobe 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          \ibus_reader:il_read_stateSBV_2\.Q * \ibus_reader:timeout_0\.Q * 
          \ibus_reader:timeout_1\.Q * \ibus_reader:timeout_2\.Q * 
          /\ibus_reader:timeout_3\.Q 
        + /\ibus_reader:il_read_stateSBV_0\.Q * 
          \ibus_reader:il_read_stateSBV_1\.Q * \ibus_reader:timeout_0\.Q * 
          \ibus_reader:timeout_1\.Q * /\ibus_reader:timeout_3\.Q * 
          ao_from_pc_strobe 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          \ibus_reader:il_read_stateSBV_2\.Q * \ibus_reader:timeout_2\.Q * 
          /ao_from_pc_strobe * loopback_state.Q * to_pc_ack.Q 
        + /\ibus_reader:il_read_stateSBV_0\.Q * 
          \ibus_reader:il_read_stateSBV_1\.Q * 
          \ibus_reader:il_read_stateSBV_2\.Q * 
          /\ibus_reader:this_is_a_ctrl_transaction\.Q * 
          \ibus_reader:timeout_2\.Q * /ao_from_pc_strobe 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          \ibus_reader:il_read_stateSBV_2\.Q * \ibus_reader:timeout_2\.Q * 
          /loopback_state.Q * write_to_bp_ack.Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          \ibus_reader:il_read_stateSBV_2\.Q * \ibus_reader:timeout_2\.Q * 
          /ao_from_pc_strobe * /loopback_state.Q * write_to_bp_ack.Q 
        + /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * \ibus_reader:timeout_2\.Q * 
          ao_from_pc_strobe 

    \ibus_reader:timeout_2\.AP =
          GND

    \ibus_reader:timeout_2\.AR =
          reset.CMB 

    \ibus_reader:timeout_2\.C =
          clk 

    \ibus_reader:timeout_3\.D =
          \ibus_reader:il_read_stateSBV_0\.Q * 
          \ibus_reader:il_read_stateSBV_1\.Q * \ibus_reader:timeout_0\.Q * 
          \ibus_reader:timeout_1\.Q * \ibus_reader:timeout_2\.Q * 
          loopback_state.Q * to_pc_ack.Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          \ibus_reader:il_read_stateSBV_1\.Q * \ibus_reader:timeout_0\.Q * 
          \ibus_reader:timeout_1\.Q * \ibus_reader:timeout_2\.Q * 
          /loopback_state.Q * write_to_bp_ack.Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          \ibus_reader:il_read_stateSBV_2\.Q * \ibus_reader:timeout_0\.Q * 
          \ibus_reader:timeout_1\.Q * \ibus_reader:timeout_2\.Q * 
          loopback_state.Q * /to_pc_ack.Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          \ibus_reader:il_read_stateSBV_2\.Q * \ibus_reader:timeout_0\.Q * 
          \ibus_reader:timeout_1\.Q * \ibus_reader:timeout_2\.Q * 
          /loopback_state.Q * /write_to_bp_ack.Q 
        + /\ibus_reader:il_read_stateSBV_0\.Q * 
          \ibus_reader:il_read_stateSBV_1\.Q * \ibus_reader:timeout_0\.Q * 
          \ibus_reader:timeout_1\.Q * \ibus_reader:timeout_2\.Q * 
          ao_from_pc_strobe 
        + /\ibus_reader:il_read_stateSBV_0\.Q * 
          \ibus_reader:il_read_stateSBV_2\.Q * \ibus_reader:timeout_3\.Q * 
          ao_from_pc_strobe 
        + /\ibus_reader:il_read_stateSBV_0\.Q * 
          \ibus_reader:this_is_a_ctrl_transaction\.Q * 
          \ibus_reader:timeout_3\.Q * /ao_from_pc_strobe 
        + /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * \ibus_reader:timeout_3\.Q * 
          /ao_from_pc_strobe 
        + \ibus_reader:il_read_stateSBV_0\.Q * \ibus_reader:timeout_3\.Q * 
          loopback_state.Q * /to_pc_ack.Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * \ibus_reader:timeout_3\.Q * 
          /loopback_state.Q * /write_to_bp_ack.Q 
        + \ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * \ibus_reader:timeout_3\.Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * \ibus_reader:timeout_3\.Q 

    \ibus_reader:timeout_3\.AP =
          GND

    \ibus_reader:timeout_3\.AR =
          reset.CMB 

    \ibus_reader:timeout_3\.C =
          clk 

    \ibus_writer:iu_writeSBV_0\.T =
          /\ibus_writer:iu_writeSBV_0\.Q * \ibus_writer:iu_writeSBV_1\.Q * 
          \ibus_writer:timeout_0\.Q * \ibus_writer:timeout_1\.Q * 
          \ibus_writer:timeout_2\.Q * \ibus_writer:timeout_3\.Q 
        + \ibus_writer:iu_writeSBV_0\.Q * \ibus_writer:timeout_0\.Q * 
          \ibus_writer:timeout_1\.Q * \ibus_writer:timeout_2\.Q * 
          \ibus_writer:timeout_3\.Q * /ao_to_pc_ack 
        + /\ibus_writer:iu_writeSBV_0\.Q * \ibus_writer:iu_writeSBV_1\.Q * 
          /from_pc_req.Q * loopback_state.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * \ibus_writer:iu_writeSBV_1\.Q * 
          /loopback_state.Q * /sensor_to_ibus_req.Q 
        + \ibus_writer:iu_writeSBV_0\.Q * \ibus_writer:iu_writeSBV_1\.Q * 
          /ao_to_pc_ack 

    \ibus_writer:iu_writeSBV_0\.AP =
          GND

    \ibus_writer:iu_writeSBV_0\.AR =
          reset.CMB 

    \ibus_writer:iu_writeSBV_0\.C =
          clk 

    \ibus_writer:iu_writeSBV_1\.T =
          /\ibus_writer:iu_writeSBV_0\.Q * \ibus_writer:iu_writeSBV_1\.Q * 
          \ibus_writer:timeout_0\.Q * \ibus_writer:timeout_1\.Q * 
          \ibus_writer:timeout_2\.Q * \ibus_writer:timeout_3\.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * \ibus_writer:iu_writeSBV_1\.Q * 
          /from_pc_req.Q * loopback_state.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * \ibus_writer:iu_writeSBV_1\.Q * 
          /loopback_state.Q * /sensor_to_ibus_req.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          from_pc_req.Q * loopback_state.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          /loopback_state.Q * sensor_to_ibus_req.Q 
        + \ibus_writer:iu_writeSBV_0\.Q * \ibus_writer:iu_writeSBV_1\.Q * 
          /ao_to_pc_ack 
        + \ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          ao_to_pc_ack 

    \ibus_writer:iu_writeSBV_1\.AP =
          GND

    \ibus_writer:iu_writeSBV_1\.AR =
          reset.CMB 

    \ibus_writer:iu_writeSBV_1\.C =
          clk 

    \ibus_writer:timeout_0\.D =
          \ibus_writer:iu_writeSBV_0\.Q * \ibus_writer:timeout_0\.Q * 
          \ibus_writer:timeout_1\.Q * \ibus_writer:timeout_2\.Q * 
          \ibus_writer:timeout_3\.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * \ibus_writer:iu_writeSBV_1\.Q * 
          /\ibus_writer:timeout_0\.Q * from_pc_req.Q * loopback_state.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          \ibus_writer:timeout_0\.Q * /from_pc_req.Q * loopback_state.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * \ibus_writer:iu_writeSBV_1\.Q * 
          /\ibus_writer:timeout_0\.Q * /loopback_state.Q * 
          sensor_to_ibus_req.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          \ibus_writer:timeout_0\.Q * /loopback_state.Q * 
          /sensor_to_ibus_req.Q 
        + \ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          /\ibus_writer:timeout_0\.Q * /ao_to_pc_ack 
        + \ibus_writer:iu_writeSBV_0\.Q * \ibus_writer:timeout_0\.Q * 
          ao_to_pc_ack 
        + \ibus_writer:iu_writeSBV_0\.Q * \ibus_writer:iu_writeSBV_1\.Q * 
          \ibus_writer:timeout_0\.Q 

    \ibus_writer:timeout_0\.AP =
          GND

    \ibus_writer:timeout_0\.AR =
          reset.CMB 

    \ibus_writer:timeout_0\.C =
          clk 

    \ibus_writer:timeout_1\.T =
          /\ibus_writer:iu_writeSBV_0\.Q * \ibus_writer:iu_writeSBV_1\.Q * 
          \ibus_writer:timeout_0\.Q * from_pc_req.Q * loopback_state.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          \ibus_writer:timeout_1\.Q * from_pc_req.Q * loopback_state.Q 
        + \ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          \ibus_writer:timeout_0\.Q * /\ibus_writer:timeout_1\.Q * 
          /ao_to_pc_ack 
        + \ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          \ibus_writer:timeout_0\.Q * /\ibus_writer:timeout_2\.Q * 
          /ao_to_pc_ack 
        + \ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          \ibus_writer:timeout_0\.Q * /\ibus_writer:timeout_3\.Q * 
          /ao_to_pc_ack 
        + /\ibus_writer:iu_writeSBV_0\.Q * \ibus_writer:iu_writeSBV_1\.Q * 
          \ibus_writer:timeout_1\.Q * /from_pc_req.Q * loopback_state.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * \ibus_writer:iu_writeSBV_1\.Q * 
          \ibus_writer:timeout_0\.Q * /loopback_state.Q * 
          sensor_to_ibus_req.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          \ibus_writer:timeout_1\.Q * /loopback_state.Q * 
          sensor_to_ibus_req.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * \ibus_writer:iu_writeSBV_1\.Q * 
          \ibus_writer:timeout_1\.Q * /loopback_state.Q * 
          /sensor_to_ibus_req.Q 

    \ibus_writer:timeout_1\.AP =
          GND

    \ibus_writer:timeout_1\.AR =
          reset.CMB 

    \ibus_writer:timeout_1\.C =
          clk 

    \ibus_writer:timeout_2\.T =
          /\ibus_writer:iu_writeSBV_0\.Q * \ibus_writer:iu_writeSBV_1\.Q * 
          \ibus_writer:timeout_0\.Q * \ibus_writer:timeout_1\.Q * 
          from_pc_req.Q * loopback_state.Q 
        + \ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          \ibus_writer:timeout_0\.Q * \ibus_writer:timeout_1\.Q * 
          /\ibus_writer:timeout_2\.Q * /ao_to_pc_ack 
        + \ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          \ibus_writer:timeout_0\.Q * \ibus_writer:timeout_1\.Q * 
          /\ibus_writer:timeout_3\.Q * /ao_to_pc_ack 
        + /\ibus_writer:iu_writeSBV_0\.Q * \ibus_writer:iu_writeSBV_1\.Q * 
          \ibus_writer:timeout_0\.Q * \ibus_writer:timeout_1\.Q * 
          /loopback_state.Q * sensor_to_ibus_req.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          \ibus_writer:timeout_2\.Q * from_pc_req.Q * loopback_state.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * \ibus_writer:iu_writeSBV_1\.Q * 
          \ibus_writer:timeout_2\.Q * /from_pc_req.Q * loopback_state.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          \ibus_writer:timeout_2\.Q * /loopback_state.Q * 
          sensor_to_ibus_req.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * \ibus_writer:iu_writeSBV_1\.Q * 
          \ibus_writer:timeout_2\.Q * /loopback_state.Q * 
          /sensor_to_ibus_req.Q 

    \ibus_writer:timeout_2\.AP =
          GND

    \ibus_writer:timeout_2\.AR =
          reset.CMB 

    \ibus_writer:timeout_2\.C =
          clk 

    \ibus_writer:timeout_3\.T =
          /\ibus_writer:iu_writeSBV_0\.Q * \ibus_writer:iu_writeSBV_1\.Q * 
          \ibus_writer:timeout_0\.Q * \ibus_writer:timeout_1\.Q * 
          \ibus_writer:timeout_2\.Q * from_pc_req.Q * loopback_state.Q 
        + \ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          \ibus_writer:timeout_0\.Q * \ibus_writer:timeout_1\.Q * 
          \ibus_writer:timeout_2\.Q * /\ibus_writer:timeout_3\.Q * 
          /ao_to_pc_ack 
        + /\ibus_writer:iu_writeSBV_0\.Q * \ibus_writer:iu_writeSBV_1\.Q * 
          \ibus_writer:timeout_0\.Q * \ibus_writer:timeout_1\.Q * 
          \ibus_writer:timeout_2\.Q * /loopback_state.Q * 
          sensor_to_ibus_req.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          \ibus_writer:timeout_3\.Q * from_pc_req.Q * loopback_state.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * \ibus_writer:iu_writeSBV_1\.Q * 
          \ibus_writer:timeout_3\.Q * /from_pc_req.Q * loopback_state.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          \ibus_writer:timeout_3\.Q * /loopback_state.Q * 
          sensor_to_ibus_req.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * \ibus_writer:iu_writeSBV_1\.Q * 
          \ibus_writer:timeout_3\.Q * /loopback_state.Q * 
          /sensor_to_ibus_req.Q 

    \ibus_writer:timeout_3\.AP =
          GND

    \ibus_writer:timeout_3\.AR =
          reset.CMB 

    \ibus_writer:timeout_3\.C =
          clk 

    /\sp_read:cmp_vv_us_MODGEN_10\ =
          /\sp_read:counter_address_0\.Q * bp_end_address_0.Q 
        + /\sp_read:counter_address_1\.Q * bp_end_address_1.Q 
        + /\sp_read:counter_address_2\.Q * bp_end_address_2.Q 
        + /\sp_read:counter_address_3\.Q * bp_end_address_3.Q 
        + /\sp_read:counter_address_4\.Q * bp_end_address_4.Q 
        + /\sp_read:counter_address_5\.Q * bp_end_address_5.Q 
        + /\sp_read:counter_address_6\.Q * bp_end_address_6.Q 
        + /\sp_read:counter_address_7\.Q * bp_end_address_7.Q 
        + \sp_read:counter_address_0\.Q * /bp_end_address_0.Q 
        + \sp_read:counter_address_1\.Q * /bp_end_address_1.Q 
        + \sp_read:counter_address_2\.Q * /bp_end_address_2.Q 
        + \sp_read:counter_address_3\.Q * /bp_end_address_3.Q 
        + \sp_read:counter_address_4\.Q * /bp_end_address_4.Q 
        + \sp_read:counter_address_5\.Q * /bp_end_address_5.Q 
        + \sp_read:counter_address_6\.Q * /bp_end_address_6.Q 
        + \sp_read:counter_address_7\.Q * /bp_end_address_7.Q 

    \sp_read:counter_address_0\.D =
          S_16.CMB 
        + S_15.CMB 

    \sp_read:counter_address_0\.AP =
          GND

    \sp_read:counter_address_0\.AR =
          reset.CMB 

    \sp_read:counter_address_0\.C =
          clk 

    \sp_read:counter_address_1\.D =
          S_14.CMB 
        + S_13.CMB 

    \sp_read:counter_address_1\.AP =
          GND

    \sp_read:counter_address_1\.AR =
          reset.CMB 

    \sp_read:counter_address_1\.C =
          clk 

    \sp_read:counter_address_2\.D =
          S_12.CMB 
        + S_11.CMB 

    \sp_read:counter_address_2\.AP =
          GND

    \sp_read:counter_address_2\.AR =
          reset.CMB 

    \sp_read:counter_address_2\.C =
          clk 

    \sp_read:counter_address_3\.D =
          S_9.CMB 
        + S_10.CMB 

    \sp_read:counter_address_3\.AP =
          GND

    \sp_read:counter_address_3\.AR =
          reset.CMB 

    \sp_read:counter_address_3\.C =
          clk 

    \sp_read:counter_address_4\.D =
          S_8.CMB 
        + S_7.CMB 

    \sp_read:counter_address_4\.AP =
          GND

    \sp_read:counter_address_4\.AR =
          reset.CMB 

    \sp_read:counter_address_4\.C =
          clk 

    \sp_read:counter_address_5\.D =
          S_6.CMB 
        + S_5.CMB 

    \sp_read:counter_address_5\.AP =
          GND

    \sp_read:counter_address_5\.AR =
          reset.CMB 

    \sp_read:counter_address_5\.C =
          clk 

    \sp_read:counter_address_6\.D =
          S_4.CMB 
        + S_3.CMB 

    \sp_read:counter_address_6\.AP =
          GND

    \sp_read:counter_address_6\.AR =
          reset.CMB 

    \sp_read:counter_address_6\.C =
          clk 

    \sp_read:counter_address_7\.D =
          S_2.CMB 
        + S_1.CMB 

    \sp_read:counter_address_7\.AP =
          GND

    \sp_read:counter_address_7\.AR =
          reset.CMB 

    \sp_read:counter_address_7\.C =
          clk 

    \sp_read:counter_read_stateSBV_0\.D =
          \sp_read:cmp_vv_us_MODGEN_10\.CMB * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          \sp_read:counter_read_stateSBV_2\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q 
        + \sp_read:counter_read_stateSBV_0\.Q * /\sp_read:reset_count_0\.Q 
        + \sp_read:counter_read_stateSBV_0\.Q * /\sp_read:reset_count_1\.Q 
        + \sp_read:counter_read_stateSBV_0\.Q * /\sp_read:reset_count_2\.Q 

    \sp_read:counter_read_stateSBV_0\.AP =
          GND

    \sp_read:counter_read_stateSBV_0\.AR =
          reset.CMB 

    \sp_read:counter_read_stateSBV_0\.C =
          clk 

    \sp_read:counter_read_stateSBV_1\.T =
          \sp_read:counter_read_stateSBV_1\.Q * 
          \sp_read:counter_read_stateSBV_2\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q * loopback_state.Q 
        + /\sp_read:counter_address_3\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q 
        + /\sp_read:counter_address_4\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q 
        + \sp_read:counter_read_stateSBV_1\.Q * 
          \sp_read:counter_read_stateSBV_2\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q * /to_pc_ack.Q 

    \sp_read:counter_read_stateSBV_1\.AP =
          GND

    \sp_read:counter_read_stateSBV_1\.AR =
          reset.CMB 

    \sp_read:counter_read_stateSBV_1\.C =
          clk 

    \sp_read:counter_read_stateSBV_2\.D =
          /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          /bp_end_address_0.Q * /bp_end_address_1.Q * /bp_end_address_2.Q * 
          /bp_end_address_3.Q * /bp_end_address_4.Q * /bp_end_address_5.Q * 
          /bp_end_address_6.Q * /bp_end_address_7.Q * hva_chassis_en_l * 
          sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          /bp_end_address_0.Q * /bp_end_address_1.Q * /bp_end_address_2.Q * 
          /bp_end_address_3.Q * /bp_end_address_4.Q * /bp_end_address_5.Q * 
          /bp_end_address_6.Q * /bp_end_address_7.Q * hva_chassis_en_l * 
          /sinphase_zeros 
        + \sp_read:counter_address_3\.Q * \sp_read:counter_address_4\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q 
        + /\sp_read:cmp_vv_us_MODGEN_10\.CMB * 
          \sp_read:counter_read_stateSBV_2\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q 
        + \sp_read:counter_read_stateSBV_1\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q * /sensor_to_bp_read_ack.Q 
        + \sp_read:counter_read_stateSBV_1\.Q * 
          \sp_read:counter_read_stateSBV_2\.Q 

    \sp_read:counter_read_stateSBV_2\.AP =
          GND

    \sp_read:counter_read_stateSBV_2\.AR =
          reset.CMB 

    \sp_read:counter_read_stateSBV_2\.C =
          clk 

    \sp_read:counter_read_stateSBV_3\.D =
          /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          hva_chassis_en_l * sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          hva_chassis_en_l * /sinphase_zeros 
        + \sp_read:counter_address_3\.Q * \sp_read:counter_address_4\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q 
        + \sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /loopback_state.Q * 
          to_pc_ack.Q 
        + \sp_read:counter_read_stateSBV_1\.Q * 
          \sp_read:counter_read_stateSBV_2\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q 
        + \sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * sensor_to_bp_read_ack.Q 
        + /\sp_read:counter_read_stateSBV_1\.Q * 
          \sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q 

    \sp_read:counter_read_stateSBV_3\.AP =
          GND

    \sp_read:counter_read_stateSBV_3\.AR =
          reset.CMB 

    \sp_read:counter_read_stateSBV_3\.C =
          clk 

    \sp_read:old_phase\.D =
          sinphase_zeros 

    \sp_read:old_phase\.AP =
          fast * sinphase_zeros * /slow 

    \sp_read:old_phase\.AR =
          fast * /sinphase_zeros * /slow 

    \sp_read:old_phase\.C =
          clk 

    \sp_read:reset_count_0\.D =
          \sp_read:counter_read_stateSBV_0\.Q * /\sp_read:reset_count_0\.Q 

    \sp_read:reset_count_0\.AP =
          GND

    \sp_read:reset_count_0\.AR =
          reset.CMB 

    \sp_read:reset_count_0\.C =
          clk 

    \sp_read:reset_count_1\.D =
          \sp_read:counter_read_stateSBV_0\.Q * /\sp_read:reset_count_0\.Q * 
          \sp_read:reset_count_1\.Q 
        + \sp_read:counter_read_stateSBV_0\.Q * \sp_read:reset_count_0\.Q * 
          /\sp_read:reset_count_1\.Q 

    \sp_read:reset_count_1\.AP =
          GND

    \sp_read:reset_count_1\.AR =
          reset.CMB 

    \sp_read:reset_count_1\.C =
          clk 

    \sp_read:reset_count_2\.T =
          \sp_read:counter_read_stateSBV_0\.Q * \sp_read:reset_count_0\.Q * 
          \sp_read:reset_count_1\.Q 
        + /\sp_read:counter_read_stateSBV_0\.Q * \sp_read:reset_count_2\.Q 

    \sp_read:reset_count_2\.AP =
          GND

    \sp_read:reset_count_2\.AR =
          reset.CMB 

    \sp_read:reset_count_2\.C =
          clk 

    address_from_pc_0.T =
          /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          \ibus_reader:il_read_stateSBV_2\.Q * /address_from_pc_0.Q * 
          /bpctrl(10).Q * bpctrl(11).Q * /bpctrl(7).Q * /bpctrl(8).Q * 
          bpd(10).Q * data_from_pc_15.Q 
        + /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          \ibus_reader:il_read_stateSBV_2\.Q * address_from_pc_0.Q * 
          /bpctrl(10).Q * bpctrl(11).Q * /bpctrl(7).Q * /bpctrl(8).Q * 
          /bpd(10).Q * data_from_pc_15.Q 

    address_from_pc_0.AP =
          GND

    address_from_pc_0.AR =
          reset.CMB 

    address_from_pc_0.C =
          clk 

    address_from_pc_1.T =
          /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          \ibus_reader:il_read_stateSBV_2\.Q * /address_from_pc_1.Q * 
          /bpctrl(10).Q * bpctrl(11).Q * /bpctrl(7).Q * /bpctrl(8).Q * 
          bpd(11).Q * data_from_pc_15.Q 
        + /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          \ibus_reader:il_read_stateSBV_2\.Q * address_from_pc_1.Q * 
          /bpctrl(10).Q * bpctrl(11).Q * /bpctrl(7).Q * /bpctrl(8).Q * 
          /bpd(11).Q * data_from_pc_15.Q 

    address_from_pc_1.AP =
          GND

    address_from_pc_1.AR =
          reset.CMB 

    address_from_pc_1.C =
          clk 

    address_from_pc_2.T =
          /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          \ibus_reader:il_read_stateSBV_2\.Q * /address_from_pc_2.Q * 
          /bpctrl(10).Q * bpctrl(11).Q * /bpctrl(7).Q * /bpctrl(8).Q * 
          bpd(12).Q * data_from_pc_15.Q 
        + /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          \ibus_reader:il_read_stateSBV_2\.Q * address_from_pc_2.Q * 
          /bpctrl(10).Q * bpctrl(11).Q * /bpctrl(7).Q * /bpctrl(8).Q * 
          /bpd(12).Q * data_from_pc_15.Q 

    address_from_pc_2.AP =
          GND

    address_from_pc_2.AR =
          reset.CMB 

    address_from_pc_2.C =
          clk 

    address_from_pc_3.T =
          /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          \ibus_reader:il_read_stateSBV_2\.Q * /address_from_pc_3.Q * 
          /bpctrl(10).Q * bpctrl(11).Q * /bpctrl(7).Q * /bpctrl(8).Q * 
          bpd(13).Q * data_from_pc_15.Q 
        + /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          \ibus_reader:il_read_stateSBV_2\.Q * address_from_pc_3.Q * 
          /bpctrl(10).Q * bpctrl(11).Q * /bpctrl(7).Q * /bpctrl(8).Q * 
          /bpd(13).Q * data_from_pc_15.Q 

    address_from_pc_3.AP =
          GND

    address_from_pc_3.AR =
          reset.CMB 

    address_from_pc_3.C =
          clk 

    address_from_pc_4.T =
          /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          \ibus_reader:il_read_stateSBV_2\.Q * /address_from_pc_4.Q * 
          /bpctrl(10).Q * bpctrl(11).Q * /bpctrl(7).Q * /bpctrl(8).Q * 
          bpd(14).Q * data_from_pc_15.Q 
        + /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          \ibus_reader:il_read_stateSBV_2\.Q * address_from_pc_4.Q * 
          /bpctrl(10).Q * bpctrl(11).Q * /bpctrl(7).Q * /bpctrl(8).Q * 
          /bpd(14).Q * data_from_pc_15.Q 

    address_from_pc_4.AP =
          GND

    address_from_pc_4.AR =
          reset.CMB 

    address_from_pc_4.C =
          clk 

    address_from_pc_5.T =
          /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          \ibus_reader:il_read_stateSBV_2\.Q * /address_from_pc_5.Q * 
          /bpctrl(10).Q * bpctrl(11).Q * /bpctrl(7).Q * /bpctrl(8).Q * 
          bpd(15).Q * data_from_pc_15.Q 
        + /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          \ibus_reader:il_read_stateSBV_2\.Q * address_from_pc_5.Q * 
          /bpctrl(10).Q * bpctrl(11).Q * /bpctrl(7).Q * /bpctrl(8).Q * 
          /bpd(15).Q * data_from_pc_15.Q 

    address_from_pc_5.AP =
          GND

    address_from_pc_5.AR =
          reset.CMB 

    address_from_pc_5.C =
          clk 

    address_from_pc_6.T =
          /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          \ibus_reader:il_read_stateSBV_2\.Q * /address_from_pc_6.Q * 
          /bpctrl(10).Q * bpctrl(11).Q * bpctrl(4).Q * /bpctrl(7).Q * 
          /bpctrl(8).Q * data_from_pc_15.Q 
        + /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          \ibus_reader:il_read_stateSBV_2\.Q * address_from_pc_6.Q * 
          /bpctrl(10).Q * bpctrl(11).Q * /bpctrl(4).Q * /bpctrl(7).Q * 
          /bpctrl(8).Q * data_from_pc_15.Q 

    address_from_pc_6.AP =
          GND

    address_from_pc_6.AR =
          reset.CMB 

    address_from_pc_6.C =
          clk 

    address_from_pc_7.T =
          /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          \ibus_reader:il_read_stateSBV_2\.Q * /address_from_pc_7.Q * 
          /bpctrl(10).Q * bpctrl(11).Q * bpctrl(5).Q * /bpctrl(7).Q * 
          /bpctrl(8).Q * data_from_pc_15.Q 
        + /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          \ibus_reader:il_read_stateSBV_2\.Q * address_from_pc_7.Q * 
          /bpctrl(10).Q * bpctrl(11).Q * /bpctrl(5).Q * /bpctrl(7).Q * 
          /bpctrl(8).Q * data_from_pc_15.Q 

    address_from_pc_7.AP =
          GND

    address_from_pc_7.AR =
          reset.CMB 

    address_from_pc_7.C =
          clk 

    ao_from_pc_ack.D =
          /\ibus_reader:il_read_stateSBV_0\.Q * 
          \ibus_reader:il_read_stateSBV_1\.Q 

    ao_from_pc_ack.AP =
          GND

    ao_from_pc_ack.AR =
          reset.CMB 

    ao_from_pc_ack.C =
          clk 

    ao_from_pc_ack.OE =
          /il_tristate.Q 

    ao_to_pc_strobe.D =
          \ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          /ao_to_pc_ack 
        + /\ibus_writer:iu_writeSBV_0\.Q * \ibus_writer:iu_writeSBV_1\.Q 

    ao_to_pc_strobe.AP =
          GND

    ao_to_pc_strobe.AR =
          reset.CMB 

    ao_to_pc_strobe.C =
          clk 

    /bp_end_address_0.T =
          \ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * address_from_pc_0.Q * 
          /address_from_pc_1.Q * /bp_end_address_0.Q * bpctrl(6).Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * address_from_pc_0.Q * 
          /address_from_pc_1.Q * bp_end_address_0.Q * /bpctrl(6).Q 

    bp_end_address_0.AP =
          GND

    bp_end_address_0.AR =
          reset.CMB 

    bp_end_address_0.C =
          clk 

    /bp_end_address_1.T =
          \ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * address_from_pc_0.Q * 
          /address_from_pc_1.Q * /bp_end_address_1.Q * bpctrl(7).Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * address_from_pc_0.Q * 
          /address_from_pc_1.Q * bp_end_address_1.Q * /bpctrl(7).Q 

    bp_end_address_1.AP =
          GND

    bp_end_address_1.AR =
          reset.CMB 

    bp_end_address_1.C =
          clk 

    /bp_end_address_2.T =
          \ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * address_from_pc_0.Q * 
          /address_from_pc_1.Q * /bp_end_address_2.Q * bpctrl(8).Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * address_from_pc_0.Q * 
          /address_from_pc_1.Q * bp_end_address_2.Q * /bpctrl(8).Q 

    bp_end_address_2.AP =
          GND

    bp_end_address_2.AR =
          reset.CMB 

    bp_end_address_2.C =
          clk 

    /bp_end_address_3.T =
          \ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * address_from_pc_0.Q * 
          /address_from_pc_1.Q * /bp_end_address_3.Q * bpctrl(10).Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * address_from_pc_0.Q * 
          /address_from_pc_1.Q * bp_end_address_3.Q * /bpctrl(10).Q 

    bp_end_address_3.AP =
          GND

    bp_end_address_3.AR =
          reset.CMB 

    bp_end_address_3.C =
          clk 

    /bp_end_address_4.T =
          \ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * address_from_pc_0.Q * 
          /address_from_pc_1.Q * /bp_end_address_4.Q * bpctrl(11).Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * address_from_pc_0.Q * 
          /address_from_pc_1.Q * bp_end_address_4.Q * /bpctrl(11).Q 

    bp_end_address_4.AP =
          GND

    bp_end_address_4.AR =
          reset.CMB 

    bp_end_address_4.C =
          clk 

    /bp_end_address_5.T =
          \ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * address_from_pc_0.Q * 
          /address_from_pc_1.Q * /bp_end_address_5.Q * data_from_pc_13.Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * address_from_pc_0.Q * 
          /address_from_pc_1.Q * bp_end_address_5.Q * /data_from_pc_13.Q 

    bp_end_address_5.AP =
          GND

    bp_end_address_5.AR =
          reset.CMB 

    bp_end_address_5.C =
          clk 

    /bp_end_address_6.T =
          \ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * address_from_pc_0.Q * 
          /address_from_pc_1.Q * /bp_end_address_6.Q * data_from_pc_14.Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * address_from_pc_0.Q * 
          /address_from_pc_1.Q * bp_end_address_6.Q * /data_from_pc_14.Q 

    bp_end_address_6.AP =
          GND

    bp_end_address_6.AR =
          reset.CMB 

    bp_end_address_6.C =
          clk 

    /bp_end_address_7.T =
          \ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * address_from_pc_0.Q * 
          /address_from_pc_1.Q * /bp_end_address_7.Q * data_from_pc_15.Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * address_from_pc_0.Q * 
          /address_from_pc_1.Q * bp_end_address_7.Q * /data_from_pc_15.Q 

    bp_end_address_7.AP =
          GND

    bp_end_address_7.AR =
          reset.CMB 

    bp_end_address_7.C =
          clk 

    /bp_start_address_0.T =
          \ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * address_from_pc_0.Q * 
          /address_from_pc_1.Q * /bp_start_address_0.Q * bpd(10).Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * address_from_pc_0.Q * 
          /address_from_pc_1.Q * bp_start_address_0.Q * /bpd(10).Q 

    bp_start_address_0.AP =
          GND

    bp_start_address_0.AR =
          reset.CMB 

    bp_start_address_0.C =
          clk 

    /bp_start_address_1.T =
          \ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * address_from_pc_0.Q * 
          /address_from_pc_1.Q * /bp_start_address_1.Q * bpd(11).Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * address_from_pc_0.Q * 
          /address_from_pc_1.Q * bp_start_address_1.Q * /bpd(11).Q 

    bp_start_address_1.AP =
          GND

    bp_start_address_1.AR =
          reset.CMB 

    bp_start_address_1.C =
          clk 

    /bp_start_address_2.T =
          \ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * address_from_pc_0.Q * 
          /address_from_pc_1.Q * /bp_start_address_2.Q * bpd(12).Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * address_from_pc_0.Q * 
          /address_from_pc_1.Q * bp_start_address_2.Q * /bpd(12).Q 

    bp_start_address_2.AP =
          GND

    bp_start_address_2.AR =
          reset.CMB 

    bp_start_address_2.C =
          clk 

    /bp_start_address_3.T =
          \ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * address_from_pc_0.Q * 
          /address_from_pc_1.Q * /bp_start_address_3.Q * bpd(13).Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * address_from_pc_0.Q * 
          /address_from_pc_1.Q * bp_start_address_3.Q * /bpd(13).Q 

    bp_start_address_3.AP =
          GND

    bp_start_address_3.AR =
          reset.CMB 

    bp_start_address_3.C =
          clk 

    /bp_start_address_4.T =
          \ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * address_from_pc_0.Q * 
          /address_from_pc_1.Q * /bp_start_address_4.Q * bpd(14).Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * address_from_pc_0.Q * 
          /address_from_pc_1.Q * bp_start_address_4.Q * /bpd(14).Q 

    bp_start_address_4.AP =
          GND

    bp_start_address_4.AR =
          reset.CMB 

    bp_start_address_4.C =
          clk 

    /bp_start_address_5.T =
          \ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * address_from_pc_0.Q * 
          /address_from_pc_1.Q * /bp_start_address_5.Q * bpd(15).Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * address_from_pc_0.Q * 
          /address_from_pc_1.Q * bp_start_address_5.Q * /bpd(15).Q 

    bp_start_address_5.AP =
          GND

    bp_start_address_5.AR =
          reset.CMB 

    bp_start_address_5.C =
          clk 

    /bp_start_address_6.T =
          \ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * address_from_pc_0.Q * 
          /address_from_pc_1.Q * /bp_start_address_6.Q * bpctrl(4).Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * address_from_pc_0.Q * 
          /address_from_pc_1.Q * bp_start_address_6.Q * /bpctrl(4).Q 

    bp_start_address_6.AP =
          GND

    bp_start_address_6.AR =
          reset.CMB 

    bp_start_address_6.C =
          clk 

    /bp_start_address_7.T =
          \ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * address_from_pc_0.Q * 
          /address_from_pc_1.Q * /bp_start_address_7.Q * bpctrl(5).Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * address_from_pc_0.Q * 
          /address_from_pc_1.Q * bp_start_address_7.Q * /bpctrl(5).Q 

    bp_start_address_7.AP =
          GND

    bp_start_address_7.AR =
          reset.CMB 

    bp_start_address_7.C =
          clk 

    bpaddr(0).T =
          /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /bpaddr(0).Q * 
          loopback_state.Q * sensor_address_0.Q * sensor_to_bp_read_req.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /bpaddr(0).Q * /from_pc_req.Q * 
          sensor_address_0.Q * sensor_to_bp_read_req.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /address_from_pc_0.Q * 
          bpaddr(0).Q * from_pc_req.Q * /loopback_state.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * address_from_pc_0.Q * 
          /bpaddr(0).Q * from_pc_req.Q * /loopback_state.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * bpaddr(0).Q * loopback_state.Q * 
          /sensor_address_0.Q * sensor_to_bp_read_req.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * bpaddr(0).Q * /from_pc_req.Q * 
          /sensor_address_0.Q * sensor_to_bp_read_req.Q 

    bpaddr(0).AP =
          GND

    bpaddr(0).AR =
          reset.CMB 

    bpaddr(0).C =
          clk 

    bpaddr(1).T =
          /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /bpaddr(1).Q * 
          loopback_state.Q * sensor_address_1.Q * sensor_to_bp_read_req.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /bpaddr(1).Q * /from_pc_req.Q * 
          sensor_address_1.Q * sensor_to_bp_read_req.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /address_from_pc_1.Q * 
          bpaddr(1).Q * from_pc_req.Q * /loopback_state.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * address_from_pc_1.Q * 
          /bpaddr(1).Q * from_pc_req.Q * /loopback_state.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * bpaddr(1).Q * loopback_state.Q * 
          /sensor_address_1.Q * sensor_to_bp_read_req.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * bpaddr(1).Q * /from_pc_req.Q * 
          /sensor_address_1.Q * sensor_to_bp_read_req.Q 

    bpaddr(1).AP =
          GND

    bpaddr(1).AR =
          reset.CMB 

    bpaddr(1).C =
          clk 

    bpaddr(2).T =
          /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /bpaddr(2).Q * 
          loopback_state.Q * sensor_address_2.Q * sensor_to_bp_read_req.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /bpaddr(2).Q * /from_pc_req.Q * 
          sensor_address_2.Q * sensor_to_bp_read_req.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /address_from_pc_2.Q * 
          bpaddr(2).Q * from_pc_req.Q * /loopback_state.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * address_from_pc_2.Q * 
          /bpaddr(2).Q * from_pc_req.Q * /loopback_state.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * bpaddr(2).Q * loopback_state.Q * 
          /sensor_address_2.Q * sensor_to_bp_read_req.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * bpaddr(2).Q * /from_pc_req.Q * 
          /sensor_address_2.Q * sensor_to_bp_read_req.Q 

    bpaddr(2).AP =
          GND

    bpaddr(2).AR =
          reset.CMB 

    bpaddr(2).C =
          clk 

    bpaddr(3).T =
          /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /bpaddr(3).Q * 
          loopback_state.Q * sensor_address_3.Q * sensor_to_bp_read_req.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /bpaddr(3).Q * /from_pc_req.Q * 
          sensor_address_3.Q * sensor_to_bp_read_req.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /address_from_pc_3.Q * 
          bpaddr(3).Q * from_pc_req.Q * /loopback_state.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * address_from_pc_3.Q * 
          /bpaddr(3).Q * from_pc_req.Q * /loopback_state.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * bpaddr(3).Q * loopback_state.Q * 
          /sensor_address_3.Q * sensor_to_bp_read_req.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * bpaddr(3).Q * /from_pc_req.Q * 
          /sensor_address_3.Q * sensor_to_bp_read_req.Q 

    bpaddr(3).AP =
          GND

    bpaddr(3).AR =
          reset.CMB 

    bpaddr(3).C =
          clk 

    bpaddr(4).T =
          /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /bpaddr(4).Q * 
          loopback_state.Q * sensor_address_4.Q * sensor_to_bp_read_req.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /bpaddr(4).Q * /from_pc_req.Q * 
          sensor_address_4.Q * sensor_to_bp_read_req.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /address_from_pc_4.Q * 
          bpaddr(4).Q * from_pc_req.Q * /loopback_state.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * address_from_pc_4.Q * 
          /bpaddr(4).Q * from_pc_req.Q * /loopback_state.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * bpaddr(4).Q * loopback_state.Q * 
          /sensor_address_4.Q * sensor_to_bp_read_req.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * bpaddr(4).Q * /from_pc_req.Q * 
          /sensor_address_4.Q * sensor_to_bp_read_req.Q 

    bpaddr(4).AP =
          GND

    bpaddr(4).AR =
          reset.CMB 

    bpaddr(4).C =
          clk 

    bpaddr(5).T =
          /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /bpaddr(5).Q * 
          loopback_state.Q * sensor_address_5.Q * sensor_to_bp_read_req.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /bpaddr(5).Q * /from_pc_req.Q * 
          sensor_address_5.Q * sensor_to_bp_read_req.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /address_from_pc_5.Q * 
          bpaddr(5).Q * from_pc_req.Q * /loopback_state.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * address_from_pc_5.Q * 
          /bpaddr(5).Q * from_pc_req.Q * /loopback_state.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * bpaddr(5).Q * loopback_state.Q * 
          /sensor_address_5.Q * sensor_to_bp_read_req.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * bpaddr(5).Q * /from_pc_req.Q * 
          /sensor_address_5.Q * sensor_to_bp_read_req.Q 

    bpaddr(5).AP =
          GND

    bpaddr(5).AR =
          reset.CMB 

    bpaddr(5).C =
          clk 

    bpaddr(6).T =
          /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /bpaddr(6).Q * 
          loopback_state.Q * sensor_address_6.Q * sensor_to_bp_read_req.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /bpaddr(6).Q * /from_pc_req.Q * 
          sensor_address_6.Q * sensor_to_bp_read_req.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /address_from_pc_6.Q * 
          bpaddr(6).Q * from_pc_req.Q * /loopback_state.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * address_from_pc_6.Q * 
          /bpaddr(6).Q * from_pc_req.Q * /loopback_state.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * bpaddr(6).Q * loopback_state.Q * 
          /sensor_address_6.Q * sensor_to_bp_read_req.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * bpaddr(6).Q * /from_pc_req.Q * 
          /sensor_address_6.Q * sensor_to_bp_read_req.Q 

    bpaddr(6).AP =
          GND

    bpaddr(6).AR =
          reset.CMB 

    bpaddr(6).C =
          clk 

    bpaddr(7).T =
          /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /bpaddr(7).Q * 
          loopback_state.Q * sensor_address_7.Q * sensor_to_bp_read_req.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /bpaddr(7).Q * /from_pc_req.Q * 
          sensor_address_7.Q * sensor_to_bp_read_req.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /address_from_pc_7.Q * 
          bpaddr(7).Q * from_pc_req.Q * /loopback_state.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * address_from_pc_7.Q * 
          /bpaddr(7).Q * from_pc_req.Q * /loopback_state.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * bpaddr(7).Q * loopback_state.Q * 
          /sensor_address_7.Q * sensor_to_bp_read_req.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * bpaddr(7).Q * /from_pc_req.Q * 
          /sensor_address_7.Q * sensor_to_bp_read_req.Q 

    bpaddr(7).AP =
          GND

    bpaddr(7).AR =
          reset.CMB 

    bpaddr(7).C =
          clk 

    bpaddr_dir =
          GND

    /bpaddr_tristate.D =
          /\bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_2\.Q 
        + /\bp_io:bp_access_stateSBV_1\.Q * \bp_io:bp_access_stateSBV_2\.Q 
        + \bp_io:bp_access_stateSBV_1\.Q * /\bp_io:bp_access_stateSBV_2\.Q 

    bpaddr_tristate.AP =
          GND

    bpaddr_tristate.AR =
          reset.CMB 

    bpaddr_tristate.C =
          clk 

    bpctrl(0).D =
          /\bp_io:bp_access_stateSBV_0\.Q * from_pc_req.Q * 
          /loopback_state.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_2\.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_1\.Q 

    bpctrl(0).AP =
          GND

    bpctrl(0).AR =
          reset.CMB 

    bpctrl(0).C =
          clk 

    bpctrl(1) =
          sinphase_zeros 

    bpctrl(10).T =
          /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * ao_from_pc_strobe * 
          /bpctrl(10).Q * d(11) 
        + /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * ao_from_pc_strobe * 
          bpctrl(10).Q * /d(11) 

    bpctrl(10).AP =
          GND

    bpctrl(10).AR =
          reset.CMB 

    bpctrl(10).C =
          clk 

    bpctrl(10).OE =
          bpctrl(0).Q 

    bpctrl(11).T =
          /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * ao_from_pc_strobe * 
          /bpctrl(11).Q * d(12) 
        + /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * ao_from_pc_strobe * 
          bpctrl(11).Q * /d(12) 

    bpctrl(11).AP =
          GND

    bpctrl(11).AR =
          reset.CMB 

    bpctrl(11).C =
          clk 

    bpctrl(11).OE =
          bpctrl(0).Q 

    bpctrl(2).D =
          /\bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_1\.Q * 
          \bp_io:bp_access_stateSBV_2\.Q 
        + \bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q 

    bpctrl(2).AP =
          GND

    bpctrl(2).AR =
          reset.CMB 

    bpctrl(2).C =
          clk 

    bpctrl(3).D =
          \sp_read:counter_read_stateSBV_0\.Q * /\sp_read:reset_count_0\.Q 
        + \sp_read:counter_read_stateSBV_0\.Q * /\sp_read:reset_count_1\.Q 
        + \sp_read:counter_read_stateSBV_0\.Q * /\sp_read:reset_count_2\.Q 

    bpctrl(3).AP =
          GND

    bpctrl(3).AR =
          reset.CMB 

    bpctrl(3).C =
          clk 

    bpctrl(4).T =
          /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * ao_from_pc_strobe * 
          /bpctrl(4).Q * d(6) 
        + /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * ao_from_pc_strobe * 
          bpctrl(4).Q * /d(6) 

    bpctrl(4).AP =
          GND

    bpctrl(4).AR =
          reset.CMB 

    bpctrl(4).C =
          clk 

    bpctrl(4).OE =
          bpctrl(0).Q 

    bpctrl(5).T =
          /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * ao_from_pc_strobe * 
          /bpctrl(5).Q * d(7) 
        + /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * ao_from_pc_strobe * 
          bpctrl(5).Q * /d(7) 

    bpctrl(5).AP =
          GND

    bpctrl(5).AR =
          reset.CMB 

    bpctrl(5).C =
          clk 

    bpctrl(5).OE =
          bpctrl(0).Q 

    bpctrl(6).T =
          /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * ao_from_pc_strobe * 
          /bpctrl(6).Q * d(8) 
        + /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * ao_from_pc_strobe * 
          bpctrl(6).Q * /d(8) 

    bpctrl(6).AP =
          GND

    bpctrl(6).AR =
          reset.CMB 

    bpctrl(6).C =
          clk 

    bpctrl(6).OE =
          bpctrl(0).Q 

    bpctrl(7).T =
          /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * ao_from_pc_strobe * 
          /bpctrl(7).Q * d(9) 
        + /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * ao_from_pc_strobe * 
          bpctrl(7).Q * /d(9) 

    bpctrl(7).AP =
          GND

    bpctrl(7).AR =
          reset.CMB 

    bpctrl(7).C =
          clk 

    bpctrl(7).OE =
          bpctrl(0).Q 

    bpctrl(8).T =
          /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * ao_from_pc_strobe * 
          /bpctrl(8).Q * d(10) 
        + /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * ao_from_pc_strobe * 
          bpctrl(8).Q * /d(10) 

    bpctrl(8).AP =
          GND

    bpctrl(8).AR =
          reset.CMB 

    bpctrl(8).C =
          clk 

    bpctrl(8).OE =
          bpctrl(0).Q 

    bpctrl_h_dir =
          GND

    bpctrl_h_tristate =
          bpd_h_tristate.Q 

    bpctrl_l_dir =
          GND

    bpctrl_l_tristate =
          GND

    bpd(10).T =
          /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * ao_from_pc_strobe * 
          /bpd(10).Q * d(0) 
        + /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * ao_from_pc_strobe * 
          bpd(10).Q * /d(0) 

    bpd(10).AP =
          GND

    bpd(10).AR =
          reset.CMB 

    bpd(10).C =
          clk 

    bpd(10).OE =
          bpctrl(0).Q 

    bpd(11).T =
          /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * ao_from_pc_strobe * 
          /bpd(11).Q * d(1) 
        + /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * ao_from_pc_strobe * 
          bpd(11).Q * /d(1) 

    bpd(11).AP =
          GND

    bpd(11).AR =
          reset.CMB 

    bpd(11).C =
          clk 

    bpd(11).OE =
          bpctrl(0).Q 

    bpd(12).T =
          /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * ao_from_pc_strobe * 
          /bpd(12).Q * d(2) 
        + /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * ao_from_pc_strobe * 
          bpd(12).Q * /d(2) 

    bpd(12).AP =
          GND

    bpd(12).AR =
          reset.CMB 

    bpd(12).C =
          clk 

    bpd(12).OE =
          bpctrl(0).Q 

    bpd(13).T =
          /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * ao_from_pc_strobe * 
          /bpd(13).Q * d(3) 
        + /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * ao_from_pc_strobe * 
          bpd(13).Q * /d(3) 

    bpd(13).AP =
          GND

    bpd(13).AR =
          reset.CMB 

    bpd(13).C =
          clk 

    bpd(13).OE =
          bpctrl(0).Q 

    bpd(14).T =
          /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * ao_from_pc_strobe * 
          /bpd(14).Q * d(4) 
        + /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * ao_from_pc_strobe * 
          bpd(14).Q * /d(4) 

    bpd(14).AP =
          GND

    bpd(14).AR =
          reset.CMB 

    bpd(14).C =
          clk 

    bpd(14).OE =
          bpctrl(0).Q 

    bpd(15).T =
          /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * ao_from_pc_strobe * 
          /bpd(15).Q * d(5) 
        + /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * ao_from_pc_strobe * 
          bpd(15).Q * /d(5) 

    bpd(15).AP =
          GND

    bpd(15).AR =
          reset.CMB 

    bpd(15).C =
          clk 

    bpd(15).OE =
          bpctrl(0).Q 

    bpd_h_dir =
          /bpctrl(0).Q 

    /bpd_h_tristate.D =
          /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * loopback_state.Q * 
          sensor_to_bp_read_req.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /from_pc_req.Q * 
          sensor_to_bp_read_req.Q 
        + \bp_io:bp_access_stateSBV_0\.Q * /\bp_io:bp_access_stateSBV_1\.Q * 
          \bp_io:bp_access_stateSBV_2\.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_1\.Q 
        + \bp_io:bp_access_stateSBV_1\.Q * /\bp_io:bp_access_stateSBV_2\.Q 

    bpd_h_tristate.AP =
          GND

    bpd_h_tristate.AR =
          reset.CMB 

    bpd_h_tristate.C =
          clk 

    bpd_l_dir =
          /bpctrl(0).Q 

    bpd_l_tristate =
          bpd_h_tristate.Q 

    d(16).T =
          /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          /bpd(10).Q * d(16).Q * from_pc_req.Q * loopback_state.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          bpd(10).Q * /d(16).Q * from_pc_req.Q * loopback_state.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          /d(16).Q * /loopback_state.Q * sensor_data_0.Q * 
          sensor_to_ibus_req.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          d(16).Q * /loopback_state.Q * /sensor_data_0.Q * 
          sensor_to_ibus_req.Q 

    d(16).AP =
          GND

    d(16).AR =
          reset.CMB 

    d(16).C =
          clk 

    d(17).T =
          /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          /bpd(11).Q * d(17).Q * from_pc_req.Q * loopback_state.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          bpd(11).Q * /d(17).Q * from_pc_req.Q * loopback_state.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          /d(17).Q * /loopback_state.Q * sensor_data_1.Q * 
          sensor_to_ibus_req.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          d(17).Q * /loopback_state.Q * /sensor_data_1.Q * 
          sensor_to_ibus_req.Q 

    d(17).AP =
          GND

    d(17).AR =
          reset.CMB 

    d(17).C =
          clk 

    d(18).T =
          /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          /bpd(12).Q * d(18).Q * from_pc_req.Q * loopback_state.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          bpd(12).Q * /d(18).Q * from_pc_req.Q * loopback_state.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          /d(18).Q * /loopback_state.Q * sensor_data_2.Q * 
          sensor_to_ibus_req.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          d(18).Q * /loopback_state.Q * /sensor_data_2.Q * 
          sensor_to_ibus_req.Q 

    d(18).AP =
          GND

    d(18).AR =
          reset.CMB 

    d(18).C =
          clk 

    d(19).T =
          /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          /bpd(13).Q * d(19).Q * from_pc_req.Q * loopback_state.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          bpd(13).Q * /d(19).Q * from_pc_req.Q * loopback_state.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          /d(19).Q * /loopback_state.Q * sensor_data_3.Q * 
          sensor_to_ibus_req.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          d(19).Q * /loopback_state.Q * /sensor_data_3.Q * 
          sensor_to_ibus_req.Q 

    d(19).AP =
          GND

    d(19).AR =
          reset.CMB 

    d(19).C =
          clk 

    d(20).T =
          /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          /bpd(14).Q * d(20).Q * from_pc_req.Q * loopback_state.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          bpd(14).Q * /d(20).Q * from_pc_req.Q * loopback_state.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          /d(20).Q * /loopback_state.Q * sensor_data_4.Q * 
          sensor_to_ibus_req.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          d(20).Q * /loopback_state.Q * /sensor_data_4.Q * 
          sensor_to_ibus_req.Q 

    d(20).AP =
          GND

    d(20).AR =
          reset.CMB 

    d(20).C =
          clk 

    d(21).T =
          /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          /bpd(15).Q * d(21).Q * from_pc_req.Q * loopback_state.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          bpd(15).Q * /d(21).Q * from_pc_req.Q * loopback_state.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          /d(21).Q * /loopback_state.Q * sensor_data_5.Q * 
          sensor_to_ibus_req.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          d(21).Q * /loopback_state.Q * /sensor_data_5.Q * 
          sensor_to_ibus_req.Q 

    d(21).AP =
          GND

    d(21).AR =
          reset.CMB 

    d(21).C =
          clk 

    d(22).T =
          /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          /bpctrl(4).Q * d(22).Q * from_pc_req.Q * loopback_state.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          bpctrl(4).Q * /d(22).Q * from_pc_req.Q * loopback_state.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          /d(22).Q * /loopback_state.Q * sensor_data_6.Q * 
          sensor_to_ibus_req.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          d(22).Q * /loopback_state.Q * /sensor_data_6.Q * 
          sensor_to_ibus_req.Q 

    d(22).AP =
          GND

    d(22).AR =
          reset.CMB 

    d(22).C =
          clk 

    d(23).T =
          /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          /bpctrl(5).Q * d(23).Q * from_pc_req.Q * loopback_state.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          bpctrl(5).Q * /d(23).Q * from_pc_req.Q * loopback_state.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          /d(23).Q * /loopback_state.Q * sensor_data_7.Q * 
          sensor_to_ibus_req.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          d(23).Q * /loopback_state.Q * /sensor_data_7.Q * 
          sensor_to_ibus_req.Q 

    d(23).AP =
          GND

    d(23).AR =
          reset.CMB 

    d(23).C =
          clk 

    d(24).T =
          /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          /bpctrl(6).Q * d(24).Q * from_pc_req.Q * loopback_state.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          bpctrl(6).Q * /d(24).Q * from_pc_req.Q * loopback_state.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          /d(24).Q * /loopback_state.Q * sensor_data_8.Q * 
          sensor_to_ibus_req.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          d(24).Q * /loopback_state.Q * /sensor_data_8.Q * 
          sensor_to_ibus_req.Q 

    d(24).AP =
          GND

    d(24).AR =
          reset.CMB 

    d(24).C =
          clk 

    d(25).T =
          /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          /bpctrl(7).Q * d(25).Q * from_pc_req.Q * loopback_state.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          bpctrl(7).Q * /d(25).Q * from_pc_req.Q * loopback_state.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          /d(25).Q * /loopback_state.Q * sensor_data_9.Q * 
          sensor_to_ibus_req.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          d(25).Q * /loopback_state.Q * /sensor_data_9.Q * 
          sensor_to_ibus_req.Q 

    d(25).AP =
          GND

    d(25).AR =
          reset.CMB 

    d(25).C =
          clk 

    d(26).T =
          /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          /bpctrl(8).Q * d(26).Q * from_pc_req.Q * loopback_state.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          bpctrl(8).Q * /d(26).Q * from_pc_req.Q * loopback_state.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          /d(26).Q * /loopback_state.Q * sensor_data_10.Q * 
          sensor_to_ibus_req.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          d(26).Q * /loopback_state.Q * /sensor_data_10.Q * 
          sensor_to_ibus_req.Q 

    d(26).AP =
          GND

    d(26).AR =
          reset.CMB 

    d(26).C =
          clk 

    d(27).T =
          /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          /bpctrl(10).Q * d(27).Q * from_pc_req.Q * loopback_state.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          bpctrl(10).Q * /d(27).Q * from_pc_req.Q * loopback_state.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          /d(27).Q * /loopback_state.Q * sensor_data_11.Q * 
          sensor_to_ibus_req.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          d(27).Q * /loopback_state.Q * /sensor_data_11.Q * 
          sensor_to_ibus_req.Q 

    d(27).AP =
          GND

    d(27).AR =
          reset.CMB 

    d(27).C =
          clk 

    d(28).T =
          /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          /bpctrl(11).Q * d(28).Q * from_pc_req.Q * loopback_state.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          bpctrl(11).Q * /d(28).Q * from_pc_req.Q * loopback_state.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          /d(28).Q * /loopback_state.Q * sensor_data_12.Q * 
          sensor_to_ibus_req.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          d(28).Q * /loopback_state.Q * /sensor_data_12.Q * 
          sensor_to_ibus_req.Q 

    d(28).AP =
          GND

    d(28).AR =
          reset.CMB 

    d(28).C =
          clk 

    d(29).T =
          /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          /d(29).Q * data_from_pc_13.Q * from_pc_req.Q * loopback_state.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          d(29).Q * /data_from_pc_13.Q * from_pc_req.Q * loopback_state.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          /d(29).Q * /loopback_state.Q * sensor_data_13.Q * 
          sensor_to_ibus_req.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          d(29).Q * /loopback_state.Q * /sensor_data_13.Q * 
          sensor_to_ibus_req.Q 

    d(29).AP =
          GND

    d(29).AR =
          reset.CMB 

    d(29).C =
          clk 

    d(30).T =
          /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          /d(30).Q * data_from_pc_14.Q * from_pc_req.Q * loopback_state.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          d(30).Q * /data_from_pc_14.Q * from_pc_req.Q * loopback_state.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          /d(30).Q * /loopback_state.Q * sensor_data_14.Q * 
          sensor_to_ibus_req.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          d(30).Q * /loopback_state.Q * /sensor_data_14.Q * 
          sensor_to_ibus_req.Q 

    d(30).AP =
          GND

    d(30).AR =
          reset.CMB 

    d(30).C =
          clk 

    d(31).T =
          /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          /d(31).Q * data_from_pc_15.Q * from_pc_req.Q * loopback_state.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          d(31).Q * /data_from_pc_15.Q * from_pc_req.Q * loopback_state.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          /d(31).Q * /loopback_state.Q * sensor_data_15.Q * 
          sensor_to_ibus_req.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          d(31).Q * /loopback_state.Q * /sensor_data_15.Q * 
          sensor_to_ibus_req.Q 

    d(31).AP =
          GND

    d(31).AR =
          reset.CMB 

    d(31).C =
          clk 

    data_from_pc_13.T =
          /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * ao_from_pc_strobe * /d(13) * 
          data_from_pc_13.Q 
        + /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * ao_from_pc_strobe * d(13) * 
          /data_from_pc_13.Q 

    data_from_pc_13.AP =
          GND

    data_from_pc_13.AR =
          reset.CMB 

    data_from_pc_13.C =
          clk 

    data_from_pc_14.T =
          /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * ao_from_pc_strobe * /d(14) * 
          data_from_pc_14.Q 
        + /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * ao_from_pc_strobe * d(14) * 
          /data_from_pc_14.Q 

    data_from_pc_14.AP =
          GND

    data_from_pc_14.AR =
          reset.CMB 

    data_from_pc_14.C =
          clk 

    data_from_pc_15.T =
          /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * ao_from_pc_strobe * /d(15) * 
          data_from_pc_15.Q 
        + /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * ao_from_pc_strobe * d(15) * 
          /data_from_pc_15.Q 

    data_from_pc_15.AP =
          GND

    data_from_pc_15.AR =
          reset.CMB 

    data_from_pc_15.C =
          clk 

    from_pc_req.D =
          \ibus_reader:il_read_stateSBV_0\.Q * 
          \ibus_reader:il_read_stateSBV_2\.Q * loopback_state.Q * 
          /to_pc_ack.Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          \ibus_reader:il_read_stateSBV_2\.Q * /loopback_state.Q * 
          /write_to_bp_ack.Q 
        + \ibus_reader:il_read_stateSBV_1\.Q * 
          \ibus_reader:il_read_stateSBV_2\.Q * 
          /\ibus_reader:this_is_a_ctrl_transaction\.Q 

    from_pc_req.AP =
          GND

    from_pc_req.AR =
          reset.CMB 

    from_pc_req.C =
          clk 

    /il_tristate.D =
          /il_tristate.Q * tristate_stateSBV_0.Q 
        + /this_chip_selected.Q * tristate_stateSBV_0.Q 
        + this_chip_selected.Q * /tristate_stateSBV_0.Q 

    il_tristate.AP =
          GND

    il_tristate.AR =
          reset.CMB 

    il_tristate.C =
          clk 

    /led1.D =
          /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * from_pc_req.Q * 
          /loopback_state.Q 
        + \bp_io:bp_access_stateSBV_0\.Q * /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_1\.Q 

    led1.AP =
          GND

    led1.AR =
          reset.CMB 

    led1.C =
          clk 

    led2 =
          fast 

    led3 =
          slow 

    loopback_state.T =
          /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * loopback_state.Q 

    loopback_state.AP =
          GND

    loopback_state.AR =
          reset.CMB 

    loopback_state.C =
          clk 

    reset =
          fast * /slow 

    sensor_address_0.T =
          /\sp_read:counter_address_0\.Q * /\sp_read:counter_address_3\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q * sensor_address_0.Q 
        + /\sp_read:counter_address_0\.Q * /\sp_read:counter_address_4\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q * sensor_address_0.Q 
        + \sp_read:counter_address_0\.Q * /\sp_read:counter_address_3\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q * /sensor_address_0.Q 
        + \sp_read:counter_address_0\.Q * /\sp_read:counter_address_4\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q * /sensor_address_0.Q 

    sensor_address_0.AP =
          GND

    sensor_address_0.AR =
          reset.CMB 

    sensor_address_0.C =
          clk 

    sensor_address_1.T =
          /\sp_read:counter_address_1\.Q * /\sp_read:counter_address_3\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q * sensor_address_1.Q 
        + /\sp_read:counter_address_1\.Q * /\sp_read:counter_address_4\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q * sensor_address_1.Q 
        + \sp_read:counter_address_1\.Q * /\sp_read:counter_address_3\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q * /sensor_address_1.Q 
        + \sp_read:counter_address_1\.Q * /\sp_read:counter_address_4\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q * /sensor_address_1.Q 

    sensor_address_1.AP =
          GND

    sensor_address_1.AR =
          reset.CMB 

    sensor_address_1.C =
          clk 

    sensor_address_2.T =
          /\sp_read:counter_address_2\.Q * /\sp_read:counter_address_3\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q * sensor_address_2.Q 
        + /\sp_read:counter_address_2\.Q * /\sp_read:counter_address_4\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q * sensor_address_2.Q 
        + \sp_read:counter_address_2\.Q * /\sp_read:counter_address_3\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q * /sensor_address_2.Q 
        + \sp_read:counter_address_2\.Q * /\sp_read:counter_address_4\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q * /sensor_address_2.Q 

    sensor_address_2.AP =
          GND

    sensor_address_2.AR =
          reset.CMB 

    sensor_address_2.C =
          clk 

    sensor_address_3.T =
          \sp_read:counter_address_3\.Q * /\sp_read:counter_address_4\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q * /sensor_address_3.Q 
        + /\sp_read:counter_address_3\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q * sensor_address_3.Q 

    sensor_address_3.AP =
          GND

    sensor_address_3.AR =
          reset.CMB 

    sensor_address_3.C =
          clk 

    sensor_address_4.T =
          /\sp_read:counter_address_3\.Q * \sp_read:counter_address_4\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q * /sensor_address_4.Q 
        + /\sp_read:counter_address_4\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q * sensor_address_4.Q 

    sensor_address_4.AP =
          GND

    sensor_address_4.AR =
          reset.CMB 

    sensor_address_4.C =
          clk 

    sensor_address_5.T =
          /\sp_read:counter_address_3\.Q * /\sp_read:counter_address_5\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q * sensor_address_5.Q 
        + /\sp_read:counter_address_4\.Q * /\sp_read:counter_address_5\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q * sensor_address_5.Q 
        + /\sp_read:counter_address_3\.Q * \sp_read:counter_address_5\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q * /sensor_address_5.Q 
        + /\sp_read:counter_address_4\.Q * \sp_read:counter_address_5\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q * /sensor_address_5.Q 

    sensor_address_5.AP =
          GND

    sensor_address_5.AR =
          reset.CMB 

    sensor_address_5.C =
          clk 

    sensor_address_6.T =
          /\sp_read:counter_address_3\.Q * /\sp_read:counter_address_6\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q * sensor_address_6.Q 
        + /\sp_read:counter_address_4\.Q * /\sp_read:counter_address_6\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q * sensor_address_6.Q 
        + /\sp_read:counter_address_3\.Q * \sp_read:counter_address_6\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q * /sensor_address_6.Q 
        + /\sp_read:counter_address_4\.Q * \sp_read:counter_address_6\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q * /sensor_address_6.Q 

    sensor_address_6.AP =
          GND

    sensor_address_6.AR =
          reset.CMB 

    sensor_address_6.C =
          clk 

    sensor_address_7.T =
          /\sp_read:counter_address_3\.Q * /\sp_read:counter_address_7\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q * sensor_address_7.Q 
        + /\sp_read:counter_address_4\.Q * /\sp_read:counter_address_7\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q * sensor_address_7.Q 
        + /\sp_read:counter_address_3\.Q * \sp_read:counter_address_7\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q * /sensor_address_7.Q 
        + /\sp_read:counter_address_4\.Q * \sp_read:counter_address_7\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q * /sensor_address_7.Q 

    sensor_address_7.AP =
          GND

    sensor_address_7.AR =
          reset.CMB 

    sensor_address_7.C =
          clk 

    sensor_data_0.T =
          \bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /\bp_io:timeout_0\.Q * 
          \bp_io:timeout_1\.Q * /\bp_io:timeout_2\.Q * /bpd(0) * 
          sensor_data_0.Q 
        + \bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /\bp_io:timeout_0\.Q * 
          \bp_io:timeout_1\.Q * /\bp_io:timeout_2\.Q * bpd(0) * 
          /sensor_data_0.Q 

    sensor_data_0.AP =
          GND

    sensor_data_0.AR =
          reset.CMB 

    sensor_data_0.C =
          clk 

    sensor_data_1.T =
          \bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /\bp_io:timeout_0\.Q * 
          \bp_io:timeout_1\.Q * /\bp_io:timeout_2\.Q * /bpd(1) * 
          sensor_data_1.Q 
        + \bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /\bp_io:timeout_0\.Q * 
          \bp_io:timeout_1\.Q * /\bp_io:timeout_2\.Q * bpd(1) * 
          /sensor_data_1.Q 

    sensor_data_1.AP =
          GND

    sensor_data_1.AR =
          reset.CMB 

    sensor_data_1.C =
          clk 

    sensor_data_10.T =
          \bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /\bp_io:timeout_0\.Q * 
          \bp_io:timeout_1\.Q * /\bp_io:timeout_2\.Q * /bpd(10) * 
          sensor_data_10.Q 
        + \bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /\bp_io:timeout_0\.Q * 
          \bp_io:timeout_1\.Q * /\bp_io:timeout_2\.Q * bpd(10) * 
          /sensor_data_10.Q 

    sensor_data_10.AP =
          GND

    sensor_data_10.AR =
          reset.CMB 

    sensor_data_10.C =
          clk 

    sensor_data_11.T =
          \bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /\bp_io:timeout_0\.Q * 
          \bp_io:timeout_1\.Q * /\bp_io:timeout_2\.Q * /bpd(11) * 
          sensor_data_11.Q 
        + \bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /\bp_io:timeout_0\.Q * 
          \bp_io:timeout_1\.Q * /\bp_io:timeout_2\.Q * bpd(11) * 
          /sensor_data_11.Q 

    sensor_data_11.AP =
          GND

    sensor_data_11.AR =
          reset.CMB 

    sensor_data_11.C =
          clk 

    sensor_data_12.T =
          \bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /\bp_io:timeout_0\.Q * 
          \bp_io:timeout_1\.Q * /\bp_io:timeout_2\.Q * /bpd(12) * 
          sensor_data_12.Q 
        + \bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /\bp_io:timeout_0\.Q * 
          \bp_io:timeout_1\.Q * /\bp_io:timeout_2\.Q * bpd(12) * 
          /sensor_data_12.Q 

    sensor_data_12.AP =
          GND

    sensor_data_12.AR =
          reset.CMB 

    sensor_data_12.C =
          clk 

    sensor_data_13.T =
          \bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /\bp_io:timeout_0\.Q * 
          \bp_io:timeout_1\.Q * /\bp_io:timeout_2\.Q * /bpd(13) * 
          sensor_data_13.Q 
        + \bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /\bp_io:timeout_0\.Q * 
          \bp_io:timeout_1\.Q * /\bp_io:timeout_2\.Q * bpd(13) * 
          /sensor_data_13.Q 

    sensor_data_13.AP =
          GND

    sensor_data_13.AR =
          reset.CMB 

    sensor_data_13.C =
          clk 

    sensor_data_14.T =
          \bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /\bp_io:timeout_0\.Q * 
          \bp_io:timeout_1\.Q * /\bp_io:timeout_2\.Q * /bpd(14) * 
          sensor_data_14.Q 
        + \bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /\bp_io:timeout_0\.Q * 
          \bp_io:timeout_1\.Q * /\bp_io:timeout_2\.Q * bpd(14) * 
          /sensor_data_14.Q 

    sensor_data_14.AP =
          GND

    sensor_data_14.AR =
          reset.CMB 

    sensor_data_14.C =
          clk 

    sensor_data_15.T =
          \sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * sensor_data_15.Q * 
          sensor_to_bp_read_ack.Q * sinphase_zeros 
        + \sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /sensor_data_15.Q * 
          sensor_to_bp_read_ack.Q * /sinphase_zeros 

    sensor_data_15.AP =
          GND

    sensor_data_15.AR =
          reset.CMB 

    sensor_data_15.C =
          clk 

    sensor_data_2.T =
          \bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /\bp_io:timeout_0\.Q * 
          \bp_io:timeout_1\.Q * /\bp_io:timeout_2\.Q * /bpd(2) * 
          sensor_data_2.Q 
        + \bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /\bp_io:timeout_0\.Q * 
          \bp_io:timeout_1\.Q * /\bp_io:timeout_2\.Q * bpd(2) * 
          /sensor_data_2.Q 

    sensor_data_2.AP =
          GND

    sensor_data_2.AR =
          reset.CMB 

    sensor_data_2.C =
          clk 

    sensor_data_3.T =
          \bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /\bp_io:timeout_0\.Q * 
          \bp_io:timeout_1\.Q * /\bp_io:timeout_2\.Q * /bpd(3) * 
          sensor_data_3.Q 
        + \bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /\bp_io:timeout_0\.Q * 
          \bp_io:timeout_1\.Q * /\bp_io:timeout_2\.Q * bpd(3) * 
          /sensor_data_3.Q 

    sensor_data_3.AP =
          GND

    sensor_data_3.AR =
          reset.CMB 

    sensor_data_3.C =
          clk 

    sensor_data_4.T =
          \bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /\bp_io:timeout_0\.Q * 
          \bp_io:timeout_1\.Q * /\bp_io:timeout_2\.Q * /bpd(4) * 
          sensor_data_4.Q 
        + \bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /\bp_io:timeout_0\.Q * 
          \bp_io:timeout_1\.Q * /\bp_io:timeout_2\.Q * bpd(4) * 
          /sensor_data_4.Q 

    sensor_data_4.AP =
          GND

    sensor_data_4.AR =
          reset.CMB 

    sensor_data_4.C =
          clk 

    sensor_data_5.T =
          \bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /\bp_io:timeout_0\.Q * 
          \bp_io:timeout_1\.Q * /\bp_io:timeout_2\.Q * /bpd(5) * 
          sensor_data_5.Q 
        + \bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /\bp_io:timeout_0\.Q * 
          \bp_io:timeout_1\.Q * /\bp_io:timeout_2\.Q * bpd(5) * 
          /sensor_data_5.Q 

    sensor_data_5.AP =
          GND

    sensor_data_5.AR =
          reset.CMB 

    sensor_data_5.C =
          clk 

    sensor_data_6.T =
          \bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /\bp_io:timeout_0\.Q * 
          \bp_io:timeout_1\.Q * /\bp_io:timeout_2\.Q * /bpd(6) * 
          sensor_data_6.Q 
        + \bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /\bp_io:timeout_0\.Q * 
          \bp_io:timeout_1\.Q * /\bp_io:timeout_2\.Q * bpd(6) * 
          /sensor_data_6.Q 

    sensor_data_6.AP =
          GND

    sensor_data_6.AR =
          reset.CMB 

    sensor_data_6.C =
          clk 

    sensor_data_7.T =
          \bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /\bp_io:timeout_0\.Q * 
          \bp_io:timeout_1\.Q * /\bp_io:timeout_2\.Q * /bpd(7) * 
          sensor_data_7.Q 
        + \bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /\bp_io:timeout_0\.Q * 
          \bp_io:timeout_1\.Q * /\bp_io:timeout_2\.Q * bpd(7) * 
          /sensor_data_7.Q 

    sensor_data_7.AP =
          GND

    sensor_data_7.AR =
          reset.CMB 

    sensor_data_7.C =
          clk 

    sensor_data_8.T =
          \bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /\bp_io:timeout_0\.Q * 
          \bp_io:timeout_1\.Q * /\bp_io:timeout_2\.Q * /bpd(8) * 
          sensor_data_8.Q 
        + \bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /\bp_io:timeout_0\.Q * 
          \bp_io:timeout_1\.Q * /\bp_io:timeout_2\.Q * bpd(8) * 
          /sensor_data_8.Q 

    sensor_data_8.AP =
          GND

    sensor_data_8.AR =
          reset.CMB 

    sensor_data_8.C =
          clk 

    sensor_data_9.T =
          \bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /\bp_io:timeout_0\.Q * 
          \bp_io:timeout_1\.Q * /\bp_io:timeout_2\.Q * /bpd(9) * 
          sensor_data_9.Q 
        + \bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /\bp_io:timeout_0\.Q * 
          \bp_io:timeout_1\.Q * /\bp_io:timeout_2\.Q * bpd(9) * 
          /sensor_data_9.Q 

    sensor_data_9.AP =
          GND

    sensor_data_9.AR =
          reset.CMB 

    sensor_data_9.C =
          clk 

    sensor_to_bp_read_ack.D =
          \bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:timeout_0\.Q * \bp_io:timeout_1\.Q * 
          /\bp_io:timeout_2\.Q 
        + \bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_1\.Q * 
          \bp_io:bp_access_stateSBV_2\.Q 

    sensor_to_bp_read_ack.AP =
          GND

    sensor_to_bp_read_ack.AR =
          reset.CMB 

    sensor_to_bp_read_ack.C =
          clk 

    sensor_to_bp_read_req.D =
          \sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /sensor_to_bp_read_ack.Q 

    sensor_to_bp_read_req.AP =
          GND

    sensor_to_bp_read_req.AR =
          reset.CMB 

    sensor_to_bp_read_req.C =
          clk 

    sensor_to_ibus_req.D =
          \sp_read:counter_read_stateSBV_1\.Q * 
          \sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * loopback_state.Q 
        + \sp_read:counter_read_stateSBV_1\.Q * 
          \sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /to_pc_ack.Q 
        + \sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q 

    sensor_to_ibus_req.AP =
          GND

    sensor_to_ibus_req.AR =
          reset.CMB 

    sensor_to_ibus_req.C =
          clk 

    this_chip_selected.D =
          /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          \ibus_reader:il_read_stateSBV_2\.Q * /bpctrl(10).Q * 
          bpctrl(11).Q * /bpctrl(7).Q * /bpctrl(8).Q * data_from_pc_15.Q 
        + \ibus_reader:il_read_stateSBV_1\.Q * this_chip_selected.Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * this_chip_selected.Q 
        + /\ibus_reader:il_read_stateSBV_2\.Q * this_chip_selected.Q 
        + /data_from_pc_15.Q * this_chip_selected.Q 

    this_chip_selected.AP =
          GND

    this_chip_selected.AR =
          reset.CMB 

    this_chip_selected.C =
          clk 

    to_pc_ack.D =
          /\ibus_writer:iu_writeSBV_0\.Q * from_pc_req.Q * 
          loopback_state.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /loopback_state.Q * 
          sensor_to_ibus_req.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * \ibus_writer:iu_writeSBV_1\.Q 

    to_pc_ack.AP =
          GND

    to_pc_ack.AR =
          reset.CMB 

    to_pc_ack.C =
          clk 

    tristate_stateSBV_0.D =
          this_chip_selected.Q 

    tristate_stateSBV_0.AP =
          GND

    tristate_stateSBV_0.AR =
          reset.CMB 

    tristate_stateSBV_0.C =
          clk 

    write_to_bp_ack.D =
          /\bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_1\.Q * 
          \bp_io:bp_access_stateSBV_2\.Q * /\bp_io:timeout_0\.Q * 
          \bp_io:timeout_1\.Q * /\bp_io:timeout_2\.Q 
        + \bp_io:bp_access_stateSBV_0\.Q * /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q 

    write_to_bp_ack.AP =
          GND

    write_to_bp_ack.AR =
          reset.CMB 

    write_to_bp_ack.C =
          clk 


Completed Successfully  
----------------------------------------------------------------------------
PLD Compiler Software:        C37KFIT.EXE    22/DEC/2000  [v4.02 ] 6.2 IR 27

DESIGN RULE CHECK          (15:40:39)

Messages:
                 None.


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully  
----------------------------------------------------------------------------
PLD Compiler Software:        C37KFIT.EXE    22/DEC/2000  [v4.02 ] 6.2 IR 27

PARTITION LOGIC            (15:40:40)

Messages:
  Information: Initializing Logic Block structures.
  Information: Forming input seeds.
  Information: Checking for duplicate NODE logic.
  Information: Forming input seeds.
  Information: Assigning fixed logic to Logic Blocks.
  Information: Processing banked global preset, reset and output enable.
  Information: Separating output logic set to GND/VCC.
  Information: Validating Logic Block's with pre-placed signals.
  Information: Separating input register logic.
  Information: Assigning initializing equations to empty Logic Blocks.
  Information: Separating output combinatorial logic.
  Information: Separating disjoint output logic.
  Information: Separating output node logic.
  Information: Assigning floating outputs to Logic Blocks.
  Information: Compacting Logic Block interconnect.
  ..................................................+....................
  .......................................................................
  .......................................................................
  ...............................
  Information: Separating output logic with >= 16 pt's.
  Information: Assigning floating outputs to Logic Blocks.
  Information: Minimizing interconnect between Logic Blocks.
  ...+..+..+.+.+.........+....+...............+...............
Start=15:40:40  End=15:40:40
  Information: Separating disjoint output logic.
  Information: Separating output node logic.
  Information: Assigning floating outputs to Logic Blocks.
  Information: Assigning floating outputs to Logic Blocks.
  Information: Minimizing interconnect between Logic Blocks.
  ...+.....++..+.............+..+.............+...............+.........
  ......
Start=15:40:40  End=15:40:41


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully  
----------------------------------------------------------------------------
PLD Compiler Software:        C37KFIT.EXE    22/DEC/2000  [v4.02 ] 6.2 IR 27

DESIGN SIGNAL PLACEMENT    (15:40:41)

Messages:
  Information: Fitting signals to Logic Block A.
  Information: Fitting signals to Logic Block B.
  Information: Assigning Signals to Macrocells.
  Information: Improving Macrocell Assignment
  ................
  Information: Assigning Product Terms to Allocator
  Information: Fitting signals to Logic Block C.
  Information: Assigning Signals to Macrocells.
  Information: Improving Macrocell Assignment
  .+.+...............+.+..............................
  Information: Assigning Product Terms to Allocator
  Information: Assigning Signals to Macrocells.
  Information: Improving Macrocell Assignment
  ................
  Information: Assigning Product Terms to Allocator
  Information: Fitting signals to Logic Block D.
  Information: Assigning Signals to Macrocells.
  Information: Improving Macrocell Assignment
  ................
  Information: Assigning Product Terms to Allocator
  Information: Fitting signals to Logic Block E.
  Information: Assigning Signals to Macrocells.
  Information: Improving Macrocell Assignment
  ................
  Information: Assigning Product Terms to Allocator
  Information: Fitting signals to Logic Block F.
  Information: Assigning Signals to Macrocells.
  Information: Improving Macrocell Assignment
  ................
  Information: Assigning Product Terms to Allocator
  Information: Fitting signals to Logic Block G.
  Information: Assigning Signals to Macrocells.
  Information: Improving Macrocell Assignment
  ..+................+..............................
  Information: Assigning Product Terms to Allocator
  Information: Fitting signals to Logic Block H.
  Information: Assigning Signals to Macrocells.
  Information: Improving Macrocell Assignment
  ................
  Information: Assigning Product Terms to Allocator
  Information: Combining '\sp_read:counter_read_stateSBV_1\' definition with input pin 'hva_chassis_en_l'.
  Information: Fitting signals to Logic Block I.
  Information: Assigning Signals to Macrocells.
  Information: Improving Macrocell Assignment
  ..+................+.+.............................
  Information: Assigning Product Terms to Allocator
  Information: Assigning Signals to Macrocells.
  Information: Improving Macrocell Assignment
  ................
  Information: Assigning Product Terms to Allocator
  Information: Fitting signals to Logic Block J.
  Information: Assigning Signals to Macrocells.
  Information: Improving Macrocell Assignment
  .+.+..+.............+...............................
  Information: Assigning Product Terms to Allocator
  Information: Assigning Signals to Macrocells.
  Information: Improving Macrocell Assignment
  .+..+................+.............................
  Information: Assigning Product Terms to Allocator
  Information: Assigning Signals to Macrocells.
  Information: Improving Macrocell Assignment
  ...+................+.............................
  Information: Assigning Product Terms to Allocator
  Information: Assigning Signals to Macrocells.
  Information: Improving Macrocell Assignment
  ................
  Information: Assigning Product Terms to Allocator
  Information: Fitting signals to Logic Block K.
  Information: Assigning Signals to Macrocells.
  Information: Improving Macrocell Assignment
  ................
  Information: Assigning Product Terms to Allocator
  Information: Fitting signals to Logic Block L.
  Information: Assigning Signals to Macrocells.
  Information: Improving Macrocell Assignment
  ................
  Information: Assigning Product Terms to Allocator
  Information: Combining 'bp_end_address_2' definition with input pin 'ao_from_pc_strobe'.
  Information: Combining 'bp_end_address_7' definition with input pin 'ao_to_pc_ack'.
  Information: Combining 'data_from_pc_13' definition with input pin 'd(0)'.
  Information: Fitting signals to Logic Block M.
  Information: Assigning Signals to Macrocells.
  Information: Improving Macrocell Assignment
  ................
  Information: Assigning Product Terms to Allocator
  Information: Combining 'sensor_address_1' definition with input pin 'd(1)'.
  Information: Combining '\ibus_reader:timeout_1\' definition with input pin 'd(5)'.
  Information: Combining '\sp_read:counter_address_2\' definition with input pin 'd(3)'.
  Information: Combining '\sp_read:counter_address_3\' definition with input pin 'd(6)'.
  Information: Combining '\sp_read:counter_address_6\' definition with input pin 'd(7)'.
  Information: Combining '\sp_read:reset_count_1\' definition with input pin 'd(2)'.
  Information: Combining '\sp_read:reset_count_0\' definition with input pin 'd(4)'.
  Information: Fitting signals to Logic Block N.
  Information: Assigning Signals to Macrocells.
  Information: Improving Macrocell Assignment
  ................
  Information: Assigning Product Terms to Allocator
  Information: Combining 'sensor_data_1' definition with input pin 'd(12)'.
  Information: Combining 'sensor_data_13' definition with input pin 'd(11)'.
  Information: Combining 'sensor_data_14' definition with input pin 'd(13)'.
  Information: Combining 'sensor_data_4' definition with input pin 'd(14)'.
  Information: Combining 'sensor_data_5' definition with input pin 'd(10)'.
  Information: Combining 'write_to_bp_ack' definition with input pin 'd(9)'.
  Information: Fitting signals to Logic Block O.
  Information: Assigning Signals to Macrocells.
  Information: Improving Macrocell Assignment
  ..+..............................
  Information: Assigning Product Terms to Allocator
  Information: Assigning Signals to Macrocells.
  Information: Improving Macrocell Assignment
  ................
  Information: Assigning Product Terms to Allocator
  Information: Fitting signals to Logic Block P.
  Information: Assigning Signals to Macrocells.
  Information: Improving Macrocell Assignment
  ................
  Information: Assigning Product Terms to Allocator
  Information: Routing signals to Logic Blocks.


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully  
----------------------------------------------------------------------------
PLD Compiler Software:        C37KFIT.EXE    22/DEC/2000  [v4.02 ] 6.2 IR 27

LOGIC BLOCK A PLACEMENT   (15:40:41)

Messages:


________________________________________________________________________________
          1111111111222222222233333333334444444444555555555566666666667777777777
01234567890123456789012345678901234567890123456789012345678901234567890123456789
________________________________________________________________________________
| 0 |[i/p]
++++++++++++++++................................................................
| 1 |UNUSED
......++++++++++++++++..........................................................
| 2 |[i/p]
..........++++++++++++++++......................................................
| 3 |UNUSED
..............++++++++++++++++..................................................
| 4 |[i/p]
..................++++++++++++++++..............................................
| 5 |UNUSED
......................++++++++++++++++..........................................
| 6 |[i/p]
..........................++++++++++++++++......................................
| 7 |UNUSED
..............................++++++++++++++++..................................
| 8 |[i/p]
..................................++++++++++++++++..............................
| 9 |UNUSED
......................................++++++++++++++++..........................
|10 |[i/p]
..........................................++++++++++++++++......................
|11 |UNUSED
..............................................++++++++++++++++..................
|12 |[i/p]
..................................................++++++++++++++++..............
|13 |UNUSED
......................................................++++++++++++++++..........
|14 |[i/p]
..........................................................++++++++++++++++......
|15 |UNUSED
................................................................++++++++++++++++
________________________________________________________________________________

Total count of outputs placed        =  0 
Total count of unique Product Terms  =  0 
Total Product Terms to be assigned   =  0 
Max Product Terms used / available   =   0 /  80   = 0.0  %


Control Signals for Logic Block A
---------------------------------
CLK pin19: <not used>
CLK pin22: <not used>
CLK pin99: <not used>
CLK pin102: <not used>
CLK PT      : AH : <not used>
PRESET      : AH : <not used>
RESET       : AH : <not used>
OE 0        : AH : <not used>
OE 1        : AH : <not used>
OE 2        : AH : <not used>
OE 3        : AH : <not used>



                              Logic Block A
                 ____________________________________________
                 |   |> not used:262                    |   |                 
                 |   |> not used:263                    |   |                 
                 |   |> not used:264                    |   |                 
                 |   |> not used:265                    |   |                 
                 |   |> not used:266                    |143|= bpd(0)         
                 |   |> not used:267                    |   |                 
                 |   |> not used:268      not used:887 >|   |                 
                 |   |> not used:269                    |   |                 
                 |   |> not used:270                    |144|= bpd(1)         
                 |   |> not used:271                    |   |                 
                 |   |> not used:272      not used:889 >|   |                 
                 |   |> not used:273                    |   |                 
                 |   |> not used:274                    |145|= bpd(2)         
                 |   |> not used:275                    |   |                 
                 |   |> not used:276      not used:891 >|   |                 
                 |   |> not used:277                    |   |                 
                 |   |> not used:278                    |146|= bpd(3)         
                 |   |> not used:279                    |   |                 
                 |   |> not used:280      not used:893 >|   |                 
                 |   |> not used:281                    |   |                 
                 |   |> not used:282                    |147|= bpd(4)         
                 |   |> not used:283                    |   |                 
                 |   |> not used:284      not used:895 >|   |                 
                 |   |> not used:285                    |   |                 
                 |   |> not used:286                    |148|= bpd(5)         
                 |   |> not used:287                    |   |                 
                 |   |> not used:288      not used:897 >|   |                 
                 |   |> not used:289                    |   |                 
                 |   |> not used:290                    |149|= bpd(6)         
                 |   |> not used:291                    |   |                 
                 |   |> not used:292      not used:899 >|   |                 
                 |   |> not used:293                    |   |                 
                 |   |> not used:294                    |150|= bpd(7)         
                 |   |> not used:295                    |   |                 
                 |   |> not used:296      not used:901 >|   |                 
                 |   |> not used:297                    |   |                 
                 |   |> not used:298                    |   |                 
                 |   |> not used:299                    |   |                 
                 |   |> not used:300                    |   |                 
                 ____________________________________________


  Information: Macrocell Utilization.

                     Description        Used     Max
                 ______________________________________
                 | I/O Macrocells     |    8  |    8  |
                 | Buried Macrocells  |    0  |    8  |
                 | PIM Input Connects |    0  |   36  |
                 ______________________________________
                                           8  /   52   = 15  %


----------------------------------------------------------------------------
PLD Compiler Software:        C37KFIT.EXE    22/DEC/2000  [v4.02 ] 6.2 IR 27

LOGIC BLOCK B PLACEMENT   (15:40:41)

Messages:


________________________________________________________________________________
          1111111111222222222233333333334444444444555555555566666666667777777777
01234567890123456789012345678901234567890123456789012345678901234567890123456789
________________________________________________________________________________
| 0 |[i/p]
++++++++++++++++................................................................
| 1 |UNUSED
......++++++++++++++++..........................................................
| 2 |[i/p]
..........++++++++++++++++......................................................
| 3 |UNUSED
..............++++++++++++++++..................................................
| 4>|bpd(10)
..................XX++++++++++++++..............................................
| 5 |UNUSED
......................++++++++++++++++..........................................
| 6>|bpd(11)
..........................XX++++++++++++++......................................
| 7 |UNUSED
..............................++++++++++++++++..................................
| 8>|bpd(12)
..................................XX++++++++++++++..............................
| 9 |UNUSED
......................................++++++++++++++++..........................
|10>|bpd(13)
..........................................XX++++++++++++++......................
|11 |UNUSED
..............................................++++++++++++++++..................
|12>|bpd(14)
..................................................XX++++++++++++++..............
|13 |UNUSED
......................................................++++++++++++++++..........
|14>|bpd(15)
..........................................................XX++++++++++++++......
|15 |UNUSED
................................................................++++++++++++++++
________________________________________________________________________________

Total count of outputs placed        =  6 
Total count of unique Product Terms  =  12 
Total Product Terms to be assigned   =  12 
Max Product Terms used / available   =  12 /  80   = 15.1  %


Control Signals for Logic Block B
---------------------------------
CLK pin19: <not used>
CLK pin22: <not used>
CLK pin99: clk
CLK pin102: <not used>
CLK PT      : AH : <not used>
PRESET      : AH : GND
RESET       : AH : reset.CMB 
OE 0        : AH : bpctrl(0).Q 
OE 1        : AH : bpctrl(0).Q 
OE 2        : AH : bpctrl(0).Q 
OE 3        : AH : bpctrl(0).Q 



                              Logic Block B
                 ____________________________________________
                 |   |= >bpd(14).Q                      |   |                 
                 |   |= >bpd(10).Q                      |   |                 
                 |   |= >ao_from_pc_..                  |   |                 
                 |   |= >reset.CMB                      |   |                 
                 |   |= >bpd(11).Q                      |152|= bpd(8)         
                 |   |> not used:306                    |   |                 
                 |   |> not used:307      not used:903 >|   |                 
                 |   |= >bpd(12).Q                      |   |                 
                 |   |> not used:309                    |153|= bpd(9)         
                 |   |> not used:310                    |   |                 
                 |   |= >bpd(13).Q        not used:905 >|   |                 
                 |   |= >bpctrl(0).Q                    |   |                 
                 |   |= >d(0)                           |154|= bpd(10)        
                 |   |= >d(4)                           |   |                 
                 |   |> not used:315      not used:907 >|   |                 
                 |   |= >\ibus_reade..                  |   |                 
                 |   |= >d(1)                           |155|= bpd(11)        
                 |   |> not used:318                    |   |                 
                 |   |= >\ibus_reade..    not used:909 >|   |                 
                 |   |> not used:320                    |   |                 
                 |   |= >d(2)                           |156|= bpd(12)        
                 |   |> not used:322                    |   |                 
                 |   |> not used:323      not used:911 >|   |                 
                 |   |> not used:324                    |   |                 
                 |   |= >d(3)                           |157|= bpd(13)        
                 |   |> not used:326                    |   |                 
                 |   |> not used:327      not used:913 >|   |                 
                 |   |> not used:328                    |   |                 
                 |   |= >d(5)                           |158|= bpd(14)        
                 |   |= >\ibus_reade..                  |   |                 
                 |   |> not used:331      not used:915 >|   |                 
                 |   |> not used:332                    |   |                 
                 |   |> not used:333                    |159|= bpd(15)        
                 |   |> not used:334                    |   |                 
                 |   |> not used:335      not used:917 >|   |                 
                 |   |= >bpd(15).Q                      |   |                 
                 |   |> not used:337                    |   |                 
                 |   |> not used:338                    |   |                 
                 |   |> not used:339                    |   |                 
                 ____________________________________________


  Information: Macrocell Utilization.

                     Description        Used     Max
                 ______________________________________
                 | I/O Macrocells     |    8  |    8  |
                 | Buried Macrocells  |    0  |    8  |
                 | PIM Input Connects |   18  |   36  |
                 ______________________________________
                                          26  /   52   = 50  %


----------------------------------------------------------------------------
PLD Compiler Software:        C37KFIT.EXE    22/DEC/2000  [v4.02 ] 6.2 IR 27

LOGIC BLOCK C PLACEMENT   (15:40:41)

Messages:


________________________________________________________________________________
          1111111111222222222233333333334444444444555555555566666666667777777777
01234567890123456789012345678901234567890123456789012345678901234567890123456789
________________________________________________________________________________
| 0 |(S_13)
XXXXXXXXXXXXXXXX................................................................
| 1 |UNUSED
......++++++++++++++++..........................................................
| 2>|bpctrl_h_tristate
..........++++++++X+++++++......................................................
| 3 |(S_8)
..............++XX+XXXXXXXX+XX..................................................
| 4>|bpd_l_tristate
..................X+++++++++++++++..............................................
| 5 |(S_14)
......................+++++X++XXXXXXXX..........................................
| 6>|bpctrl_l_dir
..........................++++++++++++X+++......................................
| 7 |UNUSED
..............................++++++++++++++++..................................
| 8 |(S_10)
..................................+++++XXXXXXXXXXX..............................
| 9 |UNUSED
......................................++++++++++++++++..........................
|10>|bpctrl_l_tristate
..........................................++++++++X+++++++......................
|11 |(S_12)
..............................................+++++XXXXXXX+XXX..................
|12>|bpctrl_h_dir
..................................................X+++++++++++++++..............
|13 |UNUSED
......................................................++++++++++++++++..........
|14>|bpd_l_dir
..........................................................X+++++++++++++++......
|15 |(S_11)
................................................................XXXXXXXXXXXXXXXX
________________________________________________________________________________

Total count of outputs placed        =  12 
Total count of unique Product Terms  =  77 
Total Product Terms to be assigned   =  80 
Max Product Terms used / available   =  78 /  80   = 97.51 %


Control Signals for Logic Block C
---------------------------------
CLK pin19: <not used>
CLK pin22: <not used>
CLK pin99: <not used>
CLK pin102: <not used>
CLK PT      : AH : <not used>
PRESET      : AH : <not used>
RESET       : AH : <not used>
OE 0        : AH : <not used>
OE 1        : AH : <not used>
OE 2        : AH : <not used>
OE 3        : AH : <not used>



                              Logic Block C
                 ____________________________________________
                 |   |= >hva_chassis..                  |   |                 
                 |   |= >bp_end_addr..                  |   |                 
                 |   |= >\sp_read:co..                  |   |                 
                 |   |= >bp_start_ad..                  |   |                 
                 |   |= >bp_end_addr..                  |  2|= (S_13)         
                 |   |= >\sp_read:co..                  |   |                 
                 |   |= >sinphase_ze..    not used:919 >|   |                 
                 |   |= >bpd_h_trist..                  |   |                 
                 |   |= >bp_start_ad..                  |  3|= bpctrl_h_tristate 
                 |   |= >\sp_read:co..                  |   |                 
                 |   |= >\sp_read:co..           (S_8) =|   |                 
                 |   |= >bpctrl(0).Q                    |   |                 
                 |   |= >\sp_read:co..                  |  4|= bpd_l_tristate 
                 |   |= >bp_start_ad..                  |   |                 
                 |   |= >bp_end_addr..          (S_14) =|   |                 
                 |   |> not used:355                    |   |                 
                 |   |> not used:356                    |  5|= bpctrl_l_dir   
                 |   |= >bp_end_addr..                  |   |                 
                 |   |= >\sp_read:co..    not used:925 >|   |                 
                 |   |> not used:359                    |   |                 
                 |   |= >bp_end_addr..                  |  6|= (S_10)         
                 |   |= >bp_end_addr..                  |   |                 
                 |   |= >\sp_read:co..    not used:927 >|   |                 
                 |   |> not used:363                    |   |                 
                 |   |> not used:364                    |  7|= bpctrl_l_tristate 
                 |   |= >bp_end_addr..                  |   |                 
                 |   |> not used:366            (S_12) =|   |                 
                 |   |> not used:367                    |   |                 
                 |   |> not used:368                    |  8|= bpctrl_h_dir   
                 |   |> not used:369                    |   |                 
                 |   |> not used:370      not used:931 >|   |                 
                 |   |> not used:371                    |   |                 
                 |   |= >bp_end_addr..                  |  9|= bpd_l_dir      
                 |   |> not used:373                    |   |                 
                 |   |= >\sp_read:co..          (S_11) =|   |                 
                 |   |= >bp_start_ad..                  |   |                 
                 |   |= >\sp_read:co..                  |   |                 
                 |   |> not used:377                    |   |                 
                 |   |= >\sp_read:ol..                  |   |                 
                 ____________________________________________


  Information: Macrocell Utilization.

                     Description        Used     Max
                 ______________________________________
                 | I/O Macrocells     |    8  |    8  |
                 | Buried Macrocells  |    4  |    8  |
                 | PIM Input Connects |   26  |   36  |
                 ______________________________________
                                          38  /   52   = 73  %


----------------------------------------------------------------------------
PLD Compiler Software:        C37KFIT.EXE    22/DEC/2000  [v4.02 ] 6.2 IR 27

LOGIC BLOCK D PLACEMENT   (15:40:41)

Messages:


________________________________________________________________________________
          1111111111222222222233333333334444444444555555555566666666667777777777
01234567890123456789012345678901234567890123456789012345678901234567890123456789
________________________________________________________________________________
| 0>|bpctrl(0)
XXX+++++++++++++................................................................
| 1 |UNUSED
......++++++++++++++++..........................................................
| 2>|bpctrl(1)
..........X+++++++++++++++......................................................
| 3 |UNUSED
..............++++++++++++++++..................................................
| 4>|bpctrl(2)
..................XX++++++++++++++..............................................
| 5 |UNUSED
......................++++++++++++++++..........................................
| 6>|bpctrl(3)
..........................XX++X+++++++++++......................................
| 7 |UNUSED
..............................++++++++++++++++..................................
| 8>|bpctrl(4)
..................................XX++++++++++++++..............................
| 9 |UNUSED
......................................++++++++++++++++..........................
|10>|bpctrl(5)
..........................................XX++++++++++++++......................
|11 |UNUSED
..............................................++++++++++++++++..................
|12>|bpctrl(6)
..................................................XX++++++++++++++..............
|13 |UNUSED
......................................................++++++++++++++++..........
|14>|bpctrl(7)
..........................................................XX++++++++++++++......
|15 |UNUSED
................................................................++++++++++++++++
________________________________________________________________________________

Total count of outputs placed        =  8 
Total count of unique Product Terms  =  17 
Total Product Terms to be assigned   =  17 
Max Product Terms used / available   =  17 /  80   = 21.26 %


Control Signals for Logic Block D
---------------------------------
CLK pin19: <not used>
CLK pin22: <not used>
CLK pin99: clk
CLK pin102: <not used>
CLK PT      : AH : <not used>
PRESET      : AH : GND
RESET       : AH : reset.CMB 
OE 0        : AH : bpctrl(0).Q 
OE 1        : AH : <not used>
OE 2        : AH : bpctrl(0).Q 
OE 3        : AH : <not used>



                              Logic Block D
                 ____________________________________________
                 |   |= >\sp_read:re..                  |   |                 
                 |   |= >d(8)                           |   |                 
                 |   |= >ao_from_pc_..                  |   |                 
                 |   |= >reset.CMB                      |   |                 
                 |   |= >\bp_io:bp_a..                  | 11|= bpctrl(0)      
                 |   |= >bpctrl(6).Q                    |   |                 
                 |   |= >sinphase_ze..    not used:935 >|   |                 
                 |   |= >d(6)                           |   |                 
                 |   |> not used:387                    | 12|= bpctrl(1)      
                 |   |= >bpctrl(7).Q                    |   |                 
                 |   |= >d(7)             not used:937 >|   |                 
                 |   |= >bpctrl(0).Q                    |   |                 
                 |   |= >bpctrl(4).Q                    | 13|= bpctrl(2)      
                 |   |> not used:392                    |   |                 
                 |   |= >\sp_read:co..    not used:939 >|   |                 
                 |   |= >\bp_io:bp_a..                  |   |                 
                 |   |= >d(9)                           | 14|= bpctrl(3)      
                 |   |> not used:396                    |   |                 
                 |   |= >\bp_io:bp_a..    not used:941 >|   |                 
                 |   |= >\sp_read:re..                  |   |                 
                 |   |= >bpctrl(5).Q                    | 15|= bpctrl(4)      
                 |   |> not used:400                    |   |                 
                 |   |> not used:401      not used:943 >|   |                 
                 |   |= >from_pc_req.Q                  |   |                 
                 |   |> not used:403                    | 16|= bpctrl(5)      
                 |   |> not used:404                    |   |                 
                 |   |= >\ibus_reade..    not used:945 >|   |                 
                 |   |> not used:406                    |   |                 
                 |   |> not used:407                    | 17|= bpctrl(6)      
                 |   |= >\ibus_reade..                  |   |                 
                 |   |> not used:409      not used:947 >|   |                 
                 |   |> not used:410                    |   |                 
                 |   |> not used:411                    | 18|= bpctrl(7)      
                 |   |> not used:412                    |   |                 
                 |   |> not used:413      not used:949 >|   |                 
                 |   |= >\sp_read:re..                  |   |                 
                 |   |= >\ibus_reade..                  |   |                 
                 |   |= >loopback_st..                  |   |                 
                 |   |> not used:417                    |   |                 
                 ____________________________________________


  Information: Macrocell Utilization.

                     Description        Used     Max
                 ______________________________________
                 | I/O Macrocells     |    8  |    8  |
                 | Buried Macrocells  |    0  |    8  |
                 | PIM Input Connects |   24  |   36  |
                 ______________________________________
                                          32  /   52   = 61  %


----------------------------------------------------------------------------
PLD Compiler Software:        C37KFIT.EXE    22/DEC/2000  [v4.02 ] 6.2 IR 27

LOGIC BLOCK E PLACEMENT   (15:40:41)

Messages:


________________________________________________________________________________
          1111111111222222222233333333334444444444555555555566666666667777777777
01234567890123456789012345678901234567890123456789012345678901234567890123456789
________________________________________________________________________________
| 0>|bpctrl(8)
XX++++++++++++++................................................................
| 1 |(bp_start_address_3)
......XX++++++++++++++..........................................................
| 2 |(bp_start_address_1)
..........XX++++++++++++++......................................................
| 3 |(this_chip_selected)
..............XXXX++X+++++++++..................................................
| 4>|bpctrl(10)
..................XX++++++++++++++..............................................
| 5 |(address_from_pc_0)
......................XX++++++++++++++..........................................
| 6>|bpctrl(11)
..........................XX++++++++++++++......................................
| 7 |(address_from_pc_1)
..............................XX++++++++++++++..................................
| 8 |(address_from_pc_2)
..................................XX++++++++++++++..............................
| 9 |(address_from_pc_3)
......................................XX++++++++++++++..........................
|10 |(address_from_pc_4)
..........................................XX++++++++++++++......................
|11 |(address_from_pc_5)
..............................................XX++++++++++++++..................
|12 |(bp_start_address_0)
..................................................XX++++++++++++++..............
|13 |(bp_start_address_2)
......................................................XX++++++++++++++..........
|14 |(bp_start_address_4)
..........................................................XX++++++++++++++......
|15 |(bp_start_address_5)
................................................................XX++++++++++++++
________________________________________________________________________________

Total count of outputs placed        =  16 
Total count of unique Product Terms  =  35 
Total Product Terms to be assigned   =  35 
Max Product Terms used / available   =  35 /  80   = 43.76 %


Control Signals for Logic Block E
---------------------------------
CLK pin19: <not used>
CLK pin22: <not used>
CLK pin99: clk
CLK pin102: <not used>
CLK PT      : AH : <not used>
PRESET      : AH : GND
RESET       : AH : reset.CMB 
OE 0        : AH : bpctrl(0).Q 
OE 1        : AH : <not used>
OE 2        : AH : bpctrl(0).Q 
OE 3        : AH : <not used>



                              Logic Block E
                 ____________________________________________
                 |   |= >d(11)                          |   |                 
                 |   |= >bp_start_ad..                  |   |                 
                 |   |= >ao_from_pc_..                  |   |                 
                 |   |= >reset.CMB                      |   |                 
                 |   |= >bpd(11).Q                      | 23|= bpctrl(8)      
                 |   |= >this_chip_s..                  |   |                 
                 |   |= >bp_start_ad..  (bp_start_address_3) =|   |                 
                 |   |= >bpctrl(10).Q                   |   |                 
                 |   |= >bp_start_ad..                  | 24|= (bp_start_address_1) 
                 |   |= >d(10)                          |   |                 
                 |   |= >bpctrl(8).Q    (this_chip_selected) =|   |                 
                 |   |= >\ibus_reade..                  |   |                 
                 |   |= >address_fro..                  | 25|= bpctrl(10)     
                 |   |= >d(12)                          |   |                 
                 |   |= >bpctrl(11).Q   (address_from_pc_0) =|   |                 
                 |   |= >\ibus_reade..                  |   |                 
                 |   |= >address_fro..                  | 26|= bpctrl(11)     
                 |   |= >bpd(12).Q                      |   |                 
                 |   |= >\ibus_reade..  (address_from_pc_1) =|   |                 
                 |   |= >address_fro..                  |   |                 
                 |   |= >bpd(13).Q                      | 27|= (address_from_pc_2) 
                 |   |= >address_fro..                  |   |                 
                 |   |= >bpd(14).Q      (address_from_pc_3) =|   |                 
                 |   |> not used:441                    |   |                 
                 |   |= >bpd(10).Q                      | 28|= (address_from_pc_4) 
                 |   |> not used:443                    |   |                 
                 |   |= >data_from_p..  (address_from_pc_5) =|   |                 
                 |   |> not used:445                    |   |                 
                 |   |> not used:446                    | 29|= (bp_start_address_0) 
                 |   |= >bp_start_ad..                  |   |                 
                 |   |= >address_fro..  (bp_start_address_2) =|   |                 
                 |   |= >bp_start_ad..                  |   |                 
                 |   |= >bpctrl(7).Q                    | 30|= (bp_start_address_4) 
                 |   |> not used:451                    |   |                 
                 |   |= >address_fro..  (bp_start_address_5) =|   |                 
                 |   |= >bpd(15).Q                      |   |                 
                 |   |> not used:454                    |   |                 
                 |   |= >bp_start_ad..                  |   |                 
                 |   |= >bpctrl(0).Q                    |   |                 
                 ____________________________________________


  Information: Macrocell Utilization.

                     Description        Used     Max
                 ______________________________________
                 | I/O Macrocells     |    8  |    8  |
                 | Buried Macrocells  |    8  |    8  |
                 | PIM Input Connects |   33  |   36  |
                 ______________________________________
                                          49  /   52   = 94  %


----------------------------------------------------------------------------
PLD Compiler Software:        C37KFIT.EXE    22/DEC/2000  [v4.02 ] 6.2 IR 27

LOGIC BLOCK F PLACEMENT   (15:40:41)

Messages:


________________________________________________________________________________
          1111111111222222222233333333334444444444555555555566666666667777777777
01234567890123456789012345678901234567890123456789012345678901234567890123456789
________________________________________________________________________________
| 0>|bpaddr(0)
XXXXXX++++++++++................................................................
| 1 |UNUSED
......++++++++++++++++..........................................................
| 2>|bpaddr(1)
..........XXXXXX++++++++++......................................................
| 3 |UNUSED
..............++++++++++++++++..................................................
| 4>|bpaddr(2)
..................XXXXXX++++++++++..............................................
| 5 |UNUSED
......................++++++++++++++++..........................................
| 6>|bpaddr(3)
..........................XXXXXX++++++++++......................................
| 7 |UNUSED
..............................++++++++++++++++..................................
| 8>|bpaddr(4)
..................................XXXXXX++++++++++..............................
| 9 |UNUSED
......................................++++++++++++++++..........................
|10>|bpaddr(5)
..........................................XXXXXX++++++++++......................
|11 |UNUSED
..............................................++++++++++++++++..................
|12>|bpaddr(6)
..................................................XXXXXX++++++++++..............
|13 |UNUSED
......................................................++++++++++++++++..........
|14>|bpaddr(7)
..........................................................XXXXXX++++++++++......
|15 |UNUSED
................................................................++++++++++++++++
________________________________________________________________________________

Total count of outputs placed        =  8 
Total count of unique Product Terms  =  48 
Total Product Terms to be assigned   =  48 
Max Product Terms used / available   =  48 /  80   = 60.1  %


Control Signals for Logic Block F
---------------------------------
CLK pin19: <not used>
CLK pin22: <not used>
CLK pin99: clk
CLK pin102: <not used>
CLK PT      : AH : <not used>
PRESET      : AH : GND
RESET       : AH : reset.CMB 
OE 0        : AH : <not used>
OE 1        : AH : <not used>
OE 2        : AH : <not used>
OE 3        : AH : <not used>



                              Logic Block F
                 ____________________________________________
                 |   |= >address_fro..                  |   |                 
                 |   |= >bpaddr(0).Q                    |   |                 
                 |   |= >sensor_addr..                  |   |                 
                 |   |= >address_fro..                  |   |                 
                 |   |= >\bp_io:bp_a..                  | 32|= bpaddr(0)      
                 |   |= >address_fro..                  |   |                 
                 |   |= >\bp_io:bp_a..    not used:967 >|   |                 
                 |   |= >sensor_to_b..                  |   |                 
                 |   |= >bpaddr(6).Q                    | 33|= bpaddr(1)      
                 |   |= >bpaddr(2).Q                    |   |                 
                 |   |> not used:467      not used:969 >|   |                 
                 |   |= >address_fro..                  |   |                 
                 |   |= >bpaddr(3).Q                    | 34|= bpaddr(2)      
                 |   |= >bpaddr(7).Q                    |   |                 
                 |   |= >sensor_addr..    not used:971 >|   |                 
                 |   |= >\bp_io:bp_a..                  |   |                 
                 |   |= >bpaddr(4).Q                    | 35|= bpaddr(3)      
                 |   |> not used:474                    |   |                 
                 |   |= >sensor_addr..    not used:973 >|   |                 
                 |   |= >bpaddr(5).Q                    |   |                 
                 |   |= >bpaddr(1).Q                    | 36|= bpaddr(4)      
                 |   |= >reset.CMB                      |   |                 
                 |   |> not used:479      not used:975 >|   |                 
                 |   |= >sensor_addr..                  |   |                 
                 |   |= >sensor_addr..                  | 37|= bpaddr(5)      
                 |   |> not used:482                    |   |                 
                 |   |= >sensor_addr..    not used:977 >|   |                 
                 |   |> not used:484                    |   |                 
                 |   |= >sensor_addr..                  | 38|= bpaddr(6)      
                 |   |> not used:486                    |   |                 
                 |   |= >address_fro..    not used:979 >|   |                 
                 |   |= >from_pc_req.Q                  |   |                 
                 |   |> not used:489                    | 39|= bpaddr(7)      
                 |   |= >address_fro..                  |   |                 
                 |   |= >address_fro..    not used:981 >|   |                 
                 |   |= >sensor_addr..                  |   |                 
                 |   |= >address_fro..                  |   |                 
                 |   |= >loopback_st..                  |   |                 
                 |   |> not used:495                    |   |                 
                 ____________________________________________


  Information: Macrocell Utilization.

                     Description        Used     Max
                 ______________________________________
                 | I/O Macrocells     |    8  |    8  |
                 | Buried Macrocells  |    0  |    8  |
                 | PIM Input Connects |   31  |   36  |
                 ______________________________________
                                          39  /   52   = 75  %


----------------------------------------------------------------------------
PLD Compiler Software:        C37KFIT.EXE    22/DEC/2000  [v4.02 ] 6.2 IR 27

LOGIC BLOCK G PLACEMENT   (15:40:41)

Messages:


________________________________________________________________________________
          1111111111222222222233333333334444444444555555555566666666667777777777
01234567890123456789012345678901234567890123456789012345678901234567890123456789
________________________________________________________________________________
| 0>|bpd_h_dir
++X+++++++++++++................................................................
| 1 |(\bp_io:timeout_1\)
......XXXX++XX++XX+X++..........................................................
| 2>|bpd_h_tristate
..........XX++XX++X+++++++......................................................
| 3 |(sensor_data_0)
..............++++++XX++++++++..................................................
| 4>|bpaddr_tristate
..................X+++XX++++++++++..............................................
| 5 |(\bp_io:timeout_0\)
......................++XXXXXXXXXXX+XX..........................................
| 6>|bpaddr_dir
..........................+++++++++X++++++......................................
| 7 |(\bp_io:bp_access_stateSBV_1\)
..............................++++++++XXXXX+++..................................
| 8 |(\bp_io:bp_access_stateSBV_2\)
..................................++++XXXXXXXX++++..............................
| 9 |(\bp_io:bp_access_stateSBV_0\)
......................................XX++++++XXXX++XX..........................
|10>|led1
..........................................++++++++XX++X+++......................
|11 |(\bp_io:timeout_2\)
..............................................+++++++++XXXX+XX..................
|12>|led2
..................................................+++++++++X++++++..............
|13 |(\sp_read:counter_address_7\)
......................................................++++++++++XX++++..........
|14>|led3
..........................................................++++X+++++++++++......
|15 |(sensor_to_bp_read_ack)
................................................................++XX++++++++++++
________________________________________________________________________________

Total count of outputs placed        =  16 
Total count of unique Product Terms  =  60 
Total Product Terms to be assigned   =  70 
Max Product Terms used / available   =  62 /  80   = 77.51 %


Control Signals for Logic Block G
---------------------------------
CLK pin19: <not used>
CLK pin22: <not used>
CLK pin99: clk
CLK pin102: <not used>
CLK PT      : AH : <not used>
PRESET      : AH : GND
RESET       : AH : reset.CMB 
OE 0        : AH : <not used>
OE 1        : AH : <not used>
OE 2        : AH : <not used>
OE 3        : AH : <not used>



                              Logic Block G
                 ____________________________________________
                 |   |= >slow                           |   |                 
                 |   |= >fast                           |   |                 
                 |   |= >from_pc_req.Q                  |   |                 
                 |   |= >reset.CMB                      |   |                 
                 |   |= >bpd(0)                         | 42|= bpd_h_dir      
                 |   |= >\bp_io:time..                  |   |                 
                 |   |= >\bp_io:bp_a..  (\bp_io:timeout_1\) =|   |                 
                 |   |= >sensor_to_b..                  |   |                 
                 |   |> not used:504                    | 43|= bpd_h_tristate 
                 |   |= >S_1.CMB                        |   |                 
                 |   |> not used:506    (sensor_data_0) =|   |                 
                 |   |= >bpctrl(0).Q                    |   |                 
                 |   |> not used:508                    | 44|= bpaddr_tristate 
                 |   |> not used:509                    |   |                 
                 |   |> not used:510    (\bp_io:timeout_0\) =|   |                 
                 |   |= >\bp_io:bp_a..                  |   |                 
                 |   |= >\bp_io:bp_a..                  | 45|= bpaddr_dir     
                 |   |> not used:513                    |   |                 
                 |   |> not used:514    (\bp_io:bp_access_stateSBV_1\) =|   |                 
                 |   |= >loopback_st..                  |   |                 
                 |   |> not used:516                    | 46|= (\bp_io:bp_access_stateSBV_2\) 
                 |   |= >S_2.CMB                        |   |                 
                 |   |= >sensor_data..  (\bp_io:bp_access_stateSBV_0\) =|   |                 
                 |   |> not used:519                    |   |                 
                 |   |> not used:520                    | 47|= led1           
                 |   |= >\bp_io:time..                  |   |                 
                 |   |> not used:522    (\bp_io:timeout_2\) =|   |                 
                 |   |> not used:523                    |   |                 
                 |   |> not used:524                    | 48|= led2           
                 |   |> not used:525                    |   |                 
                 |   |> not used:526    (\sp_read:counter_address_7\) =|   |                 
                 |   |> not used:527                    |   |                 
                 |   |> not used:528                    | 49|= led3           
                 |   |= >\bp_io:time..                  |   |                 
                 |   |> not used:530    (sensor_to_bp_read_ack) =|   |                 
                 |   |> not used:531                    |   |                 
                 |   |> not used:532                    |   |                 
                 |   |> not used:533                    |   |                 
                 |   |> not used:534                    |   |                 
                 ____________________________________________


  Information: Macrocell Utilization.

                     Description        Used     Max
                 ______________________________________
                 | I/O Macrocells     |    8  |    8  |
                 | Buried Macrocells  |    8  |    8  |
                 | PIM Input Connects |   17  |   36  |
                 ______________________________________
                                          33  /   52   = 63  %


----------------------------------------------------------------------------
PLD Compiler Software:        C37KFIT.EXE    22/DEC/2000  [v4.02 ] 6.2 IR 27

LOGIC BLOCK H PLACEMENT   (15:40:41)

Messages:


________________________________________________________________________________
          1111111111222222222233333333334444444444555555555566666666667777777777
01234567890123456789012345678901234567890123456789012345678901234567890123456789
________________________________________________________________________________
| 0 |(S_17)
XXXXXXXXXXXXXXXX................................................................
| 1 |UNUSED
......++++++++++++++++..........................................................
| 2 |(sensor_data_15)
..........+++++++++X++X+++......................................................
| 3 |(sensor_to_ibus_req)
..............++XXX+++++++++++..................................................
| 4 |(sensor_address_5)
..................++XX++XX++++++++..............................................
| 5 |(sensor_address_0)
......................++++++XX++XX++++..........................................
| 6 |(\sp_read:counter_read_stateSBV_3\)
..........................XX++X+++++XX++XX......................................
| 7 |(S_16)
..............................+X++XX++XX++X+XX..................................
| 8 |(\sp_read:counter_read_stateSBV_1\)hva_chassis_en_l
..................................+++++++++X++X+XX..............................
| 9 |(sensor_address_2)
......................................+++++++++X++X+XX..........................
|10 |(sensor_address_6)
..........................................+++++++++X++X+XX......................
|11 |(sensor_address_3)
..............................................++++++++++++++XX..................
|12 |(sensor_address_4)
..................................................+++++X++X+++++++..............
|13 |(sensor_to_bp_read_req)
......................................................+++++X++++++++++..........
|14 |UNUSED
..........................................................++++++++++++++++......
|15 |(\ibus_reader:il_read_stateSBV_0\)
................................................................XXXXXXXXXX++++++
________________________________________________________________________________

Total count of outputs placed        =  14 
Total count of unique Product Terms  =  71 
Total Product Terms to be assigned   =  71 
Max Product Terms used / available   =  71 /  80   = 88.76 %


Control Signals for Logic Block H
---------------------------------
CLK pin19: <not used>
CLK pin22: <not used>
CLK pin99: clk
CLK pin102: <not used>
CLK PT      : AH : <not used>
PRESET      : AH : GND
RESET       : AH : reset.CMB 
OE 0        : AH : <not used>
OE 1        : AH : <not used>
OE 2        : AH : <not used>
OE 3        : AH : <not used>



                              Logic Block H
                 ____________________________________________
                 |   |= >hva_chassis..                  |   |                 
                 |   |= >loopback_st..                  |   |                 
                 |   |= >ao_from_pc_..                  |   |                 
                 |   |= >reset.CMB                      |   |                 
                 |   |= >write_to_bp..                  | 51|= (S_17)         
                 |   |= >sensor_addr..                  |   |                 
                 |   |= >\sp_read:co..    not used:999 >|   |                 
                 |   |= >\ibus_reade..                  |   |                 
                 |   |= >sensor_addr..                  | 52|= (sensor_data_15) 
                 |   |= >\sp_read:co..                  |   |                 
                 |   |= >\sp_read:co..  (sensor_to_ibus_req) =|   |                 
                 |   |= >\sp_read:ol..                  |   |                 
                 |   |= >\sp_read:co..                  | 53|= (sensor_address_5) 
                 |   |= >sensor_addr..                  |   |                 
                 |   |= >sinphase_ze..  (sensor_address_0) =|   |                 
                 |   |= >\ibus_reade..                  |   |                 
                 |   |= >sensor_addr..                  | 54|= (\sp_read:counter_read_stateSBV_3\) 
                 |   |= >bp_end_addr..                  |   |                 
                 |   |= >\ibus_reade..          (S_16) =|   |                 
                 |   |= >\sp_read:co..                  |   |                 
                 |   |= >\sp_read:co..                  | 55|= (\sp_read:counter_read_stateSBV_1\)hva_chassis_en_l 
                 |   |= >\sp_read:co..                  |   |                 
                 |   |= >bp_start_ad..  (sensor_address_2) =|   |                 
                 |   |= >sensor_addr..                  |   |                 
                 |   |= >sensor_addr..                  | 56|= (sensor_address_6) 
                 |   |= >\sp_read:co..                  |   |                 
                 |   |= >\sp_read:co..  (sensor_address_3) =|   |                 
                 |   |= >\ibus_reade..                  |   |                 
                 |   |= >\ibus_reade..                  | 57|= (sensor_address_4) 
                 |   |= >\ibus_reade..                  |   |                 
                 |   |> not used:565    (sensor_to_bp_read_req) =|   |                 
                 |   |> not used:566                    |   |                 
                 |   |= >\sp_read:co..                  | 58|* not used       
                 |   |= >to_pc_ack.Q                    |   |                 
                 |   |> not used:569    (\ibus_reader:il_read_stateSBV_0\) =|   |                 
                 |   |= >sensor_data..                  |   |                 
                 |   |= >\ibus_reade..                  |   |                 
                 |   |> not used:572                    |   |                 
                 |   |= >sensor_to_b..                  |   |                 
                 ____________________________________________


  Information: Macrocell Utilization.

                     Description        Used     Max
                 ______________________________________
                 | I/O Macrocells     |    7  |    8  |
                 | Buried Macrocells  |    7  |    8  |
                 | PIM Input Connects |   35  |   36  |
                 ______________________________________
                                          49  /   52   = 94  %


----------------------------------------------------------------------------
PLD Compiler Software:        C37KFIT.EXE    22/DEC/2000  [v4.02 ] 6.2 IR 27

LOGIC BLOCK I PLACEMENT   (15:40:41)

Messages:


________________________________________________________________________________
          1111111111222222222233333333334444444444555555555566666666667777777777
01234567890123456789012345678901234567890123456789012345678901234567890123456789
________________________________________________________________________________
| 0 |(\ibus_reader:timeout_2\)
XXXXXXXXXXXXXXX+................................................................
| 1 |(il_tristate)
......+++++++++XXX++++..........................................................
| 2 |(S_18)
..........++++++++X+XX++++......................................................
| 3 |UNUSED
..............++++++++++++++++..................................................
| 4 |(from_pc_req)
..................+X++XX++++++++++..............................................
| 5 |UNUSED
......................++++++++++++++++..........................................
| 6 |[i/p]
..........................++++++++++++++++......................................
| 7 |(\ibus_reader:il_read_stateSBV_2\)
..............................XXXXXXXXXXXXX+++..................................
| 8 |UNUSED
..................................++++++++++++++++..............................
| 9 |(\ibus_reader:il_read_stateSBV_1\)
......................................X++++XXXXXXXX+++..........................
|10 |UNUSED
..........................................++++++++++++++++......................
|11 |UNUSED
..............................................++++++++++++++++..................
|12 |(\ibus_reader:timeout_3\)
..................................................+XXXXXXXXXXXX+++..............
|13 |UNUSED
......................................................++++++++++++++++..........
|14 |UNUSED
..........................................................++++++++++++++++......
|15 |(\ibus_reader:timeout_0\)
................................................................XXXXXXXXXXXXXXX+
________________________________________________________________________________

Total count of outputs placed        =  8 
Total count of unique Product Terms  =  72 
Total Product Terms to be assigned   =  73 
Max Product Terms used / available   =  72 /  80   = 90.1  %


Control Signals for Logic Block I
---------------------------------
CLK pin19: <not used>
CLK pin22: <not used>
CLK pin99: clk
CLK pin102: <not used>
CLK PT      : AH : <not used>
PRESET      : AH : GND
RESET       : AH : reset.CMB 
OE 0        : AH : <not used>
OE 1        : AH : <not used>
OE 2        : AH : <not used>
OE 3        : AH : <not used>



                              Logic Block I
                 ____________________________________________
                 |   |= >data_from_p..                  |   |                 
                 |   |= >\ibus_reade..                  |   |                 
                 |   |= >ao_from_pc_..                  |   |                 
                 |   |= >\ibus_reade..                  |   |                 
                 |   |= >write_to_bp..                  | 63|= (\ibus_reader:timeout_2\) 
                 |   |= >\ibus_reade..                  |   |                 
                 |   |> not used:580     (il_tristate) =|   |                 
                 |   |= >bpctrl(10).Q                   |   |                 
                 |   |= >to_pc_ack.Q                    | 64|= (S_18)         
                 |   |= >bpctrl(7).Q                    |   |                 
                 |   |= >bpctrl(11).Q    not used:1017 >|   |                 
                 |   |= >\ibus_reade..                  |   |                 
                 |   |= >tristate_st..                  | 65|= (from_pc_req)  
                 |   |> not used:587                    |   |                 
                 |   |= >\ibus_reade..   not used:1019 >|   |                 
                 |   |= >\ibus_reade..                  |   |                 
                 |   |> not used:590                    | 66|= sinphase_zeros 
                 |   |= >bpctrl(8).Q                    |   |                 
                 |   |= >\ibus_reade..  (\ibus_reader:il_read_stateSBV_2\) =|   |                 
                 |   |= >loopback_st..                  |   |                 
                 |   |> not used:594                    | 67|* not used       
                 |   |= >reset.CMB                      |   |                 
                 |   |= >this_chip_s..  (\ibus_reader:il_read_stateSBV_1\) =|   |                 
                 |   |= >\ibus_reade..                  |   |                 
                 |   |> not used:598                    | 68|* not used       
                 |   |> not used:599                    |   |                 
                 |   |> not used:600     not used:1025 >|   |                 
                 |   |> not used:601                    |   |                 
                 |   |> not used:602                    | 69|= (\ibus_reader:timeout_3\) 
                 |   |= >il_tristate.Q                  |   |                 
                 |   |> not used:604     not used:1027 >|   |                 
                 |   |> not used:605                    |   |                 
                 |   |> not used:606                    | 70|* not used       
                 |   |> not used:607                    |   |                 
                 |   |> not used:600    (\ibus_reader:timeout_0\) =|   |                 
                 |   |> not used:606                    |   |                 
                 |   |> not used:610                    |   |                 
                 |   |> not used:611                    |   |                 
                 |   |> not used:612                    |   |                 
                 ____________________________________________


  Information: Macrocell Utilization.

                     Description        Used     Max
                 ______________________________________
                 | I/O Macrocells     |    5  |    8  |
                 | Buried Macrocells  |    4  |    8  |
                 | PIM Input Connects |   21  |   36  |
                 ______________________________________
                                          30  /   52   = 57  %


----------------------------------------------------------------------------
PLD Compiler Software:        C37KFIT.EXE    22/DEC/2000  [v4.02 ] 6.2 IR 27

LOGIC BLOCK J PLACEMENT   (15:40:41)

Messages:


________________________________________________________________________________
          1111111111222222222233333333334444444444555555555566666666667777777777
01234567890123456789012345678901234567890123456789012345678901234567890123456789
________________________________________________________________________________
| 0 |(S_15)
XXXXXXXXXXXXXXXX................................................................
| 1 |(\sp_read:old_phase\)
......++++++++++++X+++..........................................................
| 2 |UNUSED
..........++++++++++++++++......................................................
| 3 |(S_2)
..............++XX+XXXXXXXXX++..................................................
| 4 |UNUSED
..................++++++++++++++++..............................................
| 5 |UNUSED
......................++++++++++++++++..........................................
| 6 |UNUSED
..........................++++++++++++++++......................................
| 7 |(S_1)
..............................XXXXXXXXXXXXXXXX..................................
| 8 |UNUSED
..................................++++++++++++++++..............................
| 9 |UNUSED
......................................++++++++++++++++..........................
|10 |UNUSED
..........................................++++++++++++++++......................
|11 |(\sp_read:cmp_vv_us_MODGEN_10\)
..............................................XXXXXXXXXXXXXXXX..................
|12>|reset
..................................................++++++++++++X+++..............
|13 |UNUSED
......................................................++++++++++++++++..........
|14 |UNUSED
..........................................................++++++++++++++++......
|15 |(S_9)
................................................................XXXXXXXXXXXXXXXX
________________________________________________________________________________

Total count of outputs placed        =  7 
Total count of unique Product Terms  =  77 
Total Product Terms to be assigned   =  77 
Max Product Terms used / available   =  77 /  80   = 96.26 %


Control Signals for Logic Block J
---------------------------------
CLK pin19: <not used>
CLK pin22: <not used>
CLK pin99: clk
CLK pin102: <not used>
CLK PT      : AH : <not used>
PRESET      : AH : fast * sinphase_zeros * /slow 
RESET       : AH : fast * /sinphase_zeros * /slow 
OE 0        : AH : <not used>
OE 1        : AH : <not used>
OE 2        : AH : <not used>
OE 3        : AH : <not used>



                              Logic Block J
                 ____________________________________________
                 |   |= >slow                           |   |                 
                 |   |= >fast                           |   |                 
                 |   |= >\sp_read:co..                  |   |                 
                 |   |= >bp_end_addr..                  |   |                 
                 |   |= >bp_end_addr..                  | 72|= (S_15)         
                 |   |= >\sp_read:co..                  |   |                 
                 |   |= >bp_start_ad..  (\sp_read:old_phase\) =|   |                 
                 |   |= >bp_end_addr..                  |   |                 
                 |   |= >\sp_read:co..                  | 73|* not used       
                 |   |= >\sp_read:co..                  |   |                 
                 |   |= >\sp_read:co..           (S_2) =|   |                 
                 |   |= >\sp_read:ol..                  |   |                 
                 |   |= >\sp_read:co..                  | 74|* not used       
                 |   |> not used:626                    |   |                 
                 |   |= >sinphase_ze..   not used:1035 >|   |                 
                 |   |= >bp_end_addr..                  |   |                 
                 |   |> not used:629                    | 75|* not used       
                 |   |= >bp_start_ad..                  |   |                 
                 |   |= >bp_start_ad..           (S_1) =|   |                 
                 |   |= >\sp_read:co..                  |   |                 
                 |   |= >\sp_read:co..                  | 76|* not used       
                 |   |= >\sp_read:co..                  |   |                 
                 |   |= >hva_chassis..   not used:1039 >|   |                 
                 |   |> not used:636                    |   |                 
                 |   |= >\sp_read:co..                  | 77|* not used       
                 |   |= >bp_end_addr..                  |   |                 
                 |   |> not used:639    (\sp_read:cmp_vv_us_MODGEN_10\) =|   |                 
                 |   |> not used:640                    |   |                 
                 |   |= >bp_end_addr..                  | 78|= reset          
                 |   |> not used:642                    |   |                 
                 |   |= >\sp_read:co..   not used:1043 >|   |                 
                 |   |> not used:644                    |   |                 
                 |   |= >bp_end_addr..                  | 79|* not used       
                 |   |> not used:646                    |   |                 
                 |   |= >bp_end_addr..           (S_9) =|   |                 
                 |   |> not used:648                    |   |                 
                 |   |> not used:649                    |   |                 
                 |   |> not used:650                    |   |                 
                 |   |= >\sp_read:co..                  |   |                 
                 ____________________________________________


  Information: Macrocell Utilization.

                     Description        Used     Max
                 ______________________________________
                 | I/O Macrocells     |    2  |    8  |
                 | Buried Macrocells  |    5  |    8  |
                 | PIM Input Connects |   28  |   36  |
                 ______________________________________
                                          35  /   52   = 67  %


----------------------------------------------------------------------------
PLD Compiler Software:        C37KFIT.EXE    22/DEC/2000  [v4.02 ] 6.2 IR 27

LOGIC BLOCK K PLACEMENT   (15:40:41)

Messages:


________________________________________________________________________________
          1111111111222222222233333333334444444444555555555566666666667777777777
01234567890123456789012345678901234567890123456789012345678901234567890123456789
________________________________________________________________________________
| 0 |(S_7)
XXXXXXXXXXXXXXXX................................................................
| 1 |UNUSED
......++++++++++++++++..........................................................
| 2 |UNUSED
..........++++++++++++++++......................................................
| 3 |(S_4)
..............++XXXXXXXXXXX+++..................................................
| 4 |UNUSED
..................++++++++++++++++..............................................
| 5 |UNUSED
......................++++++++++++++++..........................................
| 6 |UNUSED
..........................++++++++++++++++......................................
| 7 |(S_3)
..............................XXXXXXXXXXXXXXXX..................................
| 8 |UNUSED
..................................++++++++++++++++..............................
| 9 |UNUSED
......................................++++++++++++++++..........................
|10 |UNUSED
..........................................++++++++++++++++......................
|11 |(\sp_read:counter_read_stateSBV_2\)
..............................................XXXX++XX++++++++..................
|12 |(S_6)
..................................................XX++XXXXXXXXX+++..............
|13 |UNUSED
......................................................++++++++++++++++..........
|14 |UNUSED
..........................................................++++++++++++++++......
|15 |(S_5)
................................................................XXXXXXXXXXXXXXXX
________________________________________________________________________________

Total count of outputs placed        =  6 
Total count of unique Product Terms  =  75 
Total Product Terms to be assigned   =  76 
Max Product Terms used / available   =  76 /  80   = 95.1  %


Control Signals for Logic Block K
---------------------------------
CLK pin19: <not used>
CLK pin22: <not used>
CLK pin99: clk
CLK pin102: <not used>
CLK PT      : AH : <not used>
PRESET      : AH : GND
RESET       : AH : reset.CMB 
OE 0        : AH : <not used>
OE 1        : AH : <not used>
OE 2        : AH : <not used>
OE 3        : AH : <not used>



                              Logic Block K
                 ____________________________________________
                 |   |= >hva_chassis..                  |   |                 
                 |   |= >bp_end_addr..                  |   |                 
                 |   |= >\sp_read:cm..                  |   |                 
                 |   |= >reset.CMB                      |   |                 
                 |   |= >bp_end_addr..                  | 82|= (S_7)          
                 |   |= >\sp_read:co..                  |   |                 
                 |   |= >sinphase_ze..   not used:1047 >|   |                 
                 |   |= >bp_end_addr..                  |   |                 
                 |   |= >\sp_read:co..                  | 83|* not used       
                 |   |= >\sp_read:co..                  |   |                 
                 |   |= >\sp_read:co..           (S_4) =|   |                 
                 |   |= >\sp_read:ol..                  |   |                 
                 |   |= >\sp_read:co..                  | 84|* not used       
                 |   |= >bp_start_ad..                  |   |                 
                 |   |= >sensor_to_b..   not used:1051 >|   |                 
                 |   |= >bp_start_ad..                  |   |                 
                 |   |> not used:668                    | 85|* not used       
                 |   |= >bp_end_addr..                  |   |                 
                 |   |= >\sp_read:co..           (S_3) =|   |                 
                 |   |= >\sp_read:co..                  |   |                 
                 |   |= >bp_end_addr..                  | 86|* not used       
                 |   |= >\sp_read:co..                  |   |                 
                 |   |> not used:674     not used:1055 >|   |                 
                 |   |= >bp_start_ad..                  |   |                 
                 |   |> not used:676                    | 87|* not used       
                 |   |= >bp_end_addr..                  |   |                 
                 |   |= >\sp_read:co..  (\sp_read:counter_read_stateSBV_2\) =|   |                 
                 |   |> not used:679                    |   |                 
                 |   |= >bp_end_addr..                  | 88|= (S_6)          
                 |   |> not used:681                    |   |                 
                 |   |> not used:682     not used:1059 >|   |                 
                 |   |> not used:683                    |   |                 
                 |   |= >bp_end_addr..                  | 89|* not used       
                 |   |> not used:685                    |   |                 
                 |   |> not used:686             (S_5) =|   |                 
                 |   |> not used:687                    |   |                 
                 |   |= >\sp_read:co..                  |   |                 
                 |   |> not used:689                    |   |                 
                 |   |= >\sp_read:co..                  |   |                 
                 ____________________________________________


  Information: Macrocell Utilization.

                     Description        Used     Max
                 ______________________________________
                 | I/O Macrocells     |    2  |    8  |
                 | Buried Macrocells  |    4  |    8  |
                 | PIM Input Connects |   28  |   36  |
                 ______________________________________
                                          34  /   52   = 65  %


----------------------------------------------------------------------------
PLD Compiler Software:        C37KFIT.EXE    22/DEC/2000  [v4.02 ] 6.2 IR 27

LOGIC BLOCK L PLACEMENT   (15:40:41)

Messages:


________________________________________________________________________________
          1111111111222222222233333333334444444444555555555566666666667777777777
01234567890123456789012345678901234567890123456789012345678901234567890123456789
________________________________________________________________________________
| 0 |(data_from_pc_14)
XX++++++++++++++................................................................
| 1 |(bp_start_address_7)
......XX++++++++++++++..........................................................
| 2 |(bp_end_address_7)ao_to_pc_ack
..........XX++++++++++++++......................................................
| 3 |(address_from_pc_6)
..............XX++++++++++++++..................................................
| 4>|ao_to_pc_strobe
..................XX++++++++++++++..............................................
| 5 |(bp_end_address_0)
......................XX++++++++++++++..........................................
| 6>|ao_from_pc_ack
..........................X+++++++++++++++......................................
| 7 |(bp_end_address_1)
..............................XX++++++++++++++..................................
| 8 |(bp_end_address_2)ao_from_pc_strobe
..................................XX++++++++++++++..............................
| 9 |(bp_end_address_3)
......................................XX++++++++++++++..........................
|10 |(bp_end_address_4)
..........................................XX++++++++++++++......................
|11 |(bp_end_address_5)
..............................................XX++++++++++++++..................
|12 |(bp_end_address_6)
..................................................XX++++++++++++++..............
|13 |(bp_start_address_6)
......................................................XX++++++++++++++..........
|14 |(data_from_pc_13)d(0)
..........................................................XX++++++++++++++......
|15 |(data_from_pc_15)
................................................................XX++++++++++++++
________________________________________________________________________________

Total count of outputs placed        =  16 
Total count of unique Product Terms  =  31 
Total Product Terms to be assigned   =  31 
Max Product Terms used / available   =  31 /  80   = 38.76 %


Control Signals for Logic Block L
---------------------------------
CLK pin19: <not used>
CLK pin22: <not used>
CLK pin99: clk
CLK pin102: <not used>
CLK PT      : AH : <not used>
PRESET      : AH : GND
RESET       : AH : reset.CMB 
OE 0        : AH : /il_tristate.Q 
OE 1        : AH : <not used>
OE 2        : AH : /il_tristate.Q 
OE 3        : AH : <not used>



                              Logic Block L
                 ____________________________________________
                 |   |= >data_from_p..                  |   |                 
                 |   |= >bp_end_addr..                  |   |                 
                 |   |= >ao_from_pc_..                  |   |                 
                 |   |= >bp_end_addr..                  |   |                 
                 |   |= >bp_end_addr..                  | 91|= (data_from_pc_14) 
                 |   |= >ao_to_pc_ack                   |   |                 
                 |   |= >address_fro..  (bp_start_address_7) =|   |                 
                 |   |= >il_tristate.Q                  |   |                 
                 |   |> not used:699                    | 92|= (bp_end_address_7)ao_to_pc_ack 
                 |   |= >d(13)                          |   |                 
                 |   |= >bpctrl(8).Q    (address_from_pc_6) =|   |                 
                 |   |= >data_from_p..                  |   |                 
                 |   |= >d(14)                          | 93|= ao_to_pc_strobe 
                 |   |= >address_fro..                  |   |                 
                 |   |= >bpctrl(7).Q    (bp_end_address_0) =|   |                 
                 |   |= >data_from_p..                  |   |                 
                 |   |= >address_fro..                  | 94|= ao_from_pc_ack 
                 |   |= >bp_start_ad..                  |   |                 
                 |   |= >bpctrl(4).Q    (bp_end_address_1) =|   |                 
                 |   |> not used:710                    |   |                 
                 |   |= >bpctrl(5).Q                    | 95|= (bp_end_address_2)ao_from_pc_strobe 
                 |   |= >reset.CMB                      |   |                 
                 |   |= >\ibus_write..  (bp_end_address_3) =|   |                 
                 |   |= >bpctrl(6).Q                    |   |                 
                 |   |= >bpctrl(10).Q                   | 96|= (bp_end_address_4) 
                 |   |= >d(15)                          |   |                 
                 |   |= >\ibus_reade..  (bp_end_address_5) =|   |                 
                 |   |= >bp_end_addr..                  |   |                 
                 |   |= >bp_end_addr..                  | 97|= (bp_end_address_6) 
                 |   |= >\ibus_reade..                  |   |                 
                 |   |> not used:721    (bp_start_address_6) =|   |                 
                 |   |= >bpctrl(11).Q                   |   |                 
                 |   |= >bp_end_addr..                  | 98|= (data_from_pc_13)d(0) 
                 |   |= >\ibus_write..                  |   |                 
                 |   |= >bp_end_addr..  (data_from_pc_15) =|   |                 
                 |   |= >bp_end_addr..                  |   |                 
                 |   |= >\ibus_reade..                  |   |                 
                 |   |= >bp_start_ad..                  |   |                 
                 |   |> not used:729                    |   |                 
                 ____________________________________________


  Information: Macrocell Utilization.

                     Description        Used     Max
                 ______________________________________
                 | I/O Macrocells     |    8  |    8  |
                 | Buried Macrocells  |    8  |    8  |
                 | PIM Input Connects |   35  |   36  |
                 ______________________________________
                                          51  /   52   = 98  %


----------------------------------------------------------------------------
PLD Compiler Software:        C37KFIT.EXE    22/DEC/2000  [v4.02 ] 6.2 IR 27

LOGIC BLOCK M PLACEMENT   (15:40:41)

Messages:


________________________________________________________________________________
          1111111111222222222233333333334444444444555555555566666666667777777777
01234567890123456789012345678901234567890123456789012345678901234567890123456789
________________________________________________________________________________
| 0 |(sensor_address_1)d(1)
XXXX++++++++++++................................................................
| 1 |UNUSED
......++++++++++++++++..........................................................
| 2 |(\sp_read:reset_count_1\)d(2)
..........XX++++++++++++++......................................................
| 3 |(\sp_read:counter_address_4\)
..............XX++++++++++++++..................................................
| 4 |(\sp_read:counter_address_2\)d(3)
..................XX++++++++++++++..............................................
| 5 |(\sp_read:counter_address_0\)
......................XX++++++++++++++..........................................
| 6 |(\sp_read:reset_count_0\)d(4)
..........................++++X+++++++++++......................................
| 7 |(\sp_read:counter_read_stateSBV_0\)
..............................XXXX++++++++++++..................................
| 8 |(\ibus_reader:timeout_1\)d(5)
..................................XX++++++++++++++..............................
| 9 |(\sp_read:counter_address_1\)
......................................XX++++++++++++++..........................
|10 |(\sp_read:counter_address_3\)d(6)
..........................................XX++++++++++++++......................
|11 |(\sp_read:counter_address_5\)
..............................................XX++++++++++++++..................
|12 |(\sp_read:counter_address_6\)d(7)
..................................................XX++++++++++++++..............
|13 |(\sp_read:reset_count_2\)
......................................................XX++++++++++++++..........
|14 |[i/p]
..........................................................++++++++++++++++......
|15 |(sensor_address_7)
................................................................XXXX++++++++++++
________________________________________________________________________________

Total count of outputs placed        =  14 
Total count of unique Product Terms  =  32 
Total Product Terms to be assigned   =  33 
Max Product Terms used / available   =  32 /  80   = 40.1  %


Control Signals for Logic Block M
---------------------------------
CLK pin19: <not used>
CLK pin22: <not used>
CLK pin99: clk
CLK pin102: <not used>
CLK PT      : AH : <not used>
PRESET      : AH : GND
RESET       : AH : reset.CMB 
OE 0        : AH : <not used>
OE 1        : AH : <not used>
OE 2        : AH : <not used>
OE 3        : AH : <not used>



                              Logic Block M
                 ____________________________________________
                 |   |= >\sp_read:re..                  |   |                 
                 |   |= >S_12.CMB                       |   |                 
                 |   |= >sensor_addr..                  |   |                 
                 |   |= >reset.CMB                      |   |                 
                 |   |= >S_4.CMB                        |103|= (sensor_address_1)d(1) 
                 |   |= >\sp_read:co..                  |   |                 
                 |   |= >\sp_read:re..   not used:1079 >|   |                 
                 |   |> not used:737                    |   |                 
                 |   |= >S_11.CMB                       |104|= (\sp_read:reset_count_1\)d(2) 
                 |   |= >S_15.CMB                       |   |                 
                 |   |> not used:740    (\sp_read:counter_address_4\) =|   |                 
                 |   |= >S_17.CMB                       |   |                 
                 |   |= >\sp_read:co..                  |105|= (\sp_read:counter_address_2\)d(3) 
                 |   |= >S_14.CMB                       |   |                 
                 |   |= >\sp_read:co..  (\sp_read:counter_address_0\) =|   |                 
                 |   |= >S_3.CMB                        |   |                 
                 |   |= >S_7.CMB                        |106|= (\sp_read:reset_count_0\)d(4) 
                 |   |= >S_10.CMB                       |   |                 
                 |   |= >\sp_read:co..  (\sp_read:counter_read_stateSBV_0\) =|   |                 
                 |   |= >\sp_read:co..                  |   |                 
                 |   |= >S_18.CMB                       |107|= (\ibus_reader:timeout_1\)d(5) 
                 |   |= >\sp_read:co..                  |   |                 
                 |   |= >S_8.CMB        (\sp_read:counter_address_1\) =|   |                 
                 |   |= >\sp_read:re..                  |   |                 
                 |   |= >\sp_read:co..                  |108|= (\sp_read:counter_address_3\)d(6) 
                 |   |> not used:755                    |   |                 
                 |   |= >S_13.CMB       (\sp_read:counter_address_5\) =|   |                 
                 |   |> not used:757                    |   |                 
                 |   |= >sensor_addr..                  |109|= (\sp_read:counter_address_6\)d(7) 
                 |   |> not used:759                    |   |                 
                 |   |= >S_5.CMB        (\sp_read:reset_count_2\) =|   |                 
                 |   |= >S_16.CMB                       |   |                 
                 |   |= >S_9.CMB                        |110|= d(8)           
                 |   |> not used:763                    |   |                 
                 |   |> not used:764    (sensor_address_7) =|   |                 
                 |   |> not used:765                    |   |                 
                 |   |= >\sp_read:co..                  |   |                 
                 |   |= >S_6.CMB                        |   |                 
                 |   |= >\sp_read:cm..                  |   |                 
                 ____________________________________________


  Information: Macrocell Utilization.

                     Description        Used     Max
                 ______________________________________
                 | I/O Macrocells     |    8  |    8  |
                 | Buried Macrocells  |    7  |    8  |
                 | PIM Input Connects |   31  |   36  |
                 ______________________________________
                                          46  /   52   = 88  %


----------------------------------------------------------------------------
PLD Compiler Software:        C37KFIT.EXE    22/DEC/2000  [v4.02 ] 6.2 IR 27

LOGIC BLOCK N PLACEMENT   (15:40:41)

Messages:


________________________________________________________________________________
          1111111111222222222233333333334444444444555555555566666666667777777777
01234567890123456789012345678901234567890123456789012345678901234567890123456789
________________________________________________________________________________
| 0 |(write_to_bp_ack)d(9)
XX++++++++++++++................................................................
| 1 |(sensor_data_7)
......XX++++++++++++++..........................................................
| 2 |(sensor_data_5)d(10)
..........XX++++++++++++++......................................................
| 3 |(sensor_data_2)
..............XX++++++++++++++..................................................
| 4 |(sensor_data_13)d(11)
..................XX++++++++++++++..............................................
| 5 |(sensor_data_11)
......................XX++++++++++++++..........................................
| 6 |(sensor_data_1)d(12)
..........................XX++++++++++++++......................................
| 7 |(sensor_data_8)
..............................XX++++++++++++++..................................
| 8 |(sensor_data_10)
..................................XX++++++++++++++..............................
| 9 |(sensor_data_12)
......................................XX++++++++++++++..........................
|10 |(sensor_data_14)d(13)
..........................................XX++++++++++++++......................
|11 |(sensor_data_3)
..............................................XX++++++++++++++..................
|12 |(sensor_data_4)d(14)
..................................................XX++++++++++++++..............
|13 |(sensor_data_6)
......................................................XX++++++++++++++..........
|14 |[i/p]
..........................................................++++++++++++++++......
|15 |(sensor_data_9)
................................................................XX++++++++++++++
________________________________________________________________________________

Total count of outputs placed        =  15 
Total count of unique Product Terms  =  30 
Total Product Terms to be assigned   =  30 
Max Product Terms used / available   =  30 /  80   = 37.51 %


Control Signals for Logic Block N
---------------------------------
CLK pin19: <not used>
CLK pin22: <not used>
CLK pin99: clk
CLK pin102: <not used>
CLK PT      : AH : <not used>
PRESET      : AH : GND
RESET       : AH : reset.CMB 
OE 0        : AH : <not used>
OE 1        : AH : <not used>
OE 2        : AH : <not used>
OE 3        : AH : <not used>



                              Logic Block N
                 ____________________________________________
                 |   |= >sensor_data..                  |   |                 
                 |   |= >sensor_data..                  |   |                 
                 |   |= >sensor_data..                  |   |                 
                 |   |= >reset.CMB                      |   |                 
                 |   |= >sensor_data..                  |112|= (write_to_bp_ack)d(9) 
                 |   |= >bpd(11)                        |   |                 
                 |   |= >\bp_io:bp_a..  (sensor_data_7) =|   |                 
                 |   |= >sensor_data..                  |   |                 
                 |   |= >sensor_data..                  |113|= (sensor_data_5)d(10) 
                 |   |= >bpd(5)                         |   |                 
                 |   |= >sensor_data..  (sensor_data_2) =|   |                 
                 |   |= >sensor_data..                  |   |                 
                 |   |= >sensor_data..                  |114|= (sensor_data_13)d(11) 
                 |   |= >sensor_data..                  |   |                 
                 |   |= >bpd(7)         (sensor_data_11) =|   |                 
                 |   |= >bpd(3)                         |   |                 
                 |   |= >\bp_io:bp_a..                  |115|= (sensor_data_1)d(12) 
                 |   |= >sensor_data..                  |   |                 
                 |   |= >sensor_data..  (sensor_data_8) =|   |                 
                 |   |> not used:788                    |   |                 
                 |   |= >sensor_data..                  |116|= (sensor_data_10) 
                 |   |= >bpd(13)                        |   |                 
                 |   |= >bpd(9)         (sensor_data_12) =|   |                 
                 |   |= >bpd(14)                        |   |                 
                 |   |= >bpd(6)                         |117|= (sensor_data_14)d(13) 
                 |   |= >bpd(2)                         |   |                 
                 |   |> not used:795    (sensor_data_3) =|   |                 
                 |   |= >\bp_io:bp_a..                  |   |                 
                 |   |= >bpd(12)                        |118|= (sensor_data_4)d(14) 
                 |   |= >bpd(8)                         |   |                 
                 |   |= >bpd(4)         (sensor_data_6) =|   |                 
                 |   |= >\bp_io:time..                  |   |                 
                 |   |> not used:801                    |119|= d(15)          
                 |   |= >\bp_io:time..                  |   |                 
                 |   |= >bpd(1)         (sensor_data_9) =|   |                 
                 |   |= >bpd(10)                        |   |                 
                 |   |> not used:805                    |   |                 
                 |   |= >\bp_io:time..                  |   |                 
                 |   |= >sensor_data..                  |   |                 
                 ____________________________________________


  Information: Macrocell Utilization.

                     Description        Used     Max
                 ______________________________________
                 | I/O Macrocells     |    8  |    8  |
                 | Buried Macrocells  |    8  |    8  |
                 | PIM Input Connects |   35  |   36  |
                 ______________________________________
                                          51  /   52   = 98  %


----------------------------------------------------------------------------
PLD Compiler Software:        C37KFIT.EXE    22/DEC/2000  [v4.02 ] 6.2 IR 27

LOGIC BLOCK O PLACEMENT   (15:40:41)

Messages:


________________________________________________________________________________
          1111111111222222222233333333334444444444555555555566666666667777777777
01234567890123456789012345678901234567890123456789012345678901234567890123456789
________________________________________________________________________________
| 0>|d(16)
XXXX++++++++++++................................................................
| 1 |(\ibus_writer:timeout_1\)
......XXXX++XX++XX+X++..........................................................
| 2>|d(17)
..........XX++XX++++++++++......................................................
| 3 |(tristate_stateSBV_0)
..............++++X+++++++++++..................................................
| 4>|d(18)
..................++XX++XX++++++++..............................................
| 5 |(\ibus_writer:timeout_0\)
......................XX++XXXX++XX++++..........................................
| 6>|d(19)
..........................++++XX++++XX++++......................................
| 7 |(\ibus_writer:timeout_2\)
..............................++++XX++XXXXXX++..................................
| 8>|d(20)
..................................++++++++++XXXX++..............................
| 9 |UNUSED
......................................++++++++++++++++..........................
|10>|d(21)
..........................................++++++XXXX++++++......................
|11 |(\ibus_writer:timeout_3\)
..............................................++++++XXX+XX++XX..................
|12>|d(22)
..................................................+++++X++X+++++XX..............
|13 |(\ibus_writer:iu_writeSBV_0\)
......................................................+++++X++X+++X+XX..........
|14>|d(23)
..........................................................+++++X++++++X+XX......
|15 |(\ibus_writer:iu_writeSBV_1\)
................................................................++XXXX+X++XX++++
________________________________________________________________________________

Total count of outputs placed        =  15 
Total count of unique Product Terms  =  73 
Total Product Terms to be assigned   =  77 
Max Product Terms used / available   =  74 /  80   = 92.51 %


Control Signals for Logic Block O
---------------------------------
CLK pin19: <not used>
CLK pin22: <not used>
CLK pin99: clk
CLK pin102: <not used>
CLK PT      : AH : <not used>
PRESET      : AH : GND
RESET       : AH : reset.CMB 
OE 0        : AH : <not used>
OE 1        : AH : <not used>
OE 2        : AH : <not used>
OE 3        : AH : <not used>



                              Logic Block O
                 ____________________________________________
                 |   |= >bpd(14).Q                      |   |                 
                 |   |= >bpd(10).Q                      |   |                 
                 |   |= >sensor_data..                  |   |                 
                 |   |= >reset.CMB                      |   |                 
                 |   |= >bpd(11).Q                      |122|= d(16)          
                 |   |= >ao_to_pc_ack                   |   |                 
                 |   |= >d(16).Q        (\ibus_writer:timeout_1\) =|   |                 
                 |   |= >bpd(12).Q                      |   |                 
                 |   |= >\ibus_write..                  |123|= d(17)          
                 |   |= >sensor_data..                  |   |                 
                 |   |= >d(17).Q        (tristate_stateSBV_0) =|   |                 
                 |   |= >sensor_data..                  |   |                 
                 |   |= >bpctrl(4).Q                    |124|= d(18)          
                 |   |= >bpd(15).Q                      |   |                 
                 |   |= >sensor_to_i..  (\ibus_writer:timeout_0\) =|   |                 
                 |   |= >d(20).Q                        |   |                 
                 |   |> not used:824                    |125|= d(19)          
                 |   |= >sensor_data..                  |   |                 
                 |   |= >d(21).Q        (\ibus_writer:timeout_2\) =|   |                 
                 |   |= >sensor_data..                  |   |                 
                 |   |= >bpd(13).Q                      |126|= d(20)          
                 |   |= >sensor_data..                  |   |                 
                 |   |= >d(18).Q         not used:1119 >|   |                 
                 |   |= >from_pc_req.Q                  |   |                 
                 |   |= >d(23).Q                        |127|= d(21)          
                 |   |= >d(19).Q                        |   |                 
                 |   |= >this_chip_s..  (\ibus_writer:timeout_3\) =|   |                 
                 |   |= >d(22).Q                        |   |                 
                 |   |= >\ibus_write..                  |128|= d(22)          
                 |   |= >\ibus_write..                  |   |                 
                 |   |= >sensor_data..  (\ibus_writer:iu_writeSBV_0\) =|   |                 
                 |   |= >sensor_data..                  |   |                 
                 |   |= >\ibus_write..                  |129|= d(23)          
                 |   |= >\ibus_write..                  |   |                 
                 |   |> not used:842    (\ibus_writer:iu_writeSBV_1\) =|   |                 
                 |   |= >\ibus_write..                  |   |                 
                 |   |> not used:844                    |   |                 
                 |   |= >loopback_st..                  |   |                 
                 |   |= >bpctrl(5).Q                    |   |                 
                 ____________________________________________


  Information: Macrocell Utilization.

                     Description        Used     Max
                 ______________________________________
                 | I/O Macrocells     |    8  |    8  |
                 | Buried Macrocells  |    7  |    8  |
                 | PIM Input Connects |   36  |   36  |
                 ______________________________________
                                          51  /   52   = 98  %


----------------------------------------------------------------------------
PLD Compiler Software:        C37KFIT.EXE    22/DEC/2000  [v4.02 ] 6.2 IR 27

LOGIC BLOCK P PLACEMENT   (15:40:41)

Messages:


________________________________________________________________________________
          1111111111222222222233333333334444444444555555555566666666667777777777
01234567890123456789012345678901234567890123456789012345678901234567890123456789
________________________________________________________________________________
| 0>|d(24)
XXXX++++++++++++................................................................
| 1 |UNUSED
......++++++++++++++++..........................................................
| 2>|d(25)
..........XXXX++++++++++++......................................................
| 3 |(\ibus_reader:this_is_a_ctrl_transaction\)
..............XXXX++++++X+++++..................................................
| 4>|d(26)
..................XXXX++++++++++++..............................................
| 5 |(to_pc_ack)
......................XX++++++X+++++++..........................................
| 6>|d(27)
..........................XXXX++++++++++++......................................
| 7 |(address_from_pc_7)
..............................++XX++++++++++++..................................
| 8>|d(28)
..................................XXXX++++++++++++..............................
| 9 |(loopback_state)
......................................X+++++++++++++++..........................
|10>|d(29)
..........................................XXXX++++++++++++......................
|11 |UNUSED
..............................................++++++++++++++++..................
|12>|d(30)
..................................................XXXX++++++++++++..............
|13 |UNUSED
......................................................++++++++++++++++..........
|14>|d(31)
..........................................................XXXX++++++++++++......
|15 |UNUSED
................................................................++++++++++++++++
________________________________________________________________________________

Total count of outputs placed        =  12 
Total count of unique Product Terms  =  43 
Total Product Terms to be assigned   =  43 
Max Product Terms used / available   =  43 /  80   = 53.76 %


Control Signals for Logic Block P
---------------------------------
CLK pin19: <not used>
CLK pin22: <not used>
CLK pin99: clk
CLK pin102: <not used>
CLK PT      : AH : <not used>
PRESET      : AH : GND
RESET       : AH : reset.CMB 
OE 0        : AH : <not used>
OE 1        : AH : <not used>
OE 2        : AH : <not used>
OE 3        : AH : <not used>



                              Logic Block P
                 ____________________________________________
                 |   |= >data_from_p..                  |   |                 
                 |   |= >sensor_data..                  |   |                 
                 |   |= >from_pc_req.Q                  |   |                 
                 |   |= >reset.CMB                      |   |                 
                 |   |= >\ibus_reade..                  |131|= d(24)          
                 |   |= >sensor_data..                  |   |                 
                 |   |= >d(26).Q         not used:1127 >|   |                 
                 |   |= >\ibus_reade..                  |   |                 
                 |   |= >sensor_data..                  |132|= d(25)          
                 |   |= >bpctrl(7).Q                    |   |                 
                 |   |= >d(24).Q        (\ibus_reader:this_is_a_ctrl_transaction\) =|   |                 
                 |   |= >data_from_p..                  |   |                 
                 |   |= >d(28).Q                        |133|= d(26)          
                 |   |= >\ibus_write..                  |   |                 
                 |   |= >sensor_to_i..     (to_pc_ack) =|   |                 
                 |   |= >d(27).Q                        |   |                 
                 |   |> not used:863                    |134|= d(27)          
                 |   |= >bpctrl(8).Q                    |   |                 
                 |   |= >\ibus_reade..  (address_from_pc_7) =|   |                 
                 |   |= >loopback_st..                  |   |                 
                 |   |= >d(29).Q                        |135|= d(28)          
                 |   |= >d(25).Q                        |   |                 
                 |   |= >\ibus_write..  (loopback_state) =|   |                 
                 |   |= >bpctrl(6).Q                    |   |                 
                 |   |= >bpctrl(10).Q                   |136|= d(29)          
                 |   |= >sensor_data..                  |   |                 
                 |   |= >data_from_p..   not used:1137 >|   |                 
                 |   |= >sensor_data..                  |   |                 
                 |   |= >d(30).Q                        |137|= d(30)          
                 |   |= >\ibus_reade..                  |   |                 
                 |   |> not used:877     not used:1139 >|   |                 
                 |   |= >bpctrl(11).Q                   |   |                 
                 |   |= >d(31).Q                        |138|= d(31)          
                 |   |> not used:880                    |   |                 
                 |   |= >sensor_data..   not used:1141 >|   |                 
                 |   |= >sensor_data..                  |   |                 
                 |   |= >address_fro..                  |   |                 
                 |   |= >sensor_data..                  |   |                 
                 |   |= >bpctrl(5).Q                    |   |                 
                 ____________________________________________


  Information: Macrocell Utilization.

                     Description        Used     Max
                 ______________________________________
                 | I/O Macrocells     |    8  |    8  |
                 | Buried Macrocells  |    4  |    8  |
                 | PIM Input Connects |   36  |   36  |
                 ______________________________________
                                          48  /   52   = 92  %


----------------------------------------------------------------------------
PLD Compiler Software:        C37KFIT.EXE    22/DEC/2000  [v4.02 ] 6.2 IR 27

PINOUT INFORMATION   (15:40:41)


Device:  cy37256p160
Package: cy37256p160-125ac

                     1  :  GND
                     2  :  (S_13)
                >    3  :  bpctrl_h_tristate
                >    4  :  bpd_l_tristate
                >    5  :  bpctrl_l_dir
                     6  :  (S_10)
                >    7  :  bpctrl_l_tristate
                >    8  :  bpctrl_h_dir
                >    9  :  bpd_l_dir
                    10  :  GND
                >   11  :  bpctrl(0)
                >   12  :  bpctrl(1)
                >   13  :  bpctrl(2)
                >   14  :  bpctrl(3)
                >   15  :  bpctrl(4)
                >   16  :  bpctrl(5)
                >   17  :  bpctrl(6)
                >   18  :  bpctrl(7)
                >   19  :  slow
                    20  :  VCC
                    21  :  GND
                >   22  :  fast
                >   23  :  bpctrl(8)
                    24  :  (bp_start_address_1)
                >   25  :  bpctrl(10)
                >   26  :  bpctrl(11)
                    27  :  (address_from_pc_2)
                    28  :  (address_from_pc_4)
                    29  :  (bp_start_address_0)
                    30  :  (bp_start_address_4)
                    31  :  GND
                >   32  :  bpaddr(0)
                >   33  :  bpaddr(1)
                >   34  :  bpaddr(2)
                >   35  :  bpaddr(3)
                >   36  :  bpaddr(4)
                >   37  :  bpaddr(5)
                >   38  :  bpaddr(6)
                >   39  :  bpaddr(7)
                    40  :  VCC
                    41  :  GND
                >   42  :  bpd_h_dir
                >   43  :  bpd_h_tristate
                >   44  :  bpaddr_tristate
                >   45  :  bpaddr_dir
                    46  :  (\bp_io:bp_access_stateSBV_2\)
                >   47  :  led1
                >   48  :  led2
                >   49  :  led3
                    50  :  GND
                    51  :  (S_17)
                    52  :  (sensor_data_15)
                    53  :  (sensor_address_5)
                    54  :  (\sp_read:counter_read_stateSBV_3\)
                >   55  :  (\sp_read:counter_read_stateSBV_1\)hva_chassis_en_l
                    56  :  (sensor_address_6)
                    57  :  (sensor_address_4)
                    58  :  Not Used
                    59  :  Not Used
                    60  :  VCC
                    61  :  GND
                    62  :  VCC
                    63  :  (\ibus_reader:timeout_2\)
                    64  :  (S_18)
                    65  :  (from_pc_req)
                >   66  :  sinphase_zeros
                    67  :  Not Used
                    68  :  Not Used
                    69  :  (\ibus_reader:timeout_3\)
                    70  :  Not Used
                    71  :  GND
                    72  :  (S_15)
                    73  :  Not Used
                    74  :  Not Used
                    75  :  Not Used
                    76  :  Not Used
                    77  :  Not Used
                >   78  :  reset
                    79  :  Not Used
                    80  :  VCC
                    81  :  GND
                    82  :  (S_7)
                    83  :  Not Used
                    84  :  Not Used
                    85  :  Not Used
                    86  :  Not Used
                    87  :  Not Used
                    88  :  (S_6)
                    89  :  Not Used
                    90  :  GND
                    91  :  (data_from_pc_14)
                >   92  :  (bp_end_address_7)ao_to_pc_ack
                >   93  :  ao_to_pc_strobe
                >   94  :  ao_from_pc_ack
                >   95  :  (bp_end_address_2)ao_from_pc_strobe
                    96  :  (bp_end_address_4)
                    97  :  (bp_end_address_6)
                >   98  :  (data_from_pc_13)d(0)
                >   99  :  clk
                   100  :  VCC
                   101  :  GND
                   102  :  Not Used
                >  103  :  (sensor_address_1)d(1)
                >  104  :  (\sp_read:reset_count_1\)d(2)
                >  105  :  (\sp_read:counter_address_2\)d(3)
                >  106  :  (\sp_read:reset_count_0\)d(4)
                >  107  :  (\ibus_reader:timeout_1\)d(5)
                >  108  :  (\sp_read:counter_address_3\)d(6)
                >  109  :  (\sp_read:counter_address_6\)d(7)
                >  110  :  d(8)
                   111  :  GND
                >  112  :  (write_to_bp_ack)d(9)
                >  113  :  (sensor_data_5)d(10)
                >  114  :  (sensor_data_13)d(11)
                >  115  :  (sensor_data_1)d(12)
                   116  :  (sensor_data_10)
                >  117  :  (sensor_data_14)d(13)
                >  118  :  (sensor_data_4)d(14)
                >  119  :  d(15)
                   120  :  VCC
                   121  :  GND
                >  122  :  d(16)
                >  123  :  d(17)
                >  124  :  d(18)
                >  125  :  d(19)
                >  126  :  d(20)
                >  127  :  d(21)
                >  128  :  d(22)
                >  129  :  d(23)
                   130  :  GND
                >  131  :  d(24)
                >  132  :  d(25)
                >  133  :  d(26)
                >  134  :  d(27)
                >  135  :  d(28)
                >  136  :  d(29)
                >  137  :  d(30)
                >  138  :  d(31)
                   139  :  Not Used
                   140  :  VCC
                   141  :  GND
                   142  :  VCC
                >  143  :  bpd(0)
                >  144  :  bpd(1)
                >  145  :  bpd(2)
                >  146  :  bpd(3)
                >  147  :  bpd(4)
                >  148  :  bpd(5)
                >  149  :  bpd(6)
                >  150  :  bpd(7)
                   151  :  GND
                >  152  :  bpd(8)
                >  153  :  bpd(9)
                >  154  :  bpd(10)
                >  155  :  bpd(11)
                >  156  :  bpd(12)
                >  157  :  bpd(13)
                >  158  :  bpd(14)
                >  159  :  bpd(15)
                   160  :  VCC

----------------------------------------------------------------------------
PLD Compiler Software:        C37KFIT.EXE    22/DEC/2000  [v4.02 ] 6.2 IR 27

RESOURCE UTILIZATION (15:40:41)



  Information: Macrocell Utilization.

                     Description        Used     Max
                 ______________________________________
                 | Dedicated Inputs   |    0  |    1  |
                 | Clock/Inputs       |    3  |    4  |
                 | I/O Macrocells     |  112  |  128  |
                 | Buried Macrocells  |   74  |  128  |
                 | PIM Input Connects |  434  |  624  |
                 ______________________________________
                                         623  /  885   = 70  %



                                      Required     Max (Available)
          CLOCK/LATCH ENABLE signals     1           20
          Input REG/LATCH signals        0          133
          Input PIN signals              3            5
          Input PINs using I/O cells    13           13
          Output PIN signals            74          115


          Total PIN signals             90          133
          Macrocells Used              173          256
          Unique Product Terms         739         1280



----------------------------------------------------------------------------
PLD Compiler Software:        C37KFIT.EXE    22/DEC/2000  [v4.02 ] 6.2 IR 27

PRESET/RESET AND OUTPUT ENABLE COMBINATIONS

PRESET: GND
RESET : reset.CMB 
CLOCK PT : NULL
Used by Logic Blocks: BDEFGHIKLMNOP
Total unique inputs =  190 
count of output equations =  141 
==>OE: bpctrl(0).Q 
   Used by Logic Blocks: BDE
   count of OE equations =  13 
==>OE: GND or VCC
   count of OE equations =  127 
==>OE: /il_tristate.Q 
   Used by Logic Blocks: L
   count of OE equations =  1 


PRESET: NONE-COMBINATORIAL
RESET : NONE-COMBINATORIAL
CLOCK PT : NULL
Total unique inputs =  47 
count of output equations =  31 
==>OE: GND or VCC
   count of OE equations =  31 


PRESET: fast * sinphase_zeros * /slow 
RESET : fast * /sinphase_zeros * /slow 
CLOCK PT : NULL
Used by Logic Blocks: J
Total unique inputs =  3 
count of output equations =  1 
==>OE: GND or VCC
   count of OE equations =  1 

----------------------------------------------------------------------------
PLD Compiler Software:        C37KFIT.EXE    22/DEC/2000  [v4.02 ] 6.2 IR 27

JEDEC ASSEMBLE             (15:40:41)

Messages:
  Information: Processing JEDEC for Logic Block 1.
  Information: Processing JEDEC for Logic Block 2.
  Information: Processing JEDEC for Logic Block 3.
  Information: Processing JEDEC for Logic Block 4.
  Information: Processing JEDEC for Logic Block 5.
  Information: Processing JEDEC for Logic Block 6.
  Information: Processing JEDEC for Logic Block 7.
  Information: Processing JEDEC for Logic Block 8.
  Information: Processing JEDEC for Logic Block 9.
  Information: Processing JEDEC for Logic Block 10.
  Information: Processing JEDEC for Logic Block 11.
  Information: Processing JEDEC for Logic Block 12.
  Information: Processing JEDEC for Logic Block 13.
  Information: Processing JEDEC for Logic Block 14.
  Information: Processing JEDEC for Logic Block 15.
  Information: Processing JEDEC for Logic Block 16.
  Information: JEDEC output file 'pc_remote_bus.pin' created.
  Information: JEDEC output file 'pc_remote_bus.jed' created.


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully at 15:40:41
----------------------------------------------------------------------------
PLD Compiler Software:        C37KFIT.EXE    22/DEC/2000  [v4.02 ] 6.2 IR 27

TIMING PATH ANALYSIS       (15:40:41) using Package: cy37256p160-125ac

Messages:

----------------------------------------------------------------------------
Signal Name | Delay Type  |   tmax   | Path Description
----------------------------------------------------------------------------
cmb::bpctrl_h_tristate[3]
inp::bpd_h_tristate.Q
              tCO             12.5 ns    1 pass
----------------------------------------------------------------------------
cmb::bpd_l_tristate[4]
inp::bpd_h_tristate.Q
              tCO             12.5 ns    1 pass
----------------------------------------------------------------------------
cmb::bpctrl_l_dir[5]
----------------------------------------------------------------------------
cmb::bpctrl_l_tristate[7]
----------------------------------------------------------------------------
cmb::bpctrl_h_dir[8]
----------------------------------------------------------------------------
cmb::bpd_l_dir[9]
inp::bpctrl(0).Q
              tCO             12.5 ns    1 pass
----------------------------------------------------------------------------
reg::bpctrl(0)[11]
inp::\bp_io:bp_access_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::bpd_h_dir
              tCO             12.5 ns    1 pass
----------------------------------------------------------------------------
cmb::bpctrl(1)[12]
inp::sinphase_zeros
              tPD             8.5 ns     1 pass
----------------------------------------------------------------------------
reg::bpctrl(2)[13]
inp::\bp_io:bp_access_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::bpctrl(2)
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::bpctrl(3)[14]
inp::\sp_read:counter_read_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::bpctrl(3)
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::bpctrl(4)[15]
inp::ao_from_pc_strobe
---->ao_from_pc_strobe
              tS              4.0 ns     1 pass
inp::\ibus_reader:il_read_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::bpctrl(4)
              tCO             6.5 ns   
inp::bpctrl(0).Q
              tER             16.5 ns    1 pass
----------------------------------------------------------------------------
reg::bpctrl(5)[16]
inp::ao_from_pc_strobe
---->ao_from_pc_strobe
              tS              4.0 ns     1 pass
inp::\ibus_reader:il_read_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::bpctrl(5)
              tCO             6.5 ns   
inp::bpctrl(0).Q
              tER             16.5 ns    1 pass
----------------------------------------------------------------------------
reg::bpctrl(6)[17]
inp::ao_from_pc_strobe
---->ao_from_pc_strobe
              tS              4.0 ns     1 pass
inp::\ibus_reader:il_read_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::bpctrl(6)
              tCO             6.5 ns   
inp::bpctrl(0).Q
              tER             16.5 ns    1 pass
----------------------------------------------------------------------------
reg::bpctrl(7)[18]
inp::ao_from_pc_strobe
---->ao_from_pc_strobe
              tS              4.0 ns     1 pass
inp::\ibus_reader:il_read_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::bpctrl(7)
              tCO             6.5 ns   
inp::bpctrl(0).Q
              tER             16.5 ns    1 pass
----------------------------------------------------------------------------
reg::bpctrl(8)[23]
inp::ao_from_pc_strobe
---->ao_from_pc_strobe
              tS              4.0 ns     1 pass
inp::\ibus_reader:il_read_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::bpctrl(8)
              tCO             6.5 ns   
inp::bpctrl(0).Q
              tER             16.5 ns    1 pass
----------------------------------------------------------------------------
reg::(bp_start_address_1)[24]
inp::\ibus_reader:il_read_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::bp_start_address_1
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::bpctrl(10)[25]
inp::ao_from_pc_strobe
---->ao_from_pc_strobe
              tS              4.0 ns     1 pass
inp::\ibus_reader:il_read_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::bpctrl(10)
              tCO             6.5 ns   
inp::bpctrl(0).Q
              tER             16.5 ns    1 pass
----------------------------------------------------------------------------
reg::bpctrl(11)[26]
inp::ao_from_pc_strobe
---->ao_from_pc_strobe
              tS              4.0 ns     1 pass
inp::\ibus_reader:il_read_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::bpctrl(11)
              tCO             6.5 ns   
inp::bpctrl(0).Q
              tER             16.5 ns    1 pass
----------------------------------------------------------------------------
reg::(address_from_pc_2)[27]
inp::\ibus_reader:il_read_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::address_from_pc_2
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(address_from_pc_4)[28]
inp::\ibus_reader:il_read_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::address_from_pc_4
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(bp_start_address_0)[29]
inp::\ibus_reader:il_read_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::bp_start_address_0
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(bp_start_address_4)[30]
inp::\ibus_reader:il_read_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::bp_start_address_4
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::bpaddr(0)[32]
inp::\bp_io:bp_access_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::bpaddr(0)
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::bpaddr(1)[33]
inp::\bp_io:bp_access_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::bpaddr(1)
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::bpaddr(2)[34]
inp::\bp_io:bp_access_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::bpaddr(2)
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::bpaddr(3)[35]
inp::\bp_io:bp_access_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::bpaddr(3)
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::bpaddr(4)[36]
inp::\bp_io:bp_access_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::bpaddr(4)
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::bpaddr(5)[37]
inp::\bp_io:bp_access_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::bpaddr(5)
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::bpaddr(6)[38]
inp::\bp_io:bp_access_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::bpaddr(6)
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::bpaddr(7)[39]
inp::\bp_io:bp_access_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::bpaddr(7)
              tCO             6.5 ns   
----------------------------------------------------------------------------
cmb::bpd_h_dir[42]
inp::bpctrl(0).Q
              tCO             12.5 ns    1 pass
----------------------------------------------------------------------------
reg::bpd_h_tristate[43]
inp::\bp_io:bp_access_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::bpctrl_h_tristate
              tCO             12.5 ns    1 pass
----------------------------------------------------------------------------
reg::bpaddr_tristate[44]
inp::\bp_io:bp_access_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::bpaddr_tristate
              tCO             6.5 ns   
----------------------------------------------------------------------------
cmb::bpaddr_dir[45]
----------------------------------------------------------------------------
reg::(\bp_io:bp_access_stateSBV_2\)[46]
inp::\bp_io:bp_access_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::\bp_io:bp_access_stateSBV_2\
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::led1[47]
inp::\bp_io:bp_access_stateSBV_1\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::led1
              tCO             6.5 ns   
----------------------------------------------------------------------------
cmb::led2[48]
inp::fast
              tPD             10.0 ns    1 pass
----------------------------------------------------------------------------
cmb::led3[49]
inp::slow
              tPD             10.0 ns    1 pass
----------------------------------------------------------------------------
reg::(sensor_data_15)[52]
inp::sinphase_zeros
              tS              4.0 ns     1 pass
inp::\sp_read:counter_read_stateSBV_1\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::sensor_data_15
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(sensor_address_5)[53]
inp::\sp_read:counter_address_3\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::sensor_address_5
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(\sp_read:counter_read_stateSBV_3\)[54]
inp::hva_chassis_en_l
---->hva_chassis_en_l
              tS              4.0 ns     1 pass
inp::\sp_read:counter_read_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::\sp_read:counter_read_stateSBV_3\
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(\sp_read:counter_read_stateSBV_1\)hva_chassis_en_l[55]
inp::\sp_read:counter_read_stateSBV_1\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::\sp_read:counter_read_stateSBV_1\
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(sensor_address_6)[56]
inp::\sp_read:counter_address_3\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::sensor_address_6
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(sensor_address_4)[57]
inp::\sp_read:counter_address_3\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::sensor_address_4
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(\ibus_reader:timeout_2\)[63]
inp::ao_from_pc_strobe
---->ao_from_pc_strobe
              tS              4.0 ns     1 pass
inp::\ibus_reader:il_read_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::\ibus_reader:timeout_2\
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(from_pc_req)[65]
inp::\ibus_reader:il_read_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::from_pc_req
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(\ibus_reader:timeout_3\)[69]
inp::ao_from_pc_strobe
---->ao_from_pc_strobe
              tS              4.0 ns     1 pass
inp::\ibus_reader:il_read_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::\ibus_reader:timeout_3\
              tCO             6.5 ns   
----------------------------------------------------------------------------
cmb::reset[78]
inp::fast
              tPD             10.0 ns    1 pass
----------------------------------------------------------------------------
reg::(data_from_pc_14)[91]
inp::ao_from_pc_strobe
---->ao_from_pc_strobe
              tS              4.0 ns     1 pass
inp::\ibus_reader:il_read_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::data_from_pc_14
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(bp_end_address_7)ao_to_pc_ack[92]
inp::\ibus_reader:il_read_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::bp_end_address_7
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::ao_to_pc_strobe[93]
inp::ao_to_pc_ack
---->ao_to_pc_ack
              tS              4.0 ns     1 pass
inp::\ibus_writer:iu_writeSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::ao_to_pc_strobe
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::ao_from_pc_ack[94]
inp::\ibus_reader:il_read_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::ao_from_pc_ack
              tCO             6.5 ns   
inp::il_tristate.Q
              tER             16.5 ns    1 pass
----------------------------------------------------------------------------
reg::(bp_end_address_2)ao_from_pc_strobe[95]
inp::\ibus_reader:il_read_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::bp_end_address_2
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(bp_end_address_4)[96]
inp::\ibus_reader:il_read_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::bp_end_address_4
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(bp_end_address_6)[97]
inp::\ibus_reader:il_read_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::bp_end_address_6
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(data_from_pc_13)d(0)[98]
inp::ao_from_pc_strobe
---->ao_from_pc_strobe
              tS              4.0 ns     1 pass
inp::\ibus_reader:il_read_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::data_from_pc_13
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(sensor_address_1)d(1)[103]
inp::\sp_read:counter_address_1\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::sensor_address_1
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(\sp_read:reset_count_1\)d(2)[104]
inp::\sp_read:counter_read_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::\sp_read:reset_count_1\
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(\sp_read:counter_address_2\)d(3)[105]
inp::hva_chassis_en_l
---->hva_chassis_en_l
---->S_12
              tS              10.0 ns    2 passes
inp::\sp_read:counter_read_stateSBV_0\.Q
---->S_12
              tSCS            14.0 ns    2 passes
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::\sp_read:counter_address_2\
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(\sp_read:reset_count_0\)d(4)[106]
inp::\sp_read:counter_read_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::\sp_read:reset_count_0\
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(\ibus_reader:timeout_1\)d(5)[107]
inp::ao_from_pc_strobe
---->ao_from_pc_strobe
---->S_18
              tS              10.0 ns    2 passes
inp::\ibus_reader:il_read_stateSBV_2\.Q
---->S_18
              tSCS            14.0 ns    2 passes
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::\ibus_reader:timeout_1\
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(\sp_read:counter_address_3\)d(6)[108]
inp::hva_chassis_en_l
---->hva_chassis_en_l
---->S_9
              tS              10.0 ns    2 passes
inp::\sp_read:counter_address_3\.Q
---->S_9
              tSCS            14.0 ns    2 passes
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::\sp_read:counter_address_3\
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(\sp_read:counter_address_6\)d(7)[109]
inp::hva_chassis_en_l
---->hva_chassis_en_l
---->S_4
              tS              10.0 ns    2 passes
inp::\sp_read:counter_address_0\.Q
---->S_4
              tSCS            14.0 ns    2 passes
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::\sp_read:counter_address_6\
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(write_to_bp_ack)d(9)[112]
inp::\bp_io:bp_access_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::write_to_bp_ack
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(sensor_data_5)d(10)[113]
inp::bpd(5)
              tS              4.0 ns     1 pass
inp::\bp_io:bp_access_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::sensor_data_5
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(sensor_data_13)d(11)[114]
inp::bpd(13)
              tS              4.0 ns     1 pass
inp::\bp_io:bp_access_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::sensor_data_13
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(sensor_data_1)d(12)[115]
inp::bpd(1)
              tS              4.0 ns     1 pass
inp::\bp_io:bp_access_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::sensor_data_1
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(sensor_data_10)[116]
inp::bpd(10)
              tS              4.0 ns     1 pass
inp::\bp_io:bp_access_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::sensor_data_10
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(sensor_data_14)d(13)[117]
inp::bpd(14)
              tS              4.0 ns     1 pass
inp::\bp_io:bp_access_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::sensor_data_14
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(sensor_data_4)d(14)[118]
inp::bpd(4)
              tS              4.0 ns     1 pass
inp::\bp_io:bp_access_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::sensor_data_4
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::d(16)[122]
inp::\ibus_writer:iu_writeSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::d(16)
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::d(17)[123]
inp::\ibus_writer:iu_writeSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::d(17)
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::d(18)[124]
inp::\ibus_writer:iu_writeSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::d(18)
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::d(19)[125]
inp::\ibus_writer:iu_writeSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::d(19)
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::d(20)[126]
inp::\ibus_writer:iu_writeSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::d(20)
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::d(21)[127]
inp::\ibus_writer:iu_writeSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::d(21)
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::d(22)[128]
inp::\ibus_writer:iu_writeSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::d(22)
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::d(23)[129]
inp::\ibus_writer:iu_writeSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::d(23)
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::d(24)[131]
inp::\ibus_writer:iu_writeSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::d(24)
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::d(25)[132]
inp::\ibus_writer:iu_writeSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::d(25)
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::d(26)[133]
inp::\ibus_writer:iu_writeSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::d(26)
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::d(27)[134]
inp::\ibus_writer:iu_writeSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::d(27)
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::d(28)[135]
inp::\ibus_writer:iu_writeSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::d(28)
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::d(29)[136]
inp::\ibus_writer:iu_writeSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::d(29)
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::d(30)[137]
inp::\ibus_writer:iu_writeSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::d(30)
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::d(31)[138]
inp::\ibus_writer:iu_writeSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::d(31)
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::bpd(10)[154]
inp::ao_from_pc_strobe
---->ao_from_pc_strobe
              tS              4.0 ns     1 pass
inp::\ibus_reader:il_read_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::bpd(10)
              tCO             6.5 ns   
inp::bpctrl(0).Q
              tER             16.5 ns    1 pass
----------------------------------------------------------------------------
reg::bpd(11)[155]
inp::ao_from_pc_strobe
---->ao_from_pc_strobe
              tS              4.0 ns     1 pass
inp::\ibus_reader:il_read_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::bpd(11)
              tCO             6.5 ns   
inp::bpctrl(0).Q
              tER             16.5 ns    1 pass
----------------------------------------------------------------------------
reg::bpd(12)[156]
inp::ao_from_pc_strobe
---->ao_from_pc_strobe
              tS              4.0 ns     1 pass
inp::\ibus_reader:il_read_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::bpd(12)
              tCO             6.5 ns   
inp::bpctrl(0).Q
              tER             16.5 ns    1 pass
----------------------------------------------------------------------------
reg::bpd(13)[157]
inp::ao_from_pc_strobe
---->ao_from_pc_strobe
              tS              4.0 ns     1 pass
inp::\ibus_reader:il_read_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::bpd(13)
              tCO             6.5 ns   
inp::bpctrl(0).Q
              tER             16.5 ns    1 pass
----------------------------------------------------------------------------
reg::bpd(14)[158]
inp::ao_from_pc_strobe
---->ao_from_pc_strobe
              tS              4.0 ns     1 pass
inp::\ibus_reader:il_read_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::bpd(14)
              tCO             6.5 ns   
inp::bpctrl(0).Q
              tER             16.5 ns    1 pass
----------------------------------------------------------------------------
reg::bpd(15)[159]
inp::ao_from_pc_strobe
---->ao_from_pc_strobe
              tS              4.0 ns     1 pass
inp::\ibus_reader:il_read_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::bpd(15)
              tCO             6.5 ns   
inp::bpctrl(0).Q
              tER             16.5 ns    1 pass
----------------------------------------------------------------------------
reg::(bp_start_address_3)[951]
inp::\ibus_reader:il_read_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::bp_start_address_3
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(this_chip_selected)[953]
inp::\ibus_reader:il_read_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::this_chip_selected
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(address_from_pc_0)[955]
inp::\ibus_reader:il_read_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::address_from_pc_0
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(address_from_pc_1)[957]
inp::\ibus_reader:il_read_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::address_from_pc_1
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(address_from_pc_3)[959]
inp::\ibus_reader:il_read_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::address_from_pc_3
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(address_from_pc_5)[961]
inp::\ibus_reader:il_read_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::address_from_pc_5
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(bp_start_address_2)[963]
inp::\ibus_reader:il_read_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::bp_start_address_2
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(bp_start_address_5)[965]
inp::\ibus_reader:il_read_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::bp_start_address_5
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(\bp_io:timeout_1\)[983]
inp::\bp_io:bp_access_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::\bp_io:timeout_1\
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(sensor_data_0)[985]
inp::bpd(0)
              tS              4.0 ns     1 pass
inp::\bp_io:bp_access_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::sensor_data_0
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(\bp_io:timeout_0\)[987]
inp::\bp_io:bp_access_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::\bp_io:timeout_0\
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(\bp_io:bp_access_stateSBV_1\)[989]
inp::\bp_io:bp_access_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::\bp_io:bp_access_stateSBV_1\
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(\bp_io:bp_access_stateSBV_0\)[991]
inp::\bp_io:bp_access_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::\bp_io:bp_access_stateSBV_0\
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(\bp_io:timeout_2\)[993]
inp::\bp_io:bp_access_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::\bp_io:timeout_2\
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(\sp_read:counter_address_7\)[995]
inp::hva_chassis_en_l
---->hva_chassis_en_l
---->S_2
              tS              10.0 ns    2 passes
inp::\sp_read:counter_address_0\.Q
---->S_2
              tSCS            14.0 ns    2 passes
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::\sp_read:counter_address_7\
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(sensor_to_bp_read_ack)[997]
inp::\bp_io:bp_access_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::sensor_to_bp_read_ack
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(sensor_to_ibus_req)[1001]
inp::\sp_read:counter_read_stateSBV_1\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::sensor_to_ibus_req
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(sensor_address_0)[1003]
inp::\sp_read:counter_address_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::sensor_address_0
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(sensor_address_2)[1007]
inp::\sp_read:counter_address_2\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::sensor_address_2
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(sensor_address_3)[1009]
inp::\sp_read:counter_address_3\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::sensor_address_3
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(sensor_to_bp_read_req)[1011]
inp::\sp_read:counter_read_stateSBV_1\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::sensor_to_bp_read_req
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(\ibus_reader:il_read_stateSBV_0\)[1013]
inp::ao_from_pc_strobe
---->ao_from_pc_strobe
              tS              4.0 ns     1 pass
inp::\ibus_reader:il_read_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::\ibus_reader:il_read_stateSBV_0\
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(il_tristate)[1015]
inp::il_tristate.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::il_tristate
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(\ibus_reader:il_read_stateSBV_2\)[1021]
inp::ao_from_pc_strobe
---->ao_from_pc_strobe
              tS              4.0 ns     1 pass
inp::\ibus_reader:il_read_stateSBV_1\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::\ibus_reader:il_read_stateSBV_2\
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(\ibus_reader:il_read_stateSBV_1\)[1023]
inp::ao_from_pc_strobe
---->ao_from_pc_strobe
              tS              4.0 ns     1 pass
inp::\ibus_reader:il_read_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::\ibus_reader:il_read_stateSBV_1\
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(\ibus_reader:timeout_0\)[1029]
inp::ao_from_pc_strobe
---->ao_from_pc_strobe
              tS              4.0 ns     1 pass
inp::\ibus_reader:il_read_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::\ibus_reader:timeout_0\
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(\sp_read:old_phase\)[1031]
inp::sinphase_zeros
              tS              4.0 ns     1 pass
inp::fast
              tPO             15.0 ns    1 pass
inp::fast
              tRO             15.0 ns    1 pass
out::\sp_read:old_phase\
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(\sp_read:counter_read_stateSBV_2\)[1057]
inp::hva_chassis_en_l
---->hva_chassis_en_l
              tS              4.0 ns     1 pass
inp::\sp_read:counter_address_0\.Q
---->\sp_read:cmp_vv_us_MODGEN_10\
              tSCS            14.0 ns    2 passes
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::\sp_read:counter_read_stateSBV_2\
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(bp_start_address_7)[1063]
inp::\ibus_reader:il_read_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::bp_start_address_7
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(address_from_pc_6)[1065]
inp::\ibus_reader:il_read_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::address_from_pc_6
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(bp_end_address_0)[1067]
inp::\ibus_reader:il_read_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::bp_end_address_0
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(bp_end_address_1)[1069]
inp::\ibus_reader:il_read_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::bp_end_address_1
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(bp_end_address_3)[1071]
inp::\ibus_reader:il_read_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::bp_end_address_3
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(bp_end_address_5)[1073]
inp::\ibus_reader:il_read_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::bp_end_address_5
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(bp_start_address_6)[1075]
inp::\ibus_reader:il_read_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::bp_start_address_6
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(data_from_pc_15)[1077]
inp::ao_from_pc_strobe
---->ao_from_pc_strobe
              tS              4.0 ns     1 pass
inp::\ibus_reader:il_read_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::data_from_pc_15
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(\sp_read:counter_address_4\)[1081]
inp::hva_chassis_en_l
---->hva_chassis_en_l
---->S_8
              tS              10.0 ns    2 passes
inp::\sp_read:counter_read_stateSBV_0\.Q
---->S_8
              tSCS            14.0 ns    2 passes
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::\sp_read:counter_address_4\
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(\sp_read:counter_address_0\)[1083]
inp::hva_chassis_en_l
---->hva_chassis_en_l
---->S_16
              tS              10.0 ns    2 passes
inp::\sp_read:counter_read_stateSBV_0\.Q
---->S_16
              tSCS            14.0 ns    2 passes
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::\sp_read:counter_address_0\
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(\sp_read:counter_read_stateSBV_0\)[1085]
inp::\sp_read:counter_address_0\.Q
---->\sp_read:cmp_vv_us_MODGEN_10\
              tSCS            14.0 ns    2 passes
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::\sp_read:counter_read_stateSBV_0\
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(\sp_read:counter_address_1\)[1087]
inp::hva_chassis_en_l
---->hva_chassis_en_l
---->S_14
              tS              10.0 ns    2 passes
inp::\sp_read:counter_read_stateSBV_0\.Q
---->S_14
              tSCS            14.0 ns    2 passes
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::\sp_read:counter_address_1\
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(\sp_read:counter_address_5\)[1089]
inp::hva_chassis_en_l
---->hva_chassis_en_l
---->S_6
              tS              10.0 ns    2 passes
inp::\sp_read:counter_address_0\.Q
---->S_6
              tSCS            14.0 ns    2 passes
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::\sp_read:counter_address_5\
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(\sp_read:reset_count_2\)[1091]
inp::\sp_read:counter_read_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::\sp_read:reset_count_2\
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(sensor_address_7)[1093]
inp::\sp_read:counter_address_3\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::sensor_address_7
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(sensor_data_7)[1095]
inp::bpd(7)
              tS              4.0 ns     1 pass
inp::\bp_io:bp_access_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::sensor_data_7
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(sensor_data_2)[1097]
inp::bpd(2)
              tS              4.0 ns     1 pass
inp::\bp_io:bp_access_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::sensor_data_2
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(sensor_data_11)[1099]
inp::bpd(11)
              tS              4.0 ns     1 pass
inp::\bp_io:bp_access_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::sensor_data_11
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(sensor_data_8)[1101]
inp::bpd(8)
              tS              4.0 ns     1 pass
inp::\bp_io:bp_access_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::sensor_data_8
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(sensor_data_12)[1103]
inp::bpd(12)
              tS              4.0 ns     1 pass
inp::\bp_io:bp_access_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::sensor_data_12
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(sensor_data_3)[1105]
inp::bpd(3)
              tS              4.0 ns     1 pass
inp::\bp_io:bp_access_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::sensor_data_3
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(sensor_data_6)[1107]
inp::bpd(6)
              tS              4.0 ns     1 pass
inp::\bp_io:bp_access_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::sensor_data_6
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(sensor_data_9)[1109]
inp::bpd(9)
              tS              4.0 ns     1 pass
inp::\bp_io:bp_access_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::sensor_data_9
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(\ibus_writer:timeout_1\)[1111]
inp::ao_to_pc_ack
---->ao_to_pc_ack
              tS              4.0 ns     1 pass
inp::\ibus_writer:iu_writeSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::\ibus_writer:timeout_1\
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(tristate_stateSBV_0)[1113]
inp::this_chip_selected.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::tristate_stateSBV_0
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(\ibus_writer:timeout_0\)[1115]
inp::ao_to_pc_ack
---->ao_to_pc_ack
              tS              4.0 ns     1 pass
inp::\ibus_writer:iu_writeSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::\ibus_writer:timeout_0\
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(\ibus_writer:timeout_2\)[1117]
inp::ao_to_pc_ack
---->ao_to_pc_ack
              tS              4.0 ns     1 pass
inp::\ibus_writer:iu_writeSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::\ibus_writer:timeout_2\
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(\ibus_writer:timeout_3\)[1121]
inp::ao_to_pc_ack
---->ao_to_pc_ack
              tS              4.0 ns     1 pass
inp::\ibus_writer:iu_writeSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::\ibus_writer:timeout_3\
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(\ibus_writer:iu_writeSBV_0\)[1123]
inp::ao_to_pc_ack
---->ao_to_pc_ack
              tS              4.0 ns     1 pass
inp::\ibus_writer:iu_writeSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::\ibus_writer:iu_writeSBV_0\
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(\ibus_writer:iu_writeSBV_1\)[1125]
inp::ao_to_pc_ack
---->ao_to_pc_ack
              tS              4.0 ns     1 pass
inp::\ibus_writer:iu_writeSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::\ibus_writer:iu_writeSBV_1\
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(\ibus_reader:this_is_a_ctrl_transaction\)[1129]
inp::\ibus_reader:il_read_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::\ibus_reader:this_is_a_ctrl_transaction\
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(to_pc_ack)[1131]
inp::\ibus_writer:iu_writeSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::to_pc_ack
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(address_from_pc_7)[1133]
inp::\ibus_reader:il_read_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::address_from_pc_7
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(loopback_state)[1135]
inp::\ibus_reader:il_read_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::loopback_state
              tCO             6.5 ns   
----------------------------------------------------------------------------

Worst Case Path Summary
-----------------------

                    tPD = 10.0 ns for led2 
                     tS = 10.0 ns for \sp_read:counter_address_2\.D 
                   tSCS = 14.0 ns for \sp_read:counter_address_2\.D  using clock signal clk
                    tCO = 12.5 ns for bpctrl_h_tristate 
                    tPO = 15.0 ns for \sp_read:old_phase\.AP 
                    tRO = 21.0 ns for bpctrl(0).AR 
                    tER = 16.5 ns for bpctrl(4).OE 



Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully  
