
     | | | | | | |
   _________________
  -|               |-
  -|               |-
  -|               |-
  -|    CYPRESS    |-
  -|               |-
  -|               |-   Warp VHDL Synthesis Compiler: Version 6.2 IR 28.4
  -|               |-   Copyright (C) 1991-2001 Cypress Semiconductor
   |_______________|
     | | | | | | |

======================================================================
Compiling:  dong.vhd
Options:    -yu -e10 -w100 -o2 -ygs -fO -fP -v10 -dc37256 -pcy37256p160-125ac -a dong.vhd -u PCREMO~1.hie -uch0000
======================================================================

vhdlfe V6.2 IR 27:  VHDL parser
Mon Aug 18 14:57:02 2003

Library 'work' => directory 'lc37256'
Linking 'C:\Program Files\Cypress\Warp\bin\std.vhd'.
Linking 'C:\Program Files\Cypress\Warp\lib\common\cypress.vhd'.
Linking 'C:\Program Files\Cypress\Warp\lib\common\work\cypress.vif'.
Library 'ieee' => directory 'C:\Program Files\Cypress\Warp\lib\ieee\work'
Linking 'C:\Program Files\Cypress\Warp\lib\ieee\work\stdlogic.vif'.
Linking 'C:\Program Files\Cypress\Warp\lib\common\stdlogic\lpmpkg.vif'.
Linking 'C:\Program Files\Cypress\Warp\lib\common\stdlogic\rtlpkg.vif'.
Linking 'C:\Program Files\Cypress\Warp\lib\common\stdlogic\mod_cnst.vif'.
Linking 'C:\Program Files\Cypress\Warp\lib\common\stdlogic\mod_mthu.vif'.
Linking 'C:\Program Files\Cypress\Warp\lib\common\stdlogic\mod_mths.vif'.
Linking 'C:\Program Files\Cypress\Warp\lib\common\stdlogic\mod_genu.vif'.
dong.vhd (line 138, col 15):  Abort:  (E34) Undeclared name:  power_up
