
     | | | | | | |
   _________________
  -|               |-
  -|               |-
  -|               |-
  -|    CYPRESS    |-
  -|               |-
  -|               |-   Warp VHDL Synthesis Compiler: Version 6.2 IR 28.4
  -|               |-   Copyright (C) 1991-2001 Cypress Semiconductor
   |_______________|
     | | | | | | |

======================================================================
Compiling:  pc_remote_bus.vhd
Options:    -m -yu -e10 -w100 -o2 -ygs -fO -fP -v10 -dc37256 -pcy37256p160-125ac -b pc_remote_bus.vhd -u PC_REM~1.hie -uch0000
======================================================================

vhdlfe V6.2 IR 27:  VHDL parser
Wed Feb 05 20:12:53 2003

Library 'work' => directory 'lc37256'
Linking 'C:\Program Files\Cypress\Warp\bin\std.vhd'.
Linking 'C:\Program Files\Cypress\Warp\lib\common\cypress.vhd'.
Linking 'C:\Program Files\Cypress\Warp\lib\common\work\cypress.vif'.
Using control file 'pc_remote_bus.ctl'.
Library 'ieee' => directory 'C:\Program Files\Cypress\Warp\lib\ieee\work'
Linking 'C:\Program Files\Cypress\Warp\lib\ieee\work\stdlogic.vif'.
Linking 'C:\Program Files\Cypress\Warp\lib\common\stdlogic\lpmpkg.vif'.
Linking 'C:\Program Files\Cypress\Warp\lib\common\stdlogic\rtlpkg.vif'.
Linking 'C:\Program Files\Cypress\Warp\lib\common\stdlogic\mod_cnst.vif'.
Linking 'C:\Program Files\Cypress\Warp\lib\common\stdlogic\mod_mthu.vif'.
Linking 'C:\Program Files\Cypress\Warp\lib\common\stdlogic\mod_mths.vif'.
Linking 'C:\Program Files\Cypress\Warp\lib\common\stdlogic\mod_genu.vif'.
Note:  Using config. rule 'clk' to set attribute 'pin_numbers' on 'clk'.
Note:  Using config. rule 'reset' to set attribute 'pin_numbers' on 'reset'.
pc_remote_bus.vhd (line 65, col 34):  Note: Substituting module 'cmp_vv_us' for '='.
pc_remote_bus.vhd (line 69, col 36):  Note: Substituting module 'add_vi_us' for '+'.
pc_remote_bus.vhd (line 78, col 34):  Note: Substituting module 'cmp_vv_us' for '='.
pc_remote_bus.vhd (line 81, col 36):  Note: Substituting module 'add_vi_us' for '+'.
Library 'ieee' => directory 'C:\Program Files\Cypress\Warp\lib\ieee\work'
Note:  Using config. rule 'clk' to set attribute 'pin_numbers' on 'clk'.
Note:  Using config. rule 'reset' to set attribute 'pin_numbers' on 'reset'.
pc_remote_bus.vhd (line 223, col 34):  Note: Substituting module 'cmp_vv_us' for '='.
pc_remote_bus.vhd (line 229, col 36):  Note: Substituting module 'add_vi_us' for '+'.
pc_remote_bus.vhd (line 245, col 34):  Note: Substituting module 'cmp_vv_us' for '='.
pc_remote_bus.vhd (line 254, col 36):  Note: Substituting module 'add_vi_us' for '+'.
pc_remote_bus.vhd (line 288, col 34):  Note: Substituting module 'cmp_vv_us' for '='.
pc_remote_bus.vhd (line 291, col 36):  Note: Substituting module 'add_vi_us' for '+'.
pc_remote_bus.vhd (line 299, col 34):  Note: Substituting module 'cmp_vv_us' for '='.
pc_remote_bus.vhd (line 302, col 36):  Note: Substituting module 'add_vi_us' for '+'.
Library 'ieee' => directory 'C:\Program Files\Cypress\Warp\lib\ieee\work'
Note:  Using config. rule 'clk' to set attribute 'pin_numbers' on 'clk'.
Note:  Using config. rule 'reset' to set attribute 'pin_numbers' on 'reset'.
Note:  Using config. rule 'led1' to set attribute 'pin_numbers' on 'led1'.
pc_remote_bus.vhd (line 402, col 44):  Note: Substituting module 'cmp_vv_us' for '='.
pc_remote_bus.vhd (line 406, col 35):  Note: Substituting module 'add_vi_us' for '+'.
pc_remote_bus.vhd (line 414, col 43):  Note: Substituting module 'cmp_vv_us' for '='.
pc_remote_bus.vhd (line 419, col 34):  Note: Substituting module 'add_vi_us' for '+'.
pc_remote_bus.vhd (line 427, col 33):  Note: Substituting module 'cmp_vv_us' for '='.
pc_remote_bus.vhd (line 430, col 36):  Note: Substituting module 'add_vi_us' for '+'.
pc_remote_bus.vhd (line 436, col 43):  Note: Substituting module 'cmp_vv_us' for '='.
pc_remote_bus.vhd (line 438, col 34):  Note: Substituting module 'add_vi_us' for '+'.
pc_remote_bus.vhd (line 440, col 34):  Note: Substituting module 'add_vi_us' for '+'.
pc_remote_bus.vhd (line 446, col 43):  Note: Substituting module 'cmp_vv_us' for '='.
pc_remote_bus.vhd (line 451, col 34):  Note: Substituting module 'add_vi_us' for '+'.
pc_remote_bus.vhd (line 458, col 34):  Note: Substituting module 'cmp_vv_us' for '='.
pc_remote_bus.vhd (line 461, col 37):  Note: Substituting module 'add_vi_us' for '+'.
Library 'ieee' => directory 'C:\Program Files\Cypress\Warp\lib\ieee\work'
Note:  Using config. rule 'clk' to set attribute 'pin_numbers' on 'clk'.
Note:  Using config. rule 'reset' to set attribute 'pin_numbers' on 'reset'.
pc_remote_bus.vhd (line 531, col 30):  Note: Substituting module 'cmp_vv_us' for '='.
pc_remote_bus.vhd (line 542, col 50):  Note: Substituting module 'cmp_vv_us' for '='.
pc_remote_bus.vhd (line 577, col 45):  Note: Substituting module 'cmp_vv_us' for '='.
pc_remote_bus.vhd (line 634, col 35):  Note: Substituting module 'cmp_vv_us' for '='.
pc_remote_bus.vhd (line 639, col 34):  Note: Substituting module 'add_vi_us' for '+'.
pc_remote_bus.vhd (line 643, col 48):  Note: Substituting module 'add_vi_us' for '+'.
pc_remote_bus.vhd (line 647, col 35):  Note: Substituting module 'cmp_vv_us' for '='.
pc_remote_bus.vhd (line 650, col 42):  Note: Substituting module 'add_vi_us' for '+'.
Library 'ieee' => directory 'C:\Program Files\Cypress\Warp\lib\ieee\work'
Note:  Using config. rule 'clk' to set attribute 'pin_numbers' on 'clk'.
Note:  Using config. rule 'fast' to set attribute 'pin_numbers' on 'fast'.
Note:  Using config. rule 'slow' to set attribute 'pin_numbers' on 'slow'.
Note:  Using config. rule 'led2' to set attribute 'pin_numbers' on 'led2'.
Note:  Using config. rule 'led3' to set attribute 'pin_numbers' on 'led3'.
Note:  Using config. rule 'reset' to set attribute 'pin_numbers' on 'reset'.
Library 'ieee' => directory 'C:\Program Files\Cypress\Warp\lib\ieee\work'
Note:  Using config. rule 'led1' to set attribute 'pin_numbers' on 'led1'.
Note:  Using config. rule 'led2' to set attribute 'pin_numbers' on 'led2'.
Note:  Using config. rule 'led3' to set attribute 'pin_numbers' on 'led3'.
Note:  Using config. rule 'clk' to set attribute 'pin_numbers' on 'clk'.
Note:  Using config. rule 'fast' to set attribute 'pin_numbers' on 'fast'.
Note:  Using config. rule 'slow' to set attribute 'pin_numbers' on 'slow'.
Note:  Using config. rule 'reset' to set attribute 'pin_numbers' on 'reset'.
Note:  Using config. rule 'ao_from_pc_strobe' to set attribute 'pin_numbers' on 'ao_from_pc_strobe'.
Note:  Using config. rule 'ao_from_pc_ack' to set attribute 'pin_numbers' on 'ao_from_pc_ack'.
Note:  Using config. rule 'ao_to_pc_strobe' to set attribute 'pin_numbers' on 'ao_to_pc_strobe'.
Note:  Using config. rule 'ao_to_pc_ack' to set attribute 'pin_numbers' on 'ao_to_pc_ack'.
Note:  Using config. rule 'bpd_h_dir' to set attribute 'pin_numbers' on 'bpd_h_dir'.
Note:  Using config. rule 'bpd_h_tristate' to set attribute 'pin_numbers' on 'bpd_h_tristate'.
Note:  Using config. rule 'bpd_l_dir' to set attribute 'pin_numbers' on 'bpd_l_dir'.
Note:  Using config. rule 'bpd_l_tristate' to set attribute 'pin_numbers' on 'bpd_l_tristate'.
Note:  Using config. rule 'bpaddr_dir' to set attribute 'pin_numbers' on 'bpaddr_dir'.
Note:  Using config. rule 'bpaddr_tristate' to set attribute 'pin_numbers' on 'bpaddr_tristate'.
Note:  Using config. rule 'bpctrl_h_dir' to set attribute 'pin_numbers' on 'bpctrl_h_dir'.
Note:  Using config. rule 'bpctrl_l_dir' to set attribute 'pin_numbers' on 'bpctrl_l_dir'.
Note:  Using config. rule 'bpctrl_h_tristate' to set attribute 'pin_numbers' on 'bpctrl_h_tristate'.
Note:  Using config. rule 'bpctrl_l_tristate' to set attribute 'pin_numbers' on 'bpctrl_l_tristate'.
Note:  Using config. rule 'sinphase_zeros' to set attribute 'pin_numbers' on 'sinphase_zeros'.
Note:  Using config. rule 'bpctrl(15)' to set attribute 'pin_numbers' on 'bpctrl(15)'.
Note:  Using config. rule 'bpctrl(14)' to set attribute 'pin_numbers' on 'bpctrl(14)'.
Note:  Using config. rule 'bpctrl(13)' to set attribute 'pin_numbers' on 'bpctrl(13)'.
Note:  Using config. rule 'bpctrl(12)' to set attribute 'pin_numbers' on 'bpctrl(12)'.
Note:  Using config. rule 'bpctrl(11)' to set attribute 'pin_numbers' on 'bpctrl(11)'.
Note:  Using config. rule 'bpctrl(10)' to set attribute 'pin_numbers' on 'bpctrl(10)'.
Note:  Using config. rule 'bpctrl(9)' to set attribute 'pin_numbers' on 'bpctrl(9)'.
Note:  Using config. rule 'bpctrl(8)' to set attribute 'pin_numbers' on 'bpctrl(8)'.
Note:  Using config. rule 'bpctrl(7)' to set attribute 'pin_numbers' on 'bpctrl(7)'.
Note:  Using config. rule 'bpctrl(6)' to set attribute 'pin_numbers' on 'bpctrl(6)'.
Note:  Using config. rule 'bpctrl(5)' to set attribute 'pin_numbers' on 'bpctrl(5)'.
Note:  Using config. rule 'bpctrl(4)' to set attribute 'pin_numbers' on 'bpctrl(4)'.
Note:  Using config. rule 'bpctrl(3)' to set attribute 'pin_numbers' on 'bpctrl(3)'.
Note:  Using config. rule 'bpctrl(2)' to set attribute 'pin_numbers' on 'bpctrl(2)'.
Note:  Using config. rule 'bpctrl(1)' to set attribute 'pin_numbers' on 'bpctrl(1)'.
Note:  Using config. rule 'bpctrl(0)' to set attribute 'pin_numbers' on 'bpctrl(0)'.
Note:  Using config. rule 'clk' to set attribute 'pin_numbers' on 'clk'.
Note:  Using config. rule 'fast' to set attribute 'pin_numbers' on 'fast'.
Note:  Using config. rule 'slow' to set attribute 'pin_numbers' on 'slow'.
Note:  Using config. rule 'led2' to set attribute 'pin_numbers' on 'led2'.
Note:  Using config. rule 'led3' to set attribute 'pin_numbers' on 'led3'.
Note:  Using config. rule 'reset' to set attribute 'pin_numbers' on 'reset'.
Note:  Using config. rule 'clk' to set attribute 'pin_numbers' on 'clk'.
Note:  Using config. rule 'reset' to set attribute 'pin_numbers' on 'reset'.
Note:  Using config. rule 'clk' to set attribute 'pin_numbers' on 'clk'.
Note:  Using config. rule 'reset' to set attribute 'pin_numbers' on 'reset'.
Note:  Using config. rule 'clk' to set attribute 'pin_numbers' on 'clk'.
Note:  Using config. rule 'reset' to set attribute 'pin_numbers' on 'reset'.
Note:  Using config. rule 'led1' to set attribute 'pin_numbers' on 'led1'.
Note:  Using config. rule 'clk' to set attribute 'pin_numbers' on 'clk'.
Note:  Using config. rule 'reset' to set attribute 'pin_numbers' on 'reset'.

vhdlfe:  No errors.


tovif V6.2 IR 27:  High-level synthesis
Wed Feb 05 20:12:53 2003

Linking 'C:\Program Files\Cypress\Warp\bin\std.vhd'.
Linking 'C:\Program Files\Cypress\Warp\lib\common\cypress.vhd'.
Linking 'C:\Program Files\Cypress\Warp\lib\common\work\cypress.vif'.
Linking 'C:\Rob\MULTIF~1\PC_REM~1\bus\pc_remote_bus.ctl'.
Linking 'C:\Program Files\Cypress\Warp\lib\ieee\work\stdlogic.vif'.
Linking 'C:\Program Files\Cypress\Warp\lib\common\stdlogic\lpmpkg.vif'.
Linking 'C:\Program Files\Cypress\Warp\lib\common\stdlogic\rtlpkg.vif'.
Linking 'C:\Program Files\Cypress\Warp\lib\common\stdlogic\mod_cnst.vif'.
Linking 'C:\Program Files\Cypress\Warp\lib\common\stdlogic\mod_mthu.vif'.
Linking 'C:\Program Files\Cypress\Warp\lib\common\stdlogic\mod_mths.vif'.
Linking 'C:\Program Files\Cypress\Warp\lib\common\stdlogic\mod_genu.vif'.
Linking 'C:\Program Files\Cypress\Warp\lib\common\stdlogic\mcompare.vif'.
pc_remote_bus.vhd (line 347, col 6):  Warning: (W460) 'read_from_bp_data(15)' unassigned in arch. 'backplane_io' of backplane_io.
pc_remote_bus.vhd (line 517, col 25):  Warning: (W479) 'phase' should be referenced in the sensitivity list.
pc_remote_bus.vhd (line 508, col 6):  Warning: (W460) 'data(14)' unassigned in arch. 'read_counters_arch' of read_counters.
pc_remote_bus.vhd (line 508, col 6):  Warning: (W460) 'data(13)' unassigned in arch. 'read_counters_arch' of read_counters.
pc_remote_bus.vhd (line 508, col 6):  Warning: (W460) 'data(12)' unassigned in arch. 'read_counters_arch' of read_counters.
pc_remote_bus.vhd (line 508, col 6):  Warning: (W460) 'data(11)' unassigned in arch. 'read_counters_arch' of read_counters.
pc_remote_bus.vhd (line 508, col 6):  Warning: (W460) 'data(10)' unassigned in arch. 'read_counters_arch' of read_counters.
pc_remote_bus.vhd (line 508, col 6):  Warning: (W460) 'data(9)' unassigned in arch. 'read_counters_arch' of read_counters.
pc_remote_bus.vhd (line 508, col 6):  Warning: (W460) 'data(8)' unassigned in arch. 'read_counters_arch' of read_counters.
pc_remote_bus.vhd (line 508, col 6):  Warning: (W460) 'data(7)' unassigned in arch. 'read_counters_arch' of read_counters.
pc_remote_bus.vhd (line 508, col 6):  Warning: (W460) 'data(6)' unassigned in arch. 'read_counters_arch' of read_counters.
pc_remote_bus.vhd (line 508, col 6):  Warning: (W460) 'data(5)' unassigned in arch. 'read_counters_arch' of read_counters.
pc_remote_bus.vhd (line 508, col 6):  Warning: (W460) 'data(4)' unassigned in arch. 'read_counters_arch' of read_counters.
pc_remote_bus.vhd (line 508, col 6):  Warning: (W460) 'data(3)' unassigned in arch. 'read_counters_arch' of read_counters.
pc_remote_bus.vhd (line 508, col 6):  Warning: (W460) 'data(2)' unassigned in arch. 'read_counters_arch' of read_counters.
pc_remote_bus.vhd (line 508, col 6):  Warning: (W460) 'data(1)' unassigned in arch. 'read_counters_arch' of read_counters.
pc_remote_bus.vhd (line 508, col 6):  Warning: (W460) 'data(0)' unassigned in arch. 'read_counters_arch' of read_counters.
Note:  Using config. rule 'd(31)' to set attribute 'pin_numbers' on 'd(31)'.
Note:  Using config. rule 'd(30)' to set attribute 'pin_numbers' on 'd(30)'.
Note:  Using config. rule 'd(29)' to set attribute 'pin_numbers' on 'd(29)'.
Note:  Using config. rule 'd(28)' to set attribute 'pin_numbers' on 'd(28)'.
Note:  Using config. rule 'd(27)' to set attribute 'pin_numbers' on 'd(27)'.
Note:  Using config. rule 'd(26)' to set attribute 'pin_numbers' on 'd(26)'.
Note:  Using config. rule 'd(25)' to set attribute 'pin_numbers' on 'd(25)'.
Note:  Using config. rule 'd(24)' to set attribute 'pin_numbers' on 'd(24)'.
Note:  Using config. rule 'd(23)' to set attribute 'pin_numbers' on 'd(23)'.
Note:  Using config. rule 'd(22)' to set attribute 'pin_numbers' on 'd(22)'.
Note:  Using config. rule 'd(21)' to set attribute 'pin_numbers' on 'd(21)'.
Note:  Using config. rule 'd(20)' to set attribute 'pin_numbers' on 'd(20)'.
Note:  Using config. rule 'd(19)' to set attribute 'pin_numbers' on 'd(19)'.
Note:  Using config. rule 'd(18)' to set attribute 'pin_numbers' on 'd(18)'.
Note:  Using config. rule 'd(17)' to set attribute 'pin_numbers' on 'd(17)'.
Note:  Using config. rule 'd(16)' to set attribute 'pin_numbers' on 'd(16)'.
Note:  Using config. rule 'd(15)' to set attribute 'pin_numbers' on 'd(15)'.
Note:  Using config. rule 'd(14)' to set attribute 'pin_numbers' on 'd(14)'.
Note:  Using config. rule 'd(13)' to set attribute 'pin_numbers' on 'd(13)'.
Note:  Using config. rule 'd(12)' to set attribute 'pin_numbers' on 'd(12)'.
Note:  Using config. rule 'd(11)' to set attribute 'pin_numbers' on 'd(11)'.
Note:  Using config. rule 'd(10)' to set attribute 'pin_numbers' on 'd(10)'.
Note:  Using config. rule 'd(9)' to set attribute 'pin_numbers' on 'd(9)'.
Note:  Using config. rule 'd(8)' to set attribute 'pin_numbers' on 'd(8)'.
Note:  Using config. rule 'd(7)' to set attribute 'pin_numbers' on 'd(7)'.
Note:  Using config. rule 'd(6)' to set attribute 'pin_numbers' on 'd(6)'.
Note:  Using config. rule 'd(5)' to set attribute 'pin_numbers' on 'd(5)'.
Note:  Using config. rule 'd(4)' to set attribute 'pin_numbers' on 'd(4)'.
Note:  Using config. rule 'd(3)' to set attribute 'pin_numbers' on 'd(3)'.
Note:  Using config. rule 'd(2)' to set attribute 'pin_numbers' on 'd(2)'.
Note:  Using config. rule 'd(1)' to set attribute 'pin_numbers' on 'd(1)'.
Note:  Using config. rule 'd(0)' to set attribute 'pin_numbers' on 'd(0)'.
Note:  Using config. rule 'bpaddr(7)' to set attribute 'pin_numbers' on 'bpaddr(7)'.
Note:  Using config. rule 'bpaddr(6)' to set attribute 'pin_numbers' on 'bpaddr(6)'.
Note:  Using config. rule 'bpaddr(5)' to set attribute 'pin_numbers' on 'bpaddr(5)'.
Note:  Using config. rule 'bpaddr(4)' to set attribute 'pin_numbers' on 'bpaddr(4)'.
Note:  Using config. rule 'bpaddr(3)' to set attribute 'pin_numbers' on 'bpaddr(3)'.
Note:  Using config. rule 'bpaddr(2)' to set attribute 'pin_numbers' on 'bpaddr(2)'.
Note:  Using config. rule 'bpaddr(1)' to set attribute 'pin_numbers' on 'bpaddr(1)'.
Note:  Using config. rule 'bpaddr(0)' to set attribute 'pin_numbers' on 'bpaddr(0)'.
Note:  Using config. rule 'bpd(15)' to set attribute 'pin_numbers' on 'bpd(15)'.
Note:  Using config. rule 'bpd(14)' to set attribute 'pin_numbers' on 'bpd(14)'.
Note:  Using config. rule 'bpd(13)' to set attribute 'pin_numbers' on 'bpd(13)'.
Note:  Using config. rule 'bpd(12)' to set attribute 'pin_numbers' on 'bpd(12)'.
Note:  Using config. rule 'bpd(11)' to set attribute 'pin_numbers' on 'bpd(11)'.
Note:  Using config. rule 'bpd(10)' to set attribute 'pin_numbers' on 'bpd(10)'.
Note:  Using config. rule 'bpd(9)' to set attribute 'pin_numbers' on 'bpd(9)'.
Note:  Using config. rule 'bpd(8)' to set attribute 'pin_numbers' on 'bpd(8)'.
Note:  Using config. rule 'bpd(7)' to set attribute 'pin_numbers' on 'bpd(7)'.
Note:  Using config. rule 'bpd(6)' to set attribute 'pin_numbers' on 'bpd(6)'.
Note:  Using config. rule 'bpd(5)' to set attribute 'pin_numbers' on 'bpd(5)'.
Note:  Using config. rule 'bpd(4)' to set attribute 'pin_numbers' on 'bpd(4)'.
Note:  Using config. rule 'bpd(3)' to set attribute 'pin_numbers' on 'bpd(3)'.
Note:  Using config. rule 'bpd(2)' to set attribute 'pin_numbers' on 'bpd(2)'.
Note:  Using config. rule 'bpd(1)' to set attribute 'pin_numbers' on 'bpd(1)'.
Note:  Using config. rule 'bpd(0)' to set attribute 'pin_numbers' on 'bpd(0)'.
Note:  Using config. rule 'sw(7)' to set attribute 'pin_numbers' on 'sw(7)'.
Note:  Using config. rule 'sw(6)' to set attribute 'pin_numbers' on 'sw(6)'.
Note:  Using config. rule 'sw(5)' to set attribute 'pin_numbers' on 'sw(5)'.
Note:  Using config. rule 'sw(4)' to set attribute 'pin_numbers' on 'sw(4)'.
Note:  Using config. rule 'sw(3)' to set attribute 'pin_numbers' on 'sw(3)'.
Note:  Using config. rule 'sw(2)' to set attribute 'pin_numbers' on 'sw(2)'.
Note:  Using config. rule 'sw(1)' to set attribute 'pin_numbers' on 'sw(1)'.
Note:  Using config. rule 'sw(0)' to set attribute 'pin_numbers' on 'sw(0)'.
pc_remote_bus.vhd (line 806, col 6):  Warning: (W460) 'ao_from_pc_strobe' unassigned in arch. 'tout_arch' of tout.
pc_remote_bus.vhd (line 806, col 6):  Warning: (W460) 'bpctrl(15)' unassigned in arch. 'tout_arch' of tout.
pc_remote_bus.vhd (line 806, col 6):  Warning: (W460) 'bpctrl(14)' unassigned in arch. 'tout_arch' of tout.
pc_remote_bus.vhd (line 806, col 6):  Warning: (W460) 'bpctrl(13)' unassigned in arch. 'tout_arch' of tout.
pc_remote_bus.vhd (line 806, col 6):  Warning: (W460) 'bpctrl(12)' unassigned in arch. 'tout_arch' of tout.
pc_remote_bus.vhd (line 806, col 6):  Warning: (W460) 'bpctrl(9)' unassigned in arch. 'tout_arch' of tout.
pc_remote_bus.vhd (line 806, col 6):  Warning: (W460) 'bpd(9)' unassigned in arch. 'tout_arch' of tout.
pc_remote_bus.vhd (line 806, col 6):  Warning: (W460) 'bpd(8)' unassigned in arch. 'tout_arch' of tout.
pc_remote_bus.vhd (line 806, col 6):  Warning: (W460) 'bpd(7)' unassigned in arch. 'tout_arch' of tout.
pc_remote_bus.vhd (line 806, col 6):  Warning: (W460) 'bpd(6)' unassigned in arch. 'tout_arch' of tout.
pc_remote_bus.vhd (line 806, col 6):  Warning: (W460) 'bpd(5)' unassigned in arch. 'tout_arch' of tout.
pc_remote_bus.vhd (line 806, col 6):  Warning: (W460) 'bpd(4)' unassigned in arch. 'tout_arch' of tout.
pc_remote_bus.vhd (line 806, col 6):  Warning: (W460) 'bpd(3)' unassigned in arch. 'tout_arch' of tout.
pc_remote_bus.vhd (line 806, col 6):  Warning: (W460) 'bpd(2)' unassigned in arch. 'tout_arch' of tout.
pc_remote_bus.vhd (line 806, col 6):  Warning: (W460) 'bpd(1)' unassigned in arch. 'tout_arch' of tout.
pc_remote_bus.vhd (line 806, col 6):  Warning: (W460) 'bpd(0)' unassigned in arch. 'tout_arch' of tout.

tovif:  No errors.  33 warnings.


topld V6.2 IR 27:  Synthesis and optimization
Wed Feb 05 20:12:55 2003

Linking 'C:\Program Files\Cypress\Warp\bin\std.vhd'.
Linking 'C:\Program Files\Cypress\Warp\lib\common\cypress.vhd'.
Linking 'C:\Program Files\Cypress\Warp\lib\common\work\cypress.vif'.
Linking 'C:\Rob\MULTIF~1\PC_REM~1\bus\pc_remote_bus.ctl'.
Linking 'C:\Program Files\Cypress\Warp\lib\ieee\work\stdlogic.vif'.
Linking 'C:\Program Files\Cypress\Warp\lib\common\stdlogic\lpmpkg.vif'.
Linking 'C:\Program Files\Cypress\Warp\lib\common\stdlogic\rtlpkg.vif'.
Linking 'C:\Program Files\Cypress\Warp\lib\common\stdlogic\mod_cnst.vif'.
Linking 'C:\Program Files\Cypress\Warp\lib\common\stdlogic\mod_mthu.vif'.
Linking 'C:\Program Files\Cypress\Warp\lib\common\stdlogic\mod_mths.vif'.
Linking 'C:\Program Files\Cypress\Warp\lib\common\stdlogic\mod_genu.vif'.
Linking 'C:\Program Files\Cypress\Warp\lib\common\stdlogic\mcompare.vif'.
Note:  Using config. rule 'led1' to set attribute 'pin_numbers' on 'led1'.
Note:  Using config. rule 'led2' to set attribute 'pin_numbers' on 'led2'.
Note:  Using config. rule 'led3' to set attribute 'pin_numbers' on 'led3'.
Note:  Using config. rule 'clk' to set attribute 'pin_numbers' on 'clk'.
Note:  Using config. rule 'fast' to set attribute 'pin_numbers' on 'fast'.
Note:  Using config. rule 'slow' to set attribute 'pin_numbers' on 'slow'.
Note:  Using config. rule 'd(31)' to set attribute 'pin_numbers' on 'd(31)'.
Note:  Using config. rule 'd(30)' to set attribute 'pin_numbers' on 'd(30)'.
Note:  Using config. rule 'd(29)' to set attribute 'pin_numbers' on 'd(29)'.
Note:  Using config. rule 'd(28)' to set attribute 'pin_numbers' on 'd(28)'.
Note:  Using config. rule 'd(27)' to set attribute 'pin_numbers' on 'd(27)'.
Note:  Using config. rule 'd(26)' to set attribute 'pin_numbers' on 'd(26)'.
Note:  Using config. rule 'd(25)' to set attribute 'pin_numbers' on 'd(25)'.
Note:  Using config. rule 'd(24)' to set attribute 'pin_numbers' on 'd(24)'.
Note:  Using config. rule 'd(23)' to set attribute 'pin_numbers' on 'd(23)'.
Note:  Using config. rule 'd(22)' to set attribute 'pin_numbers' on 'd(22)'.
Note:  Using config. rule 'd(21)' to set attribute 'pin_numbers' on 'd(21)'.
Note:  Using config. rule 'd(20)' to set attribute 'pin_numbers' on 'd(20)'.
Note:  Using config. rule 'd(19)' to set attribute 'pin_numbers' on 'd(19)'.
Note:  Using config. rule 'd(18)' to set attribute 'pin_numbers' on 'd(18)'.
Note:  Using config. rule 'd(17)' to set attribute 'pin_numbers' on 'd(17)'.
Note:  Using config. rule 'd(16)' to set attribute 'pin_numbers' on 'd(16)'.
Note:  Using config. rule 'd(15)' to set attribute 'pin_numbers' on 'd(15)'.
Note:  Using config. rule 'd(14)' to set attribute 'pin_numbers' on 'd(14)'.
Note:  Using config. rule 'd(13)' to set attribute 'pin_numbers' on 'd(13)'.
Note:  Using config. rule 'd(12)' to set attribute 'pin_numbers' on 'd(12)'.
Note:  Using config. rule 'd(11)' to set attribute 'pin_numbers' on 'd(11)'.
Note:  Using config. rule 'd(10)' to set attribute 'pin_numbers' on 'd(10)'.
Note:  Using config. rule 'd(9)' to set attribute 'pin_numbers' on 'd(9)'.
Note:  Using config. rule 'd(8)' to set attribute 'pin_numbers' on 'd(8)'.
Note:  Using config. rule 'd(7)' to set attribute 'pin_numbers' on 'd(7)'.
Note:  Using config. rule 'd(6)' to set attribute 'pin_numbers' on 'd(6)'.
Note:  Using config. rule 'd(5)' to set attribute 'pin_numbers' on 'd(5)'.
Note:  Using config. rule 'd(4)' to set attribute 'pin_numbers' on 'd(4)'.
Note:  Using config. rule 'd(3)' to set attribute 'pin_numbers' on 'd(3)'.
Note:  Using config. rule 'd(2)' to set attribute 'pin_numbers' on 'd(2)'.
Note:  Using config. rule 'd(1)' to set attribute 'pin_numbers' on 'd(1)'.
Note:  Using config. rule 'd(0)' to set attribute 'pin_numbers' on 'd(0)'.
Note:  Using config. rule 'reset' to set attribute 'pin_numbers' on 'reset'.
Note:  Using config. rule 'ao_from_pc_strobe' to set attribute 'pin_numbers' on 'ao_from_pc_strobe'.
Note:  Using config. rule 'ao_from_pc_ack' to set attribute 'pin_numbers' on 'ao_from_pc_ack'.
Note:  Using config. rule 'ao_to_pc_strobe' to set attribute 'pin_numbers' on 'ao_to_pc_strobe'.
Note:  Using config. rule 'ao_to_pc_ack' to set attribute 'pin_numbers' on 'ao_to_pc_ack'.
Note:  Using config. rule 'bpaddr(7)' to set attribute 'pin_numbers' on 'bpaddr(7)'.
Note:  Using config. rule 'bpaddr(6)' to set attribute 'pin_numbers' on 'bpaddr(6)'.
Note:  Using config. rule 'bpaddr(5)' to set attribute 'pin_numbers' on 'bpaddr(5)'.
Note:  Using config. rule 'bpaddr(4)' to set attribute 'pin_numbers' on 'bpaddr(4)'.
Note:  Using config. rule 'bpaddr(3)' to set attribute 'pin_numbers' on 'bpaddr(3)'.
Note:  Using config. rule 'bpaddr(2)' to set attribute 'pin_numbers' on 'bpaddr(2)'.
Note:  Using config. rule 'bpaddr(1)' to set attribute 'pin_numbers' on 'bpaddr(1)'.
Note:  Using config. rule 'bpaddr(0)' to set attribute 'pin_numbers' on 'bpaddr(0)'.
Note:  Using config. rule 'bpctrl(15)' to set attribute 'pin_numbers' on 'bpctrl(15)'.
Note:  Using config. rule 'bpctrl(14)' to set attribute 'pin_numbers' on 'bpctrl(14)'.
Note:  Using config. rule 'bpctrl(13)' to set attribute 'pin_numbers' on 'bpctrl(13)'.
Note:  Using config. rule 'bpctrl(12)' to set attribute 'pin_numbers' on 'bpctrl(12)'.
Note:  Using config. rule 'bpctrl(11)' to set attribute 'pin_numbers' on 'bpctrl(11)'.
Note:  Using config. rule 'bpctrl(10)' to set attribute 'pin_numbers' on 'bpctrl(10)'.
Note:  Using config. rule 'bpctrl(9)' to set attribute 'pin_numbers' on 'bpctrl(9)'.
Note:  Using config. rule 'bpctrl(8)' to set attribute 'pin_numbers' on 'bpctrl(8)'.
Note:  Using config. rule 'bpctrl(7)' to set attribute 'pin_numbers' on 'bpctrl(7)'.
Note:  Using config. rule 'bpctrl(6)' to set attribute 'pin_numbers' on 'bpctrl(6)'.
Note:  Using config. rule 'bpctrl(5)' to set attribute 'pin_numbers' on 'bpctrl(5)'.
Note:  Using config. rule 'bpctrl(4)' to set attribute 'pin_numbers' on 'bpctrl(4)'.
Note:  Using config. rule 'bpctrl(3)' to set attribute 'pin_numbers' on 'bpctrl(3)'.
Note:  Using config. rule 'bpctrl(2)' to set attribute 'pin_numbers' on 'bpctrl(2)'.
Note:  Using config. rule 'bpctrl(1)' to set attribute 'pin_numbers' on 'bpctrl(1)'.
Note:  Using config. rule 'bpctrl(0)' to set attribute 'pin_numbers' on 'bpctrl(0)'.
Note:  Using config. rule 'bpd(15)' to set attribute 'pin_numbers' on 'bpd(15)'.
Note:  Using config. rule 'bpd(14)' to set attribute 'pin_numbers' on 'bpd(14)'.
Note:  Using config. rule 'bpd(13)' to set attribute 'pin_numbers' on 'bpd(13)'.
Note:  Using config. rule 'bpd(12)' to set attribute 'pin_numbers' on 'bpd(12)'.
Note:  Using config. rule 'bpd(11)' to set attribute 'pin_numbers' on 'bpd(11)'.
Note:  Using config. rule 'bpd(10)' to set attribute 'pin_numbers' on 'bpd(10)'.
Note:  Using config. rule 'bpd(9)' to set attribute 'pin_numbers' on 'bpd(9)'.
Note:  Using config. rule 'bpd(8)' to set attribute 'pin_numbers' on 'bpd(8)'.
Note:  Using config. rule 'bpd(7)' to set attribute 'pin_numbers' on 'bpd(7)'.
Note:  Using config. rule 'bpd(6)' to set attribute 'pin_numbers' on 'bpd(6)'.
Note:  Using config. rule 'bpd(5)' to set attribute 'pin_numbers' on 'bpd(5)'.
Note:  Using config. rule 'bpd(4)' to set attribute 'pin_numbers' on 'bpd(4)'.
Note:  Using config. rule 'bpd(3)' to set attribute 'pin_numbers' on 'bpd(3)'.
Note:  Using config. rule 'bpd(2)' to set attribute 'pin_numbers' on 'bpd(2)'.
Note:  Using config. rule 'bpd(1)' to set attribute 'pin_numbers' on 'bpd(1)'.
Note:  Using config. rule 'bpd(0)' to set attribute 'pin_numbers' on 'bpd(0)'.
Note:  Using config. rule 'bpd_h_dir' to set attribute 'pin_numbers' on 'bpd_h_dir'.
Note:  Using config. rule 'bpd_h_tristate' to set attribute 'pin_numbers' on 'bpd_h_tristate'.
Note:  Using config. rule 'bpd_l_dir' to set attribute 'pin_numbers' on 'bpd_l_dir'.
Note:  Using config. rule 'bpd_l_tristate' to set attribute 'pin_numbers' on 'bpd_l_tristate'.
Note:  Using config. rule 'bpaddr_dir' to set attribute 'pin_numbers' on 'bpaddr_dir'.
Note:  Using config. rule 'bpaddr_tristate' to set attribute 'pin_numbers' on 'bpaddr_tristate'.
Note:  Using config. rule 'bpctrl_h_dir' to set attribute 'pin_numbers' on 'bpctrl_h_dir'.
Note:  Using config. rule 'bpctrl_l_dir' to set attribute 'pin_numbers' on 'bpctrl_l_dir'.
Note:  Using config. rule 'bpctrl_h_tristate' to set attribute 'pin_numbers' on 'bpctrl_h_tristate'.
Note:  Using config. rule 'bpctrl_l_tristate' to set attribute 'pin_numbers' on 'bpctrl_l_tristate'.
Note:  Using config. rule 'sw(7)' to set attribute 'pin_numbers' on 'sw(7)'.
Note:  Using config. rule 'sw(6)' to set attribute 'pin_numbers' on 'sw(6)'.
Note:  Using config. rule 'sw(5)' to set attribute 'pin_numbers' on 'sw(5)'.
Note:  Using config. rule 'sw(4)' to set attribute 'pin_numbers' on 'sw(4)'.
Note:  Using config. rule 'sw(3)' to set attribute 'pin_numbers' on 'sw(3)'.
Note:  Using config. rule 'sw(2)' to set attribute 'pin_numbers' on 'sw(2)'.
Note:  Using config. rule 'sw(1)' to set attribute 'pin_numbers' on 'sw(1)'.
Note:  Using config. rule 'sw(0)' to set attribute 'pin_numbers' on 'sw(0)'.
Note:  Using config. rule 'sinphase_zeros' to set attribute 'pin_numbers' on 'sinphase_zeros'.
Linking 'C:\Program Files\Cypress\Warp\lib\lc370\stdlogic\c370.vif'.
State variable 'tristate_state' is represented by a Bit_vector (0 to 0).
State encoding (sequential) for 'tristate_state' is:
	idle :=	b"0";
	active :=	b"1";
State variable 'iu_write' is represented by a Bit_vector (0 to 1).
State encoding (sequential) for 'iu_write' is:
	idle :=	b"00";
	hs :=	b"01";
	iu_hs1 :=	b"10";
	iu_hs2 :=	b"11";
State variable 'il_read_state' is represented by a Bit_vector (0 to 2).
State encoding (sequential) for 'il_read_state' is:
	idle :=	b"000";
	am_i_addressed :=	b"001";
	il_hs_for_address :=	b"010";
	il_hs_for_data :=	b"011";
	il_use_ctrl_data :=	b"100";
	internal_ack1 :=	b"101";
	internal_ack2 :=	b"110";
State variable 'bp_access_state' is represented by a Bit_vector (0 to 2).
State encoding (sequential) for 'bp_access_state' is:
	idle :=	b"000";
	write_wait :=	b"001";
	write_settle :=	b"010";
	write_strobe :=	b"011";
	write_ack :=	b"100";
	read_from_bp :=	b"101";
	read_strobe :=	b"110";
	read_ack :=	b"111";
State variable 'counter_read_state' is represented by a Bit_vector (0 to 3).
State encoding (sequential) for 'counter_read_state' is:
	idle :=	b"0000";
	valid_address :=	b"0001";
	increment_address :=	b"0010";
	test_end :=	b"0011";
	delay_packet :=	b"0100";
	start_fetch :=	b"0101";
	complete_fetch :=	b"0110";
	transfer_to_pc :=	b"0111";
	complete_pc_transfer :=	b"1000";
	do_reset_counters :=	b"1001";
Note:  Using config. rule 'clk' to set attribute 'pin_numbers' on 'clk'.
Note:  Using config. rule 'clk' to set attribute 'pin_numbers' on 'clk'.

----------------------------------------------------------
Detecting unused logic.
----------------------------------------------------------
    User names
	soft_request_reset


Deleted 1 User equation or component.
Deleted 57 Synthesized equations/components.

------------------------------------------------------
Alias Detection
------------------------------------------------------

------------------------------------------------------
Aliased 0 equations, 182 wires.
------------------------------------------------------

----------------------------------------------------------
Circuit simplification
----------------------------------------------------------
Note:  Virtual signal \sp_read:cmp_vv_us_MODGEN_10\ with ( cost: 1073741824 or cost_inv: 1073741824)  > 30000 or with size: 256 > 256 has been made a (soft) node.

----------------------------------------------------------
Circuit simplification results:

	Expanded 130 signals.
	Turned 1 signals into soft nodes.
	Maximum default expansion cost was set at 10.
----------------------------------------------------------

------------------------------------------------------
Alias Detection
------------------------------------------------------

------------------------------------------------------
Aliased 0 equations, 0 wires.
------------------------------------------------------
Created 762 PLD nodes.

topld:  No errors.

----------------------------------------------------------------------------
PLD Optimizer Software:       DSGNOPT.EXE    31/03/2000  [v4.02 ] 6.2 IR 27

DESIGN HEADER INFORMATION  (20:13:12)

Input File(s): pc_remote_bus.pla
Device       : cy37256p160
Package      : cy37256p160-125ac
ReportFile   : pc_remote_bus.rpt

Program Controls:
    COMMAND LANGUAGE_VHDL 
    COMMAND UserCode 0000000000000000 
    COMMAND PROPERTY BUS_HOLD ENABLE 

Signal Requests:
    GROUP DT-OPT ALL
    GROUP USEPOL ALL
    GROUP FAST_SLEW ALL
    GROUP SOFT \sp_read:cmp_vv_us_MODGEN_10\ 

Completed Successfully  
----------------------------------------------------------------------------
PLD Optimizer Software:       DSGNOPT.EXE    31/03/2000  [v4.02 ] 6.2 IR 27

OPTIMIZATION OPTIONS       (20:13:12)

Messages:
  Information: Process virtual '\sp_read:cmp_vv_us_MODGEN_10\' ... converted to NODE.
  Information: Process virtual '\sp_read:delay_count_0\\D\'\sp_read:delay_count_0\\D\ ... expanded.
  Information: Process virtual '\sp_read:delay_count_1\\D\'\sp_read:delay_count_1\\D\ ... expanded.
  Information: Process virtual '\sp_read:delay_count_2\\D\'\sp_read:delay_count_2\\D\ ... expanded.
  Information: Process virtual '\sp_read:delay_count_3\\D\'\sp_read:delay_count_3\\D\ ... expanded.
  Information: Process virtual '\sp_read:delay_count_4\\D\'\sp_read:delay_count_4\\D\ ... expanded.
  Information: Process virtual '\sp_read:delay_count_5\\D\'\sp_read:delay_count_5\\D\ ... expanded.
  Information: Process virtual '\sp_read:delay_count_6\\D\'\sp_read:delay_count_6\\D\ ... expanded.
  Information: Process virtual '\sp_read:delay_count_7\\D\'\sp_read:delay_count_7\\D\ ... expanded.
  Information: Process virtual '\sp_read:delay_count_8\\D\'\sp_read:delay_count_8\\D\ ... expanded.
  Information: Process virtual '\sp_read:delay_count_9\\D\'\sp_read:delay_count_9\\D\ ... expanded.
  Information: Process virtual '\sp_read:counter_address_0\\D\'\sp_read:counter_address_0\\D\ ... expanded.
  Information: Process virtual '\sp_read:counter_address_1\\D\'\sp_read:counter_address_1\\D\ ... expanded.
  Information: Process virtual '\sp_read:counter_address_2\\D\'\sp_read:counter_address_2\\D\ ... expanded.
  Information: Process virtual '\sp_read:counter_address_3\\D\'\sp_read:counter_address_3\\D\ ... expanded.
  Information: Process virtual '\sp_read:counter_address_4\\D\'\sp_read:counter_address_4\\D\ ... expanded.
  Information: Process virtual '\sp_read:counter_address_5\\D\'\sp_read:counter_address_5\\D\ ... expanded.
  Information: Process virtual '\sp_read:counter_address_6\\D\'\sp_read:counter_address_6\\D\ ... expanded.
  Information: Process virtual '\sp_read:counter_address_7\\D\'\sp_read:counter_address_7\\D\ ... expanded.
  Information: Process virtual '\sp_read:reset_count_0\\D\'\sp_read:reset_count_0\\D\ ... expanded.
  Information: Process virtual '\sp_read:reset_count_1\\D\'\sp_read:reset_count_1\\D\ ... expanded.
  Information: Process virtual '\sp_read:reset_count_2\\D\'\sp_read:reset_count_2\\D\ ... expanded.
  Information: Process virtual '\sp_read:counter_read_stateSBV_3\\D\'\sp_read:counter_read_stateSBV_3\\D\ ... expanded.
  Information: Process virtual '\sp_read:counter_read_stateSBV_2\\D\'\sp_read:counter_read_stateSBV_2\\D\ ... expanded.
  Information: Process virtual '\sp_read:counter_read_stateSBV_1\\D\'\sp_read:counter_read_stateSBV_1\\D\ ... expanded.
  Information: Process virtual '\sp_read:counter_read_stateSBV_0\\D\'\sp_read:counter_read_stateSBV_0\\D\ ... expanded.
  Information: Process virtual 'sensor_address_0D'sensor_address_0D ... expanded.
  Information: Process virtual 'sensor_address_1D'sensor_address_1D ... expanded.
  Information: Process virtual 'sensor_address_2D'sensor_address_2D ... expanded.
  Information: Process virtual 'sensor_address_3D'sensor_address_3D ... expanded.
  Information: Process virtual 'sensor_address_4D'sensor_address_4D ... expanded.
  Information: Process virtual 'sensor_address_5D'sensor_address_5D ... expanded.
  Information: Process virtual 'sensor_address_6D'sensor_address_6D ... expanded.
  Information: Process virtual 'sensor_address_7D'sensor_address_7D ... expanded.
  Information: Process virtual '\bp_io:timeout_0\\D\'\bp_io:timeout_0\\D\ ... expanded.
  Information: Process virtual '\bp_io:timeout_1\\D\'\bp_io:timeout_1\\D\ ... expanded.
  Information: Process virtual '\bp_io:timeout_2\\D\'\bp_io:timeout_2\\D\ ... expanded.
  Information: Process virtual 'bp_addr_tristateD'bp_addr_tristateD ... expanded.
  Information: Process virtual 'sensor_to_bp_read_reqD'sensor_to_bp_read_reqD ... expanded.
  Information: Process virtual 'bp_data_tristateD'bp_data_tristateD ... expanded.
  Information: Process virtual 'sensor_to_bp_read_ackD'sensor_to_bp_read_ackD ... expanded.
  Information: Process virtual '\bp_io:bp_access_stateSBV_2\\D\'\bp_io:bp_access_stateSBV_2\\D\ ... expanded.
  Information: Process virtual '\bp_io:bp_access_stateSBV_1\\D\'\bp_io:bp_access_stateSBV_1\\D\ ... expanded.
  Information: Process virtual '\bp_io:bp_access_stateSBV_0\\D\'\bp_io:bp_access_stateSBV_0\\D\ ... expanded.
  Information: Process virtual 'bp_end_address_7D'bp_end_address_7D ... expanded.
  Information: Process virtual 'bp_start_address_7D'bp_start_address_7D ... expanded.
  Information: Process virtual 'bp_end_address_6D'bp_end_address_6D ... expanded.
  Information: Process virtual 'bp_start_address_6D'bp_start_address_6D ... expanded.
  Information: Process virtual 'bp_end_address_5D'bp_end_address_5D ... expanded.
  Information: Process virtual 'bp_start_address_5D'bp_start_address_5D ... expanded.
  Information: Process virtual 'bp_end_address_4D'bp_end_address_4D ... expanded.
  Information: Process virtual 'bp_start_address_4D'bp_start_address_4D ... expanded.
  Information: Process virtual 'bp_end_address_3D'bp_end_address_3D ... expanded.
  Information: Process virtual 'bp_start_address_3D'bp_start_address_3D ... expanded.
  Information: Process virtual 'bp_end_address_2D'bp_end_address_2D ... expanded.
  Information: Process virtual 'bp_start_address_2D'bp_start_address_2D ... expanded.
  Information: Process virtual 'bp_end_address_1D'bp_end_address_1D ... expanded.
  Information: Process virtual 'bp_start_address_1D'bp_start_address_1D ... expanded.
  Information: Process virtual 'bp_end_address_0D'bp_end_address_0D ... expanded.
  Information: Process virtual 'bp_start_address_0D'bp_start_address_0D ... expanded.
  Information: Process virtual 'address_from_pc_0D'address_from_pc_0D ... expanded.
  Information: Process virtual 'address_from_pc_1D'address_from_pc_1D ... expanded.
  Information: Process virtual 'address_from_pc_2D'address_from_pc_2D ... expanded.
  Information: Process virtual 'address_from_pc_3D'address_from_pc_3D ... expanded.
  Information: Process virtual 'address_from_pc_4D'address_from_pc_4D ... expanded.
  Information: Process virtual 'address_from_pc_5D'address_from_pc_5D ... expanded.
  Information: Process virtual 'address_from_pc_6D'address_from_pc_6D ... expanded.
  Information: Process virtual 'address_from_pc_7D'address_from_pc_7D ... expanded.
  Information: Process virtual '\ibus_reader:timeout_0\\D\'\ibus_reader:timeout_0\\D\ ... expanded.
  Information: Process virtual '\ibus_reader:timeout_1\\D\'\ibus_reader:timeout_1\\D\ ... expanded.
  Information: Process virtual '\ibus_reader:timeout_2\\D\'\ibus_reader:timeout_2\\D\ ... expanded.
  Information: Process virtual '\ibus_reader:timeout_3\\D\'\ibus_reader:timeout_3\\D\ ... expanded.
  Information: Process virtual '\ibus_reader:this_is_a_ctrl_transaction\\D\'\ibus_reader:this_is_a_ctrl_transaction\\D\ ... expanded.
  Information: Process virtual '\ibus_reader:il_read_stateSBV_2\\D\'\ibus_reader:il_read_stateSBV_2\\D\ ... expanded.
  Information: Process virtual '\ibus_reader:il_read_stateSBV_1\\D\'\ibus_reader:il_read_stateSBV_1\\D\ ... expanded.
  Information: Process virtual '\ibus_reader:il_read_stateSBV_0\\D\'\ibus_reader:il_read_stateSBV_0\\D\ ... expanded.
  Information: Process virtual '\ibus_writer:timeout_0\\D\'\ibus_writer:timeout_0\\D\ ... expanded.
  Information: Process virtual '\ibus_writer:timeout_1\\D\'\ibus_writer:timeout_1\\D\ ... expanded.
  Information: Process virtual '\ibus_writer:timeout_2\\D\'\ibus_writer:timeout_2\\D\ ... expanded.
  Information: Process virtual '\ibus_writer:timeout_3\\D\'\ibus_writer:timeout_3\\D\ ... expanded.
  Information: Process virtual '\ibus_writer:iu_writeSBV_1\\D\'\ibus_writer:iu_writeSBV_1\\D\ ... expanded.
  Information: Process virtual '\ibus_writer:iu_writeSBV_0\\D\'\ibus_writer:iu_writeSBV_0\\D\ ... expanded.
  Information: Process virtual 'sensor_data_0D'sensor_data_0D ... expanded.
  Information: Process virtual 'data_from_pc_0D'data_from_pc_0D ... expanded.
  Information: Process virtual 'sensor_data_1D'sensor_data_1D ... expanded.
  Information: Process virtual 'data_from_pc_1D'data_from_pc_1D ... expanded.
  Information: Process virtual 'sensor_data_2D'sensor_data_2D ... expanded.
  Information: Process virtual 'data_from_pc_2D'data_from_pc_2D ... expanded.
  Information: Process virtual 'sensor_data_3D'sensor_data_3D ... expanded.
  Information: Process virtual 'data_from_pc_3D'data_from_pc_3D ... expanded.
  Information: Process virtual 'sensor_data_4D'sensor_data_4D ... expanded.
  Information: Process virtual 'data_from_pc_4D'data_from_pc_4D ... expanded.
  Information: Process virtual 'sensor_data_5D'sensor_data_5D ... expanded.
  Information: Process virtual 'data_from_pc_5D'data_from_pc_5D ... expanded.
  Information: Process virtual 'sensor_data_6D'sensor_data_6D ... expanded.
  Information: Process virtual 'data_from_pc_6D'data_from_pc_6D ... expanded.
  Information: Process virtual 'sensor_data_7D'sensor_data_7D ... expanded.
  Information: Process virtual 'data_from_pc_7D'data_from_pc_7D ... expanded.
  Information: Process virtual 'sensor_data_8D'sensor_data_8D ... expanded.
  Information: Process virtual 'data_from_pc_8D'data_from_pc_8D ... expanded.
  Information: Process virtual 'sensor_data_9D'sensor_data_9D ... expanded.
  Information: Process virtual 'data_from_pc_9D'data_from_pc_9D ... expanded.
  Information: Process virtual 'sensor_data_10D'sensor_data_10D ... expanded.
  Information: Process virtual 'data_from_pc_10D'data_from_pc_10D ... expanded.
  Information: Process virtual 'sensor_data_11D'sensor_data_11D ... expanded.
  Information: Process virtual 'data_from_pc_11D'data_from_pc_11D ... expanded.
  Information: Process virtual 'sensor_data_12D'sensor_data_12D ... expanded.
  Information: Process virtual 'data_from_pc_12D'data_from_pc_12D ... expanded.
  Information: Process virtual 'sensor_data_13D'sensor_data_13D ... expanded.
  Information: Process virtual 'data_from_pc_13D'data_from_pc_13D ... expanded.
  Information: Process virtual 'sensor_data_14D'sensor_data_14D ... expanded.
  Information: Process virtual 'data_from_pc_14D'data_from_pc_14D ... expanded.
  Information: Process virtual 'sensor_data_15D'sensor_data_15D ... expanded.
  Information: Process virtual 'data_from_pc_15D'data_from_pc_15D ... expanded.
  Information: Process virtual 'sensor_to_ibus_reqD'sensor_to_ibus_reqD ... expanded.
  Information: Process virtual 'from_pc_reqD'from_pc_reqD ... expanded.
  Information: Process virtual 'write_to_bp_ackD'write_to_bp_ackD ... expanded.
  Information: Process virtual 'to_pc_ackD'to_pc_ackD ... expanded.
  Information: Process virtual 'loopback_stateD'loopback_stateD ... expanded.
  Information: Process virtual 'il_ackD'il_ackD ... expanded.
  Information: Process virtual 'il_tristateD'il_tristateD ... expanded.
  Information: Process virtual 'this_chip_selectedD'this_chip_selectedD ... expanded.
  Information: Process virtual '\bpctrl(0)D\'\bpctrl(0)D\ ... expanded.
  Information: Process virtual '\bpctrl(2)D\'\bpctrl(2)D\ ... expanded.
  Information: Process virtual '\bpctrl(3)D\'\bpctrl(3)D\ ... expanded.
  Information: Process virtual '\bpaddr(0)D\'\bpaddr(0)D\ ... expanded.
  Information: Process virtual '\bpaddr(1)D\'\bpaddr(1)D\ ... expanded.
  Information: Process virtual '\bpaddr(2)D\'\bpaddr(2)D\ ... expanded.
  Information: Process virtual '\bpaddr(3)D\'\bpaddr(3)D\ ... expanded.
  Information: Process virtual '\bpaddr(4)D\'\bpaddr(4)D\ ... expanded.
  Information: Process virtual '\bpaddr(5)D\'\bpaddr(5)D\ ... expanded.
  Information: Process virtual '\bpaddr(6)D\'\bpaddr(6)D\ ... expanded.
  Information: Process virtual '\bpaddr(7)D\'\bpaddr(7)D\ ... expanded.
  Information: Process virtual 'ao_to_pc_strobeD'ao_to_pc_strobeD ... expanded.
  Information: Process virtual '\d(16)D\'\d(16)D\ ... expanded.
  Information: Process virtual '\d(17)D\'\d(17)D\ ... expanded.
  Information: Process virtual '\d(18)D\'\d(18)D\ ... expanded.
  Information: Process virtual '\d(19)D\'\d(19)D\ ... expanded.
  Information: Process virtual '\d(20)D\'\d(20)D\ ... expanded.
  Information: Process virtual '\d(21)D\'\d(21)D\ ... expanded.
  Information: Process virtual '\d(22)D\'\d(22)D\ ... expanded.
  Information: Process virtual '\d(23)D\'\d(23)D\ ... expanded.
  Information: Process virtual '\d(24)D\'\d(24)D\ ... expanded.
  Information: Process virtual '\d(25)D\'\d(25)D\ ... expanded.
  Information: Process virtual '\d(26)D\'\d(26)D\ ... expanded.
  Information: Process virtual '\d(27)D\'\d(27)D\ ... expanded.
  Information: Process virtual '\d(28)D\'\d(28)D\ ... expanded.
  Information: Process virtual '\d(29)D\'\d(29)D\ ... expanded.
  Information: Process virtual '\d(30)D\'\d(30)D\ ... expanded.
  Information: Process virtual '\d(31)D\'\d(31)D\ ... expanded.
  Information: Process virtual 'led1D'led1D ... expanded.
  Information: Process virtual '\sp_read:old_phase\\S\'\sp_read:old_phase\\S\ ... expanded.
  Information: Process virtual '\sp_read:old_phase\\R\'\sp_read:old_phase\\R\ ... expanded.
  Information: Process virtual '\sp_read:delay_count_0\' ... converted to NODE.
  Information: Process virtual '\sp_read:delay_count_1\' ... converted to NODE.
  Information: Process virtual '\sp_read:delay_count_2\' ... converted to NODE.
  Information: Process virtual '\sp_read:delay_count_3\' ... converted to NODE.
  Information: Process virtual '\sp_read:delay_count_4\' ... converted to NODE.
  Information: Process virtual '\sp_read:delay_count_5\' ... converted to NODE.
  Information: Process virtual '\sp_read:delay_count_6\' ... converted to NODE.
  Information: Process virtual '\sp_read:delay_count_7\' ... converted to NODE.
  Information: Process virtual '\sp_read:delay_count_8\' ... converted to NODE.
  Information: Process virtual '\sp_read:delay_count_9\' ... converted to NODE.
  Information: Process virtual '\sp_read:counter_address_0\' ... converted to NODE.
  Information: Process virtual '\sp_read:counter_address_1\' ... converted to NODE.
  Information: Process virtual '\sp_read:counter_address_2\' ... converted to NODE.
  Information: Process virtual '\sp_read:counter_address_3\' ... converted to NODE.
  Information: Process virtual '\sp_read:counter_address_4\' ... converted to NODE.
  Information: Process virtual '\sp_read:counter_address_5\' ... converted to NODE.
  Information: Process virtual '\sp_read:counter_address_6\' ... converted to NODE.
  Information: Process virtual '\sp_read:counter_address_7\' ... converted to NODE.
  Information: Process virtual '\sp_read:reset_count_0\' ... converted to NODE.
  Information: Process virtual '\sp_read:reset_count_1\' ... converted to NODE.
  Information: Process virtual '\sp_read:reset_count_2\' ... converted to NODE.
  Information: Process virtual '\sp_read:old_phase\' ... converted to NODE.
  Information: Process virtual '\sp_read:counter_read_stateSBV_3\' ... converted to NODE.
  Information: Process virtual '\sp_read:counter_read_stateSBV_2\' ... converted to NODE.
  Information: Process virtual '\sp_read:counter_read_stateSBV_1\' ... converted to NODE.
  Information: Process virtual '\sp_read:counter_read_stateSBV_0\' ... converted to NODE.
  Information: Process virtual 'sensor_address_0' ... converted to NODE.
  Information: Process virtual 'sensor_address_1' ... converted to NODE.
  Information: Process virtual 'sensor_address_2' ... converted to NODE.
  Information: Process virtual 'sensor_address_3' ... converted to NODE.
  Information: Process virtual 'sensor_address_4' ... converted to NODE.
  Information: Process virtual 'sensor_address_5' ... converted to NODE.
  Information: Process virtual 'sensor_address_6' ... converted to NODE.
  Information: Process virtual 'sensor_address_7' ... converted to NODE.
  Information: Process virtual '\bp_io:timeout_0\' ... converted to NODE.
  Information: Process virtual '\bp_io:timeout_1\' ... converted to NODE.
  Information: Process virtual '\bp_io:timeout_2\' ... converted to NODE.
  Information: Process virtual 'bp_addr_tristate'bp_addr_tristate ... expanded.
  Information: Process virtual 'sensor_to_bp_read_req' ... converted to NODE.
  Information: Process virtual 'bp_data_tristate'bp_data_tristate ... expanded.
  Information: Process virtual 'sensor_to_bp_read_ack' ... converted to NODE.
  Information: Process virtual '\bp_io:bp_access_stateSBV_2\' ... converted to NODE.
  Information: Process virtual '\bp_io:bp_access_stateSBV_1\' ... converted to NODE.
  Information: Process virtual '\bp_io:bp_access_stateSBV_0\' ... converted to NODE.
  Information: Process virtual 'bp_end_address_7' ... converted to NODE.
  Information: Process virtual 'bp_start_address_7' ... converted to NODE.
  Information: Process virtual 'bp_end_address_6' ... converted to NODE.
  Information: Process virtual 'bp_start_address_6' ... converted to NODE.
  Information: Process virtual 'bp_end_address_5' ... converted to NODE.
  Information: Process virtual 'bp_start_address_5' ... converted to NODE.
  Information: Process virtual 'bp_end_address_4' ... converted to NODE.
  Information: Process virtual 'bp_start_address_4' ... converted to NODE.
  Information: Process virtual 'bp_end_address_3' ... converted to NODE.
  Information: Process virtual 'bp_start_address_3' ... converted to NODE.
  Information: Process virtual 'bp_end_address_2' ... converted to NODE.
  Information: Process virtual 'bp_start_address_2' ... converted to NODE.
  Information: Process virtual 'bp_end_address_1' ... converted to NODE.
  Information: Process virtual 'bp_start_address_1' ... converted to NODE.
  Information: Process virtual 'bp_end_address_0' ... converted to NODE.
  Information: Process virtual 'bp_start_address_0' ... converted to NODE.
  Information: Process virtual 'address_from_pc_0' ... converted to NODE.
  Information: Process virtual 'address_from_pc_1' ... converted to NODE.
  Information: Process virtual 'address_from_pc_2' ... converted to NODE.
  Information: Process virtual 'address_from_pc_3' ... converted to NODE.
  Information: Process virtual 'address_from_pc_4' ... converted to NODE.
  Information: Process virtual 'address_from_pc_5' ... converted to NODE.
  Information: Process virtual 'address_from_pc_6' ... converted to NODE.
  Information: Process virtual 'address_from_pc_7' ... converted to NODE.
  Information: Process virtual '\ibus_reader:timeout_0\' ... converted to NODE.
  Information: Process virtual '\ibus_reader:timeout_1\' ... converted to NODE.
  Information: Process virtual '\ibus_reader:timeout_2\' ... converted to NODE.
  Information: Process virtual '\ibus_reader:timeout_3\' ... converted to NODE.
  Information: Process virtual '\ibus_reader:this_is_a_ctrl_transaction\' ... converted to NODE.
  Information: Process virtual '\ibus_reader:il_read_stateSBV_2\' ... converted to NODE.
  Information: Process virtual '\ibus_reader:il_read_stateSBV_1\' ... converted to NODE.
  Information: Process virtual '\ibus_reader:il_read_stateSBV_0\' ... converted to NODE.
  Information: Process virtual '\ibus_writer:timeout_0\' ... converted to NODE.
  Information: Process virtual '\ibus_writer:timeout_1\' ... converted to NODE.
  Information: Process virtual '\ibus_writer:timeout_2\' ... converted to NODE.
  Information: Process virtual '\ibus_writer:timeout_3\' ... converted to NODE.
  Information: Process virtual '\ibus_writer:iu_writeSBV_1\' ... converted to NODE.
  Information: Process virtual '\ibus_writer:iu_writeSBV_0\' ... converted to NODE.
  Information: Process virtual 'sensor_data_0' ... converted to NODE.
  Information: Process virtual 'data_from_pc_0'data_from_pc_0 ... expanded.
  Information: Process virtual 'sensor_data_1' ... converted to NODE.
  Information: Process virtual 'data_from_pc_1'data_from_pc_1 ... expanded.
  Information: Process virtual 'sensor_data_2' ... converted to NODE.
  Information: Process virtual 'data_from_pc_2'data_from_pc_2 ... expanded.
  Information: Process virtual 'sensor_data_3' ... converted to NODE.
  Information: Process virtual 'data_from_pc_3'data_from_pc_3 ... expanded.
  Information: Process virtual 'sensor_data_4' ... converted to NODE.
  Information: Process virtual 'data_from_pc_4'data_from_pc_4 ... expanded.
  Information: Process virtual 'sensor_data_5' ... converted to NODE.
  Information: Process virtual 'data_from_pc_5'data_from_pc_5 ... expanded.
  Information: Process virtual 'sensor_data_6' ... converted to NODE.
  Information: Process virtual 'data_from_pc_6'data_from_pc_6 ... expanded.
  Information: Process virtual 'sensor_data_7' ... converted to NODE.
  Information: Process virtual 'data_from_pc_7'data_from_pc_7 ... expanded.
  Information: Process virtual 'sensor_data_8' ... converted to NODE.
  Information: Process virtual 'data_from_pc_8'data_from_pc_8 ... expanded.
  Information: Process virtual 'sensor_data_9' ... converted to NODE.
  Information: Process virtual 'data_from_pc_9'data_from_pc_9 ... expanded.
  Information: Process virtual 'sensor_data_10' ... converted to NODE.
  Information: Process virtual 'data_from_pc_10'data_from_pc_10 ... expanded.
  Information: Process virtual 'sensor_data_11' ... converted to NODE.
  Information: Process virtual 'data_from_pc_11'data_from_pc_11 ... expanded.
  Information: Process virtual 'sensor_data_12' ... converted to NODE.
  Information: Process virtual 'data_from_pc_12'data_from_pc_12 ... expanded.
  Information: Process virtual 'sensor_data_13' ... converted to NODE.
  Information: Process virtual 'data_from_pc_13' ... converted to NODE.
  Information: Process virtual 'sensor_data_14' ... converted to NODE.
  Information: Process virtual 'data_from_pc_14' ... converted to NODE.
  Information: Process virtual 'sensor_data_15' ... converted to NODE.
  Information: Process virtual 'data_from_pc_15' ... converted to NODE.
  Information: Process virtual 'sensor_to_ibus_req' ... converted to NODE.
  Information: Process virtual 'from_pc_req' ... converted to NODE.
  Information: Process virtual 'write_to_bp_ack' ... converted to NODE.
  Information: Process virtual 'to_pc_ack' ... converted to NODE.
  Information: Process virtual 'loopback_state' ... converted to NODE.
  Information: Process virtual 'il_tristate' ... converted to NODE.
  Information: Process virtual 'this_chip_selected' ... converted to NODE.
  Information: Process virtual 'tristate_stateSBV_0' ... converted to NODE.
  Information: Generating both D & T register equations for signal bpctrl(0).D[11]
  Information: Expanding XOR equation found on signal bpctrl(0).T[11]
  Information: Generating both D & T register equations for signal bpctrl(2).D[13]
  Information: Expanding XOR equation found on signal bpctrl(2).T[13]
  Information: Generating both D & T register equations for signal bpctrl(3).D[14]
  Information: Expanding XOR equation found on signal bpctrl(3).T[14]
  Information: Generating both D & T register equations for signal bpctrl(4).D[15]
  Information: Expanding XOR equation found on signal bpctrl(4).T[15]
  Information: Generating both D & T register equations for signal bpctrl(5).D[16]
  Information: Expanding XOR equation found on signal bpctrl(5).T[16]
  Information: Generating both D & T register equations for signal bpctrl(6).D[17]
  Information: Expanding XOR equation found on signal bpctrl(6).T[17]
  Information: Generating both D & T register equations for signal bpctrl(7).D[18]
  Information: Expanding XOR equation found on signal bpctrl(7).T[18]
  Information: Generating both D & T register equations for signal bpctrl(8).D[23]
  Information: Expanding XOR equation found on signal bpctrl(8).T[23]
  Information: Generating both D & T register equations for signal bpctrl(10).D[25]
  Information: Expanding XOR equation found on signal bpctrl(10).T[25]
  Information: Generating both D & T register equations for signal bpctrl(11).D[26]
  Information: Expanding XOR equation found on signal bpctrl(11).T[26]
  Information: Generating both D & T register equations for signal bpaddr(0).D[32]
  Information: Expanding XOR equation found on signal bpaddr(0).T[32]
  Information: Generating both D & T register equations for signal bpaddr(1).D[33]
  Information: Expanding XOR equation found on signal bpaddr(1).T[33]
  Information: Generating both D & T register equations for signal bpaddr(2).D[34]
  Information: Expanding XOR equation found on signal bpaddr(2).T[34]
  Information: Generating both D & T register equations for signal bpaddr(3).D[35]
  Information: Expanding XOR equation found on signal bpaddr(3).T[35]
  Information: Generating both D & T register equations for signal bpaddr(4).D[36]
  Information: Expanding XOR equation found on signal bpaddr(4).T[36]
  Information: Generating both D & T register equations for signal bpaddr(5).D[37]
  Information: Expanding XOR equation found on signal bpaddr(5).T[37]
  Information: Generating both D & T register equations for signal bpaddr(6).D[38]
  Information: Expanding XOR equation found on signal bpaddr(6).T[38]
  Information: Generating both D & T register equations for signal bpaddr(7).D[39]
  Information: Expanding XOR equation found on signal bpaddr(7).T[39]
  Information: Generating both D & T register equations for signal bpd_h_tristate.D[43]
  Information: Expanding XOR equation found on signal bpd_h_tristate.T[43]
  Information: Generating both D & T register equations for signal bpaddr_tristate.D[44]
  Information: Expanding XOR equation found on signal bpaddr_tristate.T[44]
  Information: Generating both D & T register equations for signal led1.D[47]
  Information: Expanding XOR equation found on signal led1.T[47]
  Information: Generating both D & T register equations for signal ao_to_pc_strobe.D[93]
  Information: Expanding XOR equation found on signal ao_to_pc_strobe.T[93]
  Information: Generating both D & T register equations for signal ao_from_pc_ack.D[94]
  Information: Expanding XOR equation found on signal ao_from_pc_ack.T[94]
  Information: Generating both D & T register equations for signal d(16).D[122]
  Information: Expanding XOR equation found on signal d(16).T[122]
  Information: Generating both D & T register equations for signal d(17).D[123]
  Information: Expanding XOR equation found on signal d(17).T[123]
  Information: Generating both D & T register equations for signal d(18).D[124]
  Information: Expanding XOR equation found on signal d(18).T[124]
  Information: Generating both D & T register equations for signal d(19).D[125]
  Information: Expanding XOR equation found on signal d(19).T[125]
  Information: Generating both D & T register equations for signal d(20).D[126]
  Information: Expanding XOR equation found on signal d(20).T[126]
  Information: Generating both D & T register equations for signal d(21).D[127]
  Information: Expanding XOR equation found on signal d(21).T[127]
  Information: Generating both D & T register equations for signal d(22).D[128]
  Information: Expanding XOR equation found on signal d(22).T[128]
  Information: Generating both D & T register equations for signal d(23).D[129]
  Information: Expanding XOR equation found on signal d(23).T[129]
  Information: Generating both D & T register equations for signal d(24).D[131]
  Information: Expanding XOR equation found on signal d(24).T[131]
  Information: Generating both D & T register equations for signal d(25).D[132]
  Information: Expanding XOR equation found on signal d(25).T[132]
  Information: Generating both D & T register equations for signal d(26).D[133]
  Information: Expanding XOR equation found on signal d(26).T[133]
  Information: Generating both D & T register equations for signal d(27).D[134]
  Information: Expanding XOR equation found on signal d(27).T[134]
  Information: Generating both D & T register equations for signal d(28).D[135]
  Information: Expanding XOR equation found on signal d(28).T[135]
  Information: Generating both D & T register equations for signal d(29).D[136]
  Information: Expanding XOR equation found on signal d(29).T[136]
  Information: Generating both D & T register equations for signal d(30).D[137]
  Information: Expanding XOR equation found on signal d(30).T[137]
  Information: Generating both D & T register equations for signal d(31).D[138]
  Information: Expanding XOR equation found on signal d(31).T[138]
  Information: Generating both D & T register equations for signal bpd(10).D[154]
  Information: Expanding XOR equation found on signal bpd(10).T[154]
  Information: Generating both D & T register equations for signal bpd(11).D[155]
  Information: Expanding XOR equation found on signal bpd(11).T[155]
  Information: Generating both D & T register equations for signal bpd(12).D[156]
  Information: Expanding XOR equation found on signal bpd(12).T[156]
  Information: Generating both D & T register equations for signal bpd(13).D[157]
  Information: Expanding XOR equation found on signal bpd(13).T[157]
  Information: Generating both D & T register equations for signal bpd(14).D[158]
  Information: Expanding XOR equation found on signal bpd(14).T[158]
  Information: Generating both D & T register equations for signal bpd(15).D[159]
  Information: Expanding XOR equation found on signal bpd(15).T[159]
  Information: Generating both D & T register equations for signal \sp_read:delay_count_0\.D
  Information: Expanding XOR equation found on signal \sp_read:delay_count_0\.T
  Information: Generating both D & T register equations for signal \sp_read:delay_count_1\.D
  Information: Expanding XOR equation found on signal \sp_read:delay_count_1\.T
  Information: Generating both D & T register equations for signal \sp_read:delay_count_2\.D
  Information: Expanding XOR equation found on signal \sp_read:delay_count_2\.T
  Information: Generating both D & T register equations for signal \sp_read:delay_count_3\.D
  Information: Expanding XOR equation found on signal \sp_read:delay_count_3\.T
  Information: Generating both D & T register equations for signal \sp_read:delay_count_4\.D
  Information: Expanding XOR equation found on signal \sp_read:delay_count_4\.T
  Information: Generating both D & T register equations for signal \sp_read:delay_count_5\.D
  Information: Expanding XOR equation found on signal \sp_read:delay_count_5\.T
  Information: Generating both D & T register equations for signal \sp_read:delay_count_6\.D
  Information: Expanding XOR equation found on signal \sp_read:delay_count_6\.T
  Information: Generating both D & T register equations for signal \sp_read:delay_count_7\.D
  Information: Expanding XOR equation found on signal \sp_read:delay_count_7\.T
  Information: Generating both D & T register equations for signal \sp_read:delay_count_8\.D
  Information: Expanding XOR equation found on signal \sp_read:delay_count_8\.T
  Information: Generating both D & T register equations for signal \sp_read:delay_count_9\.D
  Information: Expanding XOR equation found on signal \sp_read:delay_count_9\.T
  Information: Generating both D & T register equations for signal \sp_read:counter_address_0\.D
  Information: Expanding XOR equation found on signal \sp_read:counter_address_0\.T
  Information: Generating both D & T register equations for signal \sp_read:counter_address_1\.D
  Information: Expanding XOR equation found on signal \sp_read:counter_address_1\.T
  Information: Generating both D & T register equations for signal \sp_read:counter_address_2\.D
  Information: Expanding XOR equation found on signal \sp_read:counter_address_2\.T
  Information: Generating both D & T register equations for signal \sp_read:counter_address_3\.D
  Information: Expanding XOR equation found on signal \sp_read:counter_address_3\.T
  Information: Generating both D & T register equations for signal \sp_read:counter_address_4\.D
  Information: Expanding XOR equation found on signal \sp_read:counter_address_4\.T
  Information: Generating both D & T register equations for signal \sp_read:counter_address_5\.D
  Information: Expanding XOR equation found on signal \sp_read:counter_address_5\.T
  Information: Generating both D & T register equations for signal \sp_read:counter_address_6\.D
  Information: Expanding XOR equation found on signal \sp_read:counter_address_6\.T
  Information: Generating both D & T register equations for signal \sp_read:counter_address_7\.D
  Information: Expanding XOR equation found on signal \sp_read:counter_address_7\.T
  Information: Generating both D & T register equations for signal \sp_read:reset_count_0\.D
  Information: Expanding XOR equation found on signal \sp_read:reset_count_0\.T
  Information: Generating both D & T register equations for signal \sp_read:reset_count_1\.D
  Information: Expanding XOR equation found on signal \sp_read:reset_count_1\.T
  Information: Generating both D & T register equations for signal \sp_read:reset_count_2\.D
  Information: Expanding XOR equation found on signal \sp_read:reset_count_2\.T
  Information: Generating both D & T register equations for signal \sp_read:old_phase\.D
  Information: Expanding XOR equation found on signal \sp_read:old_phase\.T
  Information: Generating both D & T register equations for signal \sp_read:counter_read_stateSBV_3\.D
  Information: Expanding XOR equation found on signal \sp_read:counter_read_stateSBV_3\.T
  Information: Generating both D & T register equations for signal \sp_read:counter_read_stateSBV_2\.D
  Information: Expanding XOR equation found on signal \sp_read:counter_read_stateSBV_2\.T
  Information: Generating both D & T register equations for signal \sp_read:counter_read_stateSBV_1\.D
  Information: Expanding XOR equation found on signal \sp_read:counter_read_stateSBV_1\.T
  Information: Generating both D & T register equations for signal \sp_read:counter_read_stateSBV_0\.D
  Information: Expanding XOR equation found on signal \sp_read:counter_read_stateSBV_0\.T
  Information: Generating both D & T register equations for signal sensor_address_0.D
  Information: Expanding XOR equation found on signal sensor_address_0.T
  Information: Generating both D & T register equations for signal sensor_address_1.D
  Information: Expanding XOR equation found on signal sensor_address_1.T
  Information: Generating both D & T register equations for signal sensor_address_2.D
  Information: Expanding XOR equation found on signal sensor_address_2.T
  Information: Generating both D & T register equations for signal sensor_address_3.D
  Information: Expanding XOR equation found on signal sensor_address_3.T
  Information: Generating both D & T register equations for signal sensor_address_4.D
  Information: Expanding XOR equation found on signal sensor_address_4.T
  Information: Generating both D & T register equations for signal sensor_address_5.D
  Information: Expanding XOR equation found on signal sensor_address_5.T
  Information: Generating both D & T register equations for signal sensor_address_6.D
  Information: Expanding XOR equation found on signal sensor_address_6.T
  Information: Generating both D & T register equations for signal sensor_address_7.D
  Information: Expanding XOR equation found on signal sensor_address_7.T
  Information: Generating both D & T register equations for signal \bp_io:timeout_0\.D
  Information: Expanding XOR equation found on signal \bp_io:timeout_0\.T
  Information: Generating both D & T register equations for signal \bp_io:timeout_1\.D
  Information: Expanding XOR equation found on signal \bp_io:timeout_1\.T
  Information: Generating both D & T register equations for signal \bp_io:timeout_2\.D
  Information: Expanding XOR equation found on signal \bp_io:timeout_2\.T
  Information: Generating both D & T register equations for signal sensor_to_bp_read_req.D
  Information: Expanding XOR equation found on signal sensor_to_bp_read_req.T
  Information: Generating both D & T register equations for signal sensor_to_bp_read_ack.D
  Information: Expanding XOR equation found on signal sensor_to_bp_read_ack.T
  Information: Generating both D & T register equations for signal \bp_io:bp_access_stateSBV_2\.D
  Information: Expanding XOR equation found on signal \bp_io:bp_access_stateSBV_2\.T
  Information: Generating both D & T register equations for signal \bp_io:bp_access_stateSBV_1\.D
  Information: Expanding XOR equation found on signal \bp_io:bp_access_stateSBV_1\.T
  Information: Generating both D & T register equations for signal \bp_io:bp_access_stateSBV_0\.D
  Information: Expanding XOR equation found on signal \bp_io:bp_access_stateSBV_0\.T
  Information: Generating both D & T register equations for signal bp_end_address_7.D
  Information: Expanding XOR equation found on signal bp_end_address_7.T
  Information: Generating both D & T register equations for signal bp_start_address_7.D
  Information: Expanding XOR equation found on signal bp_start_address_7.T
  Information: Generating both D & T register equations for signal bp_end_address_6.D
  Information: Expanding XOR equation found on signal bp_end_address_6.T
  Information: Generating both D & T register equations for signal bp_start_address_6.D
  Information: Expanding XOR equation found on signal bp_start_address_6.T
  Information: Generating both D & T register equations for signal bp_end_address_5.D
  Information: Expanding XOR equation found on signal bp_end_address_5.T
  Information: Generating both D & T register equations for signal bp_start_address_5.D
  Information: Expanding XOR equation found on signal bp_start_address_5.T
  Information: Generating both D & T register equations for signal bp_end_address_4.D
  Information: Expanding XOR equation found on signal bp_end_address_4.T
  Information: Generating both D & T register equations for signal bp_start_address_4.D
  Information: Expanding XOR equation found on signal bp_start_address_4.T
  Information: Generating both D & T register equations for signal bp_end_address_3.D
  Information: Expanding XOR equation found on signal bp_end_address_3.T
  Information: Generating both D & T register equations for signal bp_start_address_3.D
  Information: Expanding XOR equation found on signal bp_start_address_3.T
  Information: Generating both D & T register equations for signal bp_end_address_2.D
  Information: Expanding XOR equation found on signal bp_end_address_2.T
  Information: Generating both D & T register equations for signal bp_start_address_2.D
  Information: Expanding XOR equation found on signal bp_start_address_2.T
  Information: Generating both D & T register equations for signal bp_end_address_1.D
  Information: Expanding XOR equation found on signal bp_end_address_1.T
  Information: Generating both D & T register equations for signal bp_start_address_1.D
  Information: Expanding XOR equation found on signal bp_start_address_1.T
  Information: Generating both D & T register equations for signal bp_end_address_0.D
  Information: Expanding XOR equation found on signal bp_end_address_0.T
  Information: Generating both D & T register equations for signal bp_start_address_0.D
  Information: Expanding XOR equation found on signal bp_start_address_0.T
  Information: Generating both D & T register equations for signal address_from_pc_0.D
  Information: Expanding XOR equation found on signal address_from_pc_0.T
  Information: Generating both D & T register equations for signal address_from_pc_1.D
  Information: Expanding XOR equation found on signal address_from_pc_1.T
  Information: Generating both D & T register equations for signal address_from_pc_2.D
  Information: Expanding XOR equation found on signal address_from_pc_2.T
  Information: Generating both D & T register equations for signal address_from_pc_3.D
  Information: Expanding XOR equation found on signal address_from_pc_3.T
  Information: Generating both D & T register equations for signal address_from_pc_4.D
  Information: Expanding XOR equation found on signal address_from_pc_4.T
  Information: Generating both D & T register equations for signal address_from_pc_5.D
  Information: Expanding XOR equation found on signal address_from_pc_5.T
  Information: Generating both D & T register equations for signal address_from_pc_6.D
  Information: Expanding XOR equation found on signal address_from_pc_6.T
  Information: Generating both D & T register equations for signal address_from_pc_7.D
  Information: Expanding XOR equation found on signal address_from_pc_7.T
  Information: Generating both D & T register equations for signal \ibus_reader:timeout_0\.D
  Information: Expanding XOR equation found on signal \ibus_reader:timeout_0\.T
  Information: Generating both D & T register equations for signal \ibus_reader:timeout_1\.D
  Information: Expanding XOR equation found on signal \ibus_reader:timeout_1\.T
  Information: Generating both D & T register equations for signal \ibus_reader:timeout_2\.D
  Information: Expanding XOR equation found on signal \ibus_reader:timeout_2\.T
  Information: Generating both D & T register equations for signal \ibus_reader:timeout_3\.D
  Information: Expanding XOR equation found on signal \ibus_reader:timeout_3\.T
  Information: Generating both D & T register equations for signal \ibus_reader:this_is_a_ctrl_transaction\.D
  Information: Expanding XOR equation found on signal \ibus_reader:this_is_a_ctrl_transaction\.T
  Information: Generating both D & T register equations for signal \ibus_reader:il_read_stateSBV_2\.D
  Information: Expanding XOR equation found on signal \ibus_reader:il_read_stateSBV_2\.T
  Information: Generating both D & T register equations for signal \ibus_reader:il_read_stateSBV_1\.D
  Information: Expanding XOR equation found on signal \ibus_reader:il_read_stateSBV_1\.T
  Information: Generating both D & T register equations for signal \ibus_reader:il_read_stateSBV_0\.D
  Information: Expanding XOR equation found on signal \ibus_reader:il_read_stateSBV_0\.T
  Information: Generating both D & T register equations for signal \ibus_writer:timeout_0\.D
  Information: Expanding XOR equation found on signal \ibus_writer:timeout_0\.T
  Information: Generating both D & T register equations for signal \ibus_writer:timeout_1\.D
  Information: Expanding XOR equation found on signal \ibus_writer:timeout_1\.T
  Information: Generating both D & T register equations for signal \ibus_writer:timeout_2\.D
  Information: Expanding XOR equation found on signal \ibus_writer:timeout_2\.T
  Information: Generating both D & T register equations for signal \ibus_writer:timeout_3\.D
  Information: Expanding XOR equation found on signal \ibus_writer:timeout_3\.T
  Information: Generating both D & T register equations for signal \ibus_writer:iu_writeSBV_1\.D
  Information: Expanding XOR equation found on signal \ibus_writer:iu_writeSBV_1\.T
  Information: Generating both D & T register equations for signal \ibus_writer:iu_writeSBV_0\.D
  Information: Expanding XOR equation found on signal \ibus_writer:iu_writeSBV_0\.T
  Information: Generating both D & T register equations for signal sensor_data_0.D
  Information: Expanding XOR equation found on signal sensor_data_0.T
  Information: Generating both D & T register equations for signal sensor_data_1.D
  Information: Expanding XOR equation found on signal sensor_data_1.T
  Information: Generating both D & T register equations for signal sensor_data_2.D
  Information: Expanding XOR equation found on signal sensor_data_2.T
  Information: Generating both D & T register equations for signal sensor_data_3.D
  Information: Expanding XOR equation found on signal sensor_data_3.T
  Information: Generating both D & T register equations for signal sensor_data_4.D
  Information: Expanding XOR equation found on signal sensor_data_4.T
  Information: Generating both D & T register equations for signal sensor_data_5.D
  Information: Expanding XOR equation found on signal sensor_data_5.T
  Information: Generating both D & T register equations for signal sensor_data_6.D
  Information: Expanding XOR equation found on signal sensor_data_6.T
  Information: Generating both D & T register equations for signal sensor_data_7.D
  Information: Expanding XOR equation found on signal sensor_data_7.T
  Information: Generating both D & T register equations for signal sensor_data_8.D
  Information: Expanding XOR equation found on signal sensor_data_8.T
  Information: Generating both D & T register equations for signal sensor_data_9.D
  Information: Expanding XOR equation found on signal sensor_data_9.T
  Information: Generating both D & T register equations for signal sensor_data_10.D
  Information: Expanding XOR equation found on signal sensor_data_10.T
  Information: Generating both D & T register equations for signal sensor_data_11.D
  Information: Expanding XOR equation found on signal sensor_data_11.T
  Information: Generating both D & T register equations for signal sensor_data_12.D
  Information: Expanding XOR equation found on signal sensor_data_12.T
  Information: Generating both D & T register equations for signal sensor_data_13.D
  Information: Expanding XOR equation found on signal sensor_data_13.T
  Information: Generating both D & T register equations for signal data_from_pc_13.D
  Information: Expanding XOR equation found on signal data_from_pc_13.T
  Information: Generating both D & T register equations for signal sensor_data_14.D
  Information: Expanding XOR equation found on signal sensor_data_14.T
  Information: Generating both D & T register equations for signal data_from_pc_14.D
  Information: Expanding XOR equation found on signal data_from_pc_14.T
  Information: Generating both D & T register equations for signal sensor_data_15.D
  Information: Expanding XOR equation found on signal sensor_data_15.T
  Information: Generating both D & T register equations for signal data_from_pc_15.D
  Information: Expanding XOR equation found on signal data_from_pc_15.T
  Information: Generating both D & T register equations for signal sensor_to_ibus_req.D
  Information: Expanding XOR equation found on signal sensor_to_ibus_req.T
  Information: Generating both D & T register equations for signal from_pc_req.D
  Information: Expanding XOR equation found on signal from_pc_req.T
  Information: Generating both D & T register equations for signal write_to_bp_ack.D
  Information: Expanding XOR equation found on signal write_to_bp_ack.T
  Information: Generating both D & T register equations for signal to_pc_ack.D
  Information: Expanding XOR equation found on signal to_pc_ack.T
  Information: Generating both D & T register equations for signal loopback_state.D
  Information: Expanding XOR equation found on signal loopback_state.T
  Information: Generating both D & T register equations for signal il_tristate.D
  Information: Expanding XOR equation found on signal il_tristate.T
  Information: Generating both D & T register equations for signal this_chip_selected.D
  Information: Expanding XOR equation found on signal this_chip_selected.T
  Information: Generating both D & T register equations for signal tristate_stateSBV_0.D
  Information: Expanding XOR equation found on signal tristate_stateSBV_0.T
  Information: Optimizing logic without changing polarity for signals:
         \bp_io:bp_access_stateSBV_0\.T \bp_io:bp_access_stateSBV_1\.T
         \bp_io:bp_access_stateSBV_2\.T \bp_io:timeout_0\.T
         \bp_io:timeout_1\.T \bp_io:timeout_2\.T
         \ibus_reader:il_read_stateSBV_0\.T \ibus_reader:il_read_stateSBV_1\.T
         \ibus_reader:il_read_stateSBV_2\.T
         \ibus_reader:this_is_a_ctrl_transaction\.T \ibus_reader:timeout_0\.T
         \ibus_reader:timeout_1\.T \ibus_reader:timeout_2\.T
         \ibus_reader:timeout_3\.T \ibus_writer:iu_writeSBV_0\.T
         \ibus_writer:iu_writeSBV_1\.T \ibus_writer:timeout_0\.T
         \ibus_writer:timeout_1\.T \ibus_writer:timeout_2\.T
         \ibus_writer:timeout_3\.T \sp_read:counter_address_0\.T
         \sp_read:counter_address_1\.T \sp_read:counter_address_2\.T
         \sp_read:counter_address_3\.T \sp_read:counter_address_4\.T
         \sp_read:counter_address_5\.T \sp_read:counter_address_6\.T
         \sp_read:counter_address_7\.T \sp_read:counter_read_stateSBV_0\.T
         \sp_read:counter_read_stateSBV_1\.T
         \sp_read:counter_read_stateSBV_2\.T
         \sp_read:counter_read_stateSBV_3\.T \sp_read:delay_count_0\.T
         \sp_read:delay_count_1\.T \sp_read:delay_count_2\.T
         \sp_read:delay_count_3\.T \sp_read:delay_count_4\.T
         \sp_read:delay_count_5\.T \sp_read:delay_count_6\.T
         \sp_read:delay_count_7\.T \sp_read:delay_count_8\.T
         \sp_read:delay_count_9\.T \sp_read:old_phase\.T
         \sp_read:reset_count_0\.T \sp_read:reset_count_1\.T
         \sp_read:reset_count_2\.T address_from_pc_0.T address_from_pc_1.T
         address_from_pc_2.T address_from_pc_3.T address_from_pc_4.T
         address_from_pc_5.T address_from_pc_6.T address_from_pc_7.T
         ao_from_pc_ack.T ao_to_pc_strobe.T bp_end_address_0.T
         bp_end_address_1.T bp_end_address_2.T bp_end_address_3.T
         bp_end_address_4.T bp_end_address_5.T bp_end_address_6.T
         bp_end_address_7.T bp_start_address_0.T bp_start_address_1.T
         bp_start_address_2.T bp_start_address_3.T bp_start_address_4.T
         bp_start_address_5.T bp_start_address_6.T bp_start_address_7.T
         bpaddr(0).T bpaddr(1).T bpaddr(2).T bpaddr(3).T bpaddr(4).T
         bpaddr(5).T bpaddr(6).T bpaddr(7).T bpaddr_tristate.T bpctrl(0).T
         bpctrl(10).T bpctrl(11).T bpctrl(2).T bpctrl(3).T bpctrl(4).T
         bpctrl(5).T bpctrl(6).T bpctrl(7).T bpctrl(8).T bpd(10).T bpd(11).T
         bpd(12).T bpd(13).T bpd(14).T bpd(15).T bpd_h_tristate.T d(16).T
         d(17).T d(18).T d(19).T d(20).T d(21).T d(22).T d(23).T d(24).T
         d(25).T d(26).T d(27).T d(28).T d(29).T d(30).T d(31).T
         data_from_pc_13.T data_from_pc_14.T data_from_pc_15.T from_pc_req.T
         il_tristate.T led1.T sensor_address_0.T sensor_address_1.T
         sensor_address_2.T sensor_address_3.T sensor_address_4.T
         sensor_address_5.T sensor_address_6.T sensor_address_7.T
         sensor_data_0.T sensor_data_1.T sensor_data_10.T sensor_data_11.T
         sensor_data_12.T sensor_data_13.T sensor_data_14.T sensor_data_15.T
         sensor_data_2.T sensor_data_3.T sensor_data_4.T sensor_data_5.T
         sensor_data_6.T sensor_data_7.T sensor_data_8.T sensor_data_9.T
         sensor_to_bp_read_ack.T sensor_to_bp_read_req.T sensor_to_ibus_req.T
         this_chip_selected.T to_pc_ack.T tristate_stateSBV_0.T
         write_to_bp_ack.T

  Information: Optimizing logic using best output polarity for signals:
         \bp_io:bp_access_stateSBV_0\.D \bp_io:bp_access_stateSBV_1\.D
         \bp_io:bp_access_stateSBV_2\.D \bp_io:timeout_0\.D
         \bp_io:timeout_1\.D \bp_io:timeout_2\.D
         \ibus_reader:il_read_stateSBV_0\.D \ibus_reader:il_read_stateSBV_1\.D
         \ibus_reader:il_read_stateSBV_2\.D
         \ibus_reader:this_is_a_ctrl_transaction\.D \ibus_reader:timeout_0\.D
         \ibus_reader:timeout_1\.D \ibus_reader:timeout_2\.D
         \ibus_reader:timeout_3\.D \ibus_writer:iu_writeSBV_0\.D
         \ibus_writer:iu_writeSBV_1\.D \ibus_writer:timeout_0\.D
         \ibus_writer:timeout_1\.D \ibus_writer:timeout_2\.D
         \ibus_writer:timeout_3\.D \sp_read:cmp_vv_us_MODGEN_10\
         \sp_read:counter_address_0\.D \sp_read:counter_address_1\.D
         \sp_read:counter_address_2\.D \sp_read:counter_address_3\.D
         \sp_read:counter_address_4\.D \sp_read:counter_address_5\.D
         \sp_read:counter_address_6\.D \sp_read:counter_address_7\.D
         \sp_read:counter_read_stateSBV_0\.D
         \sp_read:counter_read_stateSBV_1\.D
         \sp_read:counter_read_stateSBV_2\.D
         \sp_read:counter_read_stateSBV_3\.D \sp_read:delay_count_0\.D
         \sp_read:delay_count_1\.D \sp_read:delay_count_2\.D
         \sp_read:delay_count_3\.D \sp_read:delay_count_4\.D
         \sp_read:delay_count_5\.D \sp_read:delay_count_6\.D
         \sp_read:delay_count_7\.D \sp_read:delay_count_8\.D
         \sp_read:delay_count_9\.D \sp_read:reset_count_1\.D
         \sp_read:reset_count_2\.D address_from_pc_0.D address_from_pc_1.D
         address_from_pc_2.D address_from_pc_3.D address_from_pc_4.D
         address_from_pc_5.D address_from_pc_6.D address_from_pc_7.D
         ao_to_pc_strobe.D bp_end_address_0.D bp_end_address_1.D
         bp_end_address_2.D bp_end_address_3.D bp_end_address_4.D
         bp_end_address_5.D bp_end_address_6.D bp_end_address_7.D
         bp_start_address_0.D bp_start_address_1.D bp_start_address_2.D
         bp_start_address_3.D bp_start_address_4.D bp_start_address_5.D
         bp_start_address_6.D bp_start_address_7.D bpaddr(0).D bpaddr(1).D
         bpaddr(2).D bpaddr(3).D bpaddr(4).D bpaddr(5).D bpaddr(6).D
         bpaddr(7).D bpaddr_tristate.D bpctrl(0).D bpctrl(10).D bpctrl(11).D
         bpctrl(2).D bpctrl(4).D bpctrl(5).D bpctrl(6).D bpctrl(7).D
         bpctrl(8).D bpd(10).D bpd(11).D bpd(12).D bpd(13).D bpd(14).D
         bpd(15).D bpd_h_tristate.D d(16).D d(17).D d(18).D d(19).D d(20).D
         d(21).D d(22).D d(23).D d(24).D d(25).D d(26).D d(27).D d(28).D
         d(29).D d(30).D d(31).D data_from_pc_13.D data_from_pc_14.D
         data_from_pc_15.D from_pc_req.D il_tristate.D led1.D loopback_state.D
         sensor_address_0.D sensor_address_1.D sensor_address_2.D
         sensor_address_3.D sensor_address_4.D sensor_address_5.D
         sensor_address_6.D sensor_address_7.D sensor_data_0.D sensor_data_1.D
         sensor_data_10.D sensor_data_11.D sensor_data_12.D sensor_data_13.D
         sensor_data_14.D sensor_data_15.D sensor_data_2.D sensor_data_3.D
         sensor_data_4.D sensor_data_5.D sensor_data_6.D sensor_data_7.D
         sensor_data_8.D sensor_data_9.D sensor_to_bp_read_ack.D
         sensor_to_ibus_req.D this_chip_selected.D to_pc_ack.D
         write_to_bp_ack.D

  Information: Selected logic optimization OFF for signals:
         \bp_io:bp_access_stateSBV_0\.C \bp_io:bp_access_stateSBV_1\.C
         \bp_io:bp_access_stateSBV_2\.C \bp_io:timeout_0\.C
         \bp_io:timeout_1\.C \bp_io:timeout_2\.C
         \ibus_reader:il_read_stateSBV_0\.C \ibus_reader:il_read_stateSBV_1\.C
         \ibus_reader:il_read_stateSBV_2\.C
         \ibus_reader:this_is_a_ctrl_transaction\.AR
         \ibus_reader:this_is_a_ctrl_transaction\.C \ibus_reader:timeout_0\.C
         \ibus_reader:timeout_1\.C \ibus_reader:timeout_2\.C
         \ibus_reader:timeout_3\.C \ibus_writer:iu_writeSBV_0\.C
         \ibus_writer:iu_writeSBV_1\.C \ibus_writer:timeout_0\.C
         \ibus_writer:timeout_1\.C \ibus_writer:timeout_2\.C
         \ibus_writer:timeout_3\.C \sp_read:counter_address_0\.C
         \sp_read:counter_address_1\.C \sp_read:counter_address_2\.C
         \sp_read:counter_address_3\.C \sp_read:counter_address_4\.C
         \sp_read:counter_address_5\.C \sp_read:counter_address_6\.C
         \sp_read:counter_address_7\.C \sp_read:counter_read_stateSBV_0\.C
         \sp_read:counter_read_stateSBV_1\.C
         \sp_read:counter_read_stateSBV_2\.C
         \sp_read:counter_read_stateSBV_3\.C \sp_read:delay_count_0\.C
         \sp_read:delay_count_1\.C \sp_read:delay_count_2\.C
         \sp_read:delay_count_3\.C \sp_read:delay_count_4\.C
         \sp_read:delay_count_5\.C \sp_read:delay_count_6\.C
         \sp_read:delay_count_7\.C \sp_read:delay_count_8\.C
         \sp_read:delay_count_9\.C \sp_read:old_phase\.D
         \sp_read:old_phase\.AP \sp_read:old_phase\.AR \sp_read:old_phase\.C
         \sp_read:reset_count_0\.D \sp_read:reset_count_0\.C
         \sp_read:reset_count_1\.C \sp_read:reset_count_2\.C
         address_from_pc_0.C address_from_pc_1.C address_from_pc_2.C
         address_from_pc_3.C address_from_pc_4.C address_from_pc_5.C
         address_from_pc_6.C address_from_pc_7.C ao_from_pc_ack.D
         ao_from_pc_ack.C ao_from_pc_ack.OE ao_to_pc_strobe.C
         bp_end_address_0.AP bp_end_address_0.C bp_end_address_1.AP
         bp_end_address_1.C bp_end_address_2.AP bp_end_address_2.C
         bp_end_address_3.AP bp_end_address_3.C bp_end_address_4.AP
         bp_end_address_4.C bp_end_address_5.AP bp_end_address_5.C
         bp_end_address_6.AP bp_end_address_6.C bp_end_address_7.AP
         bp_end_address_7.C bp_start_address_0.AP bp_start_address_0.C
         bp_start_address_1.AP bp_start_address_1.C bp_start_address_2.AP
         bp_start_address_2.C bp_start_address_3.AP bp_start_address_3.C
         bp_start_address_4.AP bp_start_address_4.C bp_start_address_5.AP
         bp_start_address_5.C bp_start_address_6.AP bp_start_address_6.C
         bp_start_address_7.AP bp_start_address_7.C bpaddr(0).C bpaddr(1).C
         bpaddr(2).C bpaddr(3).C bpaddr(4).C bpaddr(5).C bpaddr(6).C
         bpaddr(7).C bpaddr_dir bpaddr_tristate.C bpctrl(0).C bpctrl(1)
         bpctrl(10).C bpctrl(10).OE bpctrl(11).C bpctrl(11).OE bpctrl(2).C
         bpctrl(3).D bpctrl(3).C bpctrl(4).C bpctrl(4).OE bpctrl(5).C
         bpctrl(5).OE bpctrl(6).C bpctrl(6).OE bpctrl(7).C bpctrl(7).OE
         bpctrl(8).C bpctrl(8).OE bpctrl_h_dir bpctrl_h_tristate bpctrl_l_dir
         bpctrl_l_tristate bpd(10).C bpd(10).OE bpd(11).C bpd(11).OE bpd(12).C
         bpd(12).OE bpd(13).C bpd(13).OE bpd(14).C bpd(14).OE bpd(15).C
         bpd(15).OE bpd_h_dir bpd_h_tristate.C bpd_l_dir bpd_l_tristate
         d(16).C d(17).C d(18).C d(19).C d(20).C d(21).C d(22).C d(23).C
         d(24).C d(25).C d(26).C d(27).C d(28).C d(29).C d(30).C d(31).C
         data_from_pc_13.C data_from_pc_14.C data_from_pc_15.C from_pc_req.C
         il_tristate.C led1.C led2 led3 loopback_state.T loopback_state.AR
         loopback_state.C reset sensor_address_0.C sensor_address_1.C
         sensor_address_2.C sensor_address_3.C sensor_address_4.C
         sensor_address_5.C sensor_address_6.C sensor_address_7.C
         sensor_data_0.C sensor_data_1.C sensor_data_10.C sensor_data_11.C
         sensor_data_12.C sensor_data_13.C sensor_data_14.C sensor_data_15.C
         sensor_data_2.C sensor_data_3.C sensor_data_4.C sensor_data_5.C
         sensor_data_6.C sensor_data_7.C sensor_data_8.C sensor_data_9.C
         sensor_to_bp_read_ack.C sensor_to_bp_read_req.D
         sensor_to_bp_read_req.C sensor_to_ibus_req.C this_chip_selected.AR
         this_chip_selected.C to_pc_ack.C tristate_stateSBV_0.D
         tristate_stateSBV_0.C write_to_bp_ack.C



Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully  
----------------------------------------------------------------------------
PLD Optimizer Software:       MINOPT.EXE     01/NOV/1999  [v4.02 ] 6.2 IR 27

LOGIC MINIMIZATION         ()

Messages:


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully
----------------------------------------------------------------------------
PLD Optimizer Software:       DSGNOPT.EXE    31/03/2000  [v4.02 ] 6.2 IR 27

OPTIMIZATION OPTIONS       (20:13:13)

Messages:
  Information: Optimizing Banked Preset/Reset requirements.
  Information: Selecting D register equation as minimal for signal \ibus_reader:this_is_a_ctrl_transaction\
  Information: Selecting D register equation as minimal for signal this_chip_selected
  Information: Inverting Preset/Reset & output logic polarity for bp_end_address_0.
  Information: Selecting T register equation as minimal for signal bp_end_address_0
  Information: Inverting Preset/Reset & output logic polarity for bp_end_address_1.
  Information: Selecting T register equation as minimal for signal bp_end_address_1
  Information: Inverting Preset/Reset & output logic polarity for bp_end_address_2.
  Information: Selecting T register equation as minimal for signal bp_end_address_2
  Information: Inverting Preset/Reset & output logic polarity for bp_end_address_3.
  Information: Selecting T register equation as minimal for signal bp_end_address_3
  Information: Inverting Preset/Reset & output logic polarity for bp_end_address_4.
  Information: Selecting T register equation as minimal for signal bp_end_address_4
  Information: Inverting Preset/Reset & output logic polarity for bp_end_address_5.
  Information: Selecting T register equation as minimal for signal bp_end_address_5
  Information: Inverting Preset/Reset & output logic polarity for bp_end_address_6.
  Information: Selecting T register equation as minimal for signal bp_end_address_6
  Information: Inverting Preset/Reset & output logic polarity for bp_end_address_7.
  Information: Selecting T register equation as minimal for signal bp_end_address_7
  Information: Inverting Preset/Reset & output logic polarity for bp_start_address_0.
  Information: Selecting T register equation as minimal for signal bp_start_address_0
  Information: Inverting Preset/Reset & output logic polarity for bp_start_address_1.
  Information: Selecting T register equation as minimal for signal bp_start_address_1
  Information: Inverting Preset/Reset & output logic polarity for bp_start_address_2.
  Information: Selecting T register equation as minimal for signal bp_start_address_2
  Information: Inverting Preset/Reset & output logic polarity for bp_start_address_3.
  Information: Selecting T register equation as minimal for signal bp_start_address_3
  Information: Inverting Preset/Reset & output logic polarity for bp_start_address_4.
  Information: Selecting T register equation as minimal for signal bp_start_address_4
  Information: Inverting Preset/Reset & output logic polarity for bp_start_address_5.
  Information: Selecting T register equation as minimal for signal bp_start_address_5
  Information: Inverting Preset/Reset & output logic polarity for bp_start_address_6.
  Information: Selecting T register equation as minimal for signal bp_start_address_6
  Information: Inverting Preset/Reset & output logic polarity for bp_start_address_7.
  Information: Selecting T register equation as minimal for signal bp_start_address_7
  Information: Inverting Preset/Reset & output logic polarity for loopback_state.
  Information: Selecting T register equation as minimal for signal loopback_state
  Information: Selecting D register equation as minimal for signal \sp_read:old_phase\
  Information: Selecting D register equation as minimal for signal bpctrl(0)
  Information: Selecting D register equation as minimal for signal bpctrl(2)
  Information: Selecting D register equation as minimal for signal bpctrl(3)
  Information: Selecting T register equation as minimal for signal bpctrl(4)
  Information: Selecting T register equation as minimal for signal bpctrl(5)
  Information: Selecting T register equation as minimal for signal bpctrl(6)
  Information: Selecting T register equation as minimal for signal bpctrl(7)
  Information: Selecting T register equation as minimal for signal bpctrl(8)
  Information: Selecting T register equation as minimal for signal bpctrl(10)
  Information: Selecting T register equation as minimal for signal bpctrl(11)
  Information: Selecting T register equation as minimal for signal bpaddr(0)
  Information: Selecting T register equation as minimal for signal bpaddr(1)
  Information: Selecting T register equation as minimal for signal bpaddr(2)
  Information: Selecting T register equation as minimal for signal bpaddr(3)
  Information: Selecting T register equation as minimal for signal bpaddr(4)
  Information: Selecting T register equation as minimal for signal bpaddr(5)
  Information: Selecting T register equation as minimal for signal bpaddr(6)
  Information: Selecting T register equation as minimal for signal bpaddr(7)
  Information: Selecting D register equation as minimal for signal bpd_h_tristate
  Information: Selecting D register equation as minimal for signal bpaddr_tristate
  Information: Selecting D register equation as minimal for signal led1
  Information: Selecting D register equation as minimal for signal ao_to_pc_strobe
  Information: Selecting D register equation as minimal for signal ao_from_pc_ack
  Information: Selecting T register equation as minimal for signal d(16)
  Information: Selecting T register equation as minimal for signal d(17)
  Information: Selecting T register equation as minimal for signal d(18)
  Information: Selecting T register equation as minimal for signal d(19)
  Information: Selecting T register equation as minimal for signal d(20)
  Information: Selecting T register equation as minimal for signal d(21)
  Information: Selecting T register equation as minimal for signal d(22)
  Information: Selecting T register equation as minimal for signal d(23)
  Information: Selecting T register equation as minimal for signal d(24)
  Information: Selecting T register equation as minimal for signal d(25)
  Information: Selecting T register equation as minimal for signal d(26)
  Information: Selecting T register equation as minimal for signal d(27)
  Information: Selecting T register equation as minimal for signal d(28)
  Information: Selecting T register equation as minimal for signal d(29)
  Information: Selecting T register equation as minimal for signal d(30)
  Information: Selecting T register equation as minimal for signal d(31)
  Information: Selecting T register equation as minimal for signal bpd(10)
  Information: Selecting T register equation as minimal for signal bpd(11)
  Information: Selecting T register equation as minimal for signal bpd(12)
  Information: Selecting T register equation as minimal for signal bpd(13)
  Information: Selecting T register equation as minimal for signal bpd(14)
  Information: Selecting T register equation as minimal for signal bpd(15)
  Information: Selecting D register equation as minimal for signal write_to_bp_ack
  Information: Selecting D register equation as minimal for signal tristate_stateSBV_0
  Information: Selecting D register equation as minimal for signal to_pc_ack
  Information: Selecting D register equation as minimal for signal sensor_to_ibus_req
  Information: Selecting D register equation as minimal for signal sensor_to_bp_read_req
  Information: Selecting D register equation as minimal for signal sensor_to_bp_read_ack
  Information: Selecting T register equation as minimal for signal sensor_data_9
  Information: Selecting T register equation as minimal for signal sensor_data_8
  Information: Selecting T register equation as minimal for signal sensor_data_7
  Information: Selecting T register equation as minimal for signal sensor_data_6
  Information: Selecting T register equation as minimal for signal sensor_data_5
  Information: Selecting T register equation as minimal for signal sensor_data_4
  Information: Selecting T register equation as minimal for signal sensor_data_3
  Information: Selecting T register equation as minimal for signal sensor_data_2
  Information: Selecting T register equation as minimal for signal sensor_data_15
  Information: Selecting T register equation as minimal for signal sensor_data_14
  Information: Selecting T register equation as minimal for signal sensor_data_13
  Information: Selecting T register equation as minimal for signal sensor_data_12
  Information: Selecting T register equation as minimal for signal sensor_data_11
  Information: Selecting T register equation as minimal for signal sensor_data_10
  Information: Selecting T register equation as minimal for signal sensor_data_1
  Information: Selecting T register equation as minimal for signal sensor_data_0
  Information: Selecting T register equation as minimal for signal sensor_address_7
  Information: Selecting T register equation as minimal for signal sensor_address_6
  Information: Selecting T register equation as minimal for signal sensor_address_5
  Information: Selecting T register equation as minimal for signal sensor_address_4
  Information: Selecting T register equation as minimal for signal sensor_address_3
  Information: Selecting T register equation as minimal for signal sensor_address_2
  Information: Selecting T register equation as minimal for signal sensor_address_1
  Information: Selecting T register equation as minimal for signal sensor_address_0
  Information: Selecting D register equation as minimal for signal il_tristate
  Information: Selecting D register equation as minimal for signal from_pc_req
  Information: Selecting T register equation as minimal for signal data_from_pc_15
  Information: Selecting T register equation as minimal for signal data_from_pc_14
  Information: Selecting T register equation as minimal for signal data_from_pc_13
  Information: Selecting T register equation as minimal for signal address_from_pc_7
  Information: Selecting T register equation as minimal for signal address_from_pc_6
  Information: Selecting T register equation as minimal for signal address_from_pc_5
  Information: Selecting T register equation as minimal for signal address_from_pc_4
  Information: Selecting T register equation as minimal for signal address_from_pc_3
  Information: Selecting T register equation as minimal for signal address_from_pc_2
  Information: Selecting T register equation as minimal for signal address_from_pc_1
  Information: Selecting T register equation as minimal for signal address_from_pc_0
  Information: Selecting D register equation as minimal for signal \sp_read:reset_count_2\
  Information: Selecting D register equation as minimal for signal \sp_read:reset_count_1\
  Information: Selecting D register equation as minimal for signal \sp_read:reset_count_0\
  Information: Selecting D register equation as minimal for signal \sp_read:delay_count_9\
  Information: Selecting D register equation as minimal for signal \sp_read:delay_count_8\
  Information: Selecting D register equation as minimal for signal \sp_read:delay_count_7\
  Information: Selecting D register equation as minimal for signal \sp_read:delay_count_6\
  Information: Selecting D register equation as minimal for signal \sp_read:delay_count_5\
  Information: Selecting D register equation as minimal for signal \sp_read:delay_count_4\
  Information: Selecting D register equation as minimal for signal \sp_read:delay_count_3\
  Information: Selecting D register equation as minimal for signal \sp_read:delay_count_2\
  Information: Selecting D register equation as minimal for signal \sp_read:delay_count_1\
  Information: Selecting D register equation as minimal for signal \sp_read:delay_count_0\
  Information: Selecting D register equation as minimal for signal \sp_read:counter_read_stateSBV_3\
  Information: Selecting T register equation as minimal for signal \sp_read:counter_read_stateSBV_2\
  Information: Sum-Splitting output logic for signal \sp_read:counter_read_stateSBV_2\.
  Information: Selecting T register equation as minimal for signal \sp_read:counter_read_stateSBV_1\
  Information: Selecting D register equation as minimal for signal \sp_read:counter_read_stateSBV_0\
  Information: Selecting D register equation as minimal for signal \sp_read:counter_address_7\
  Information: Sum-Splitting output logic for signal \sp_read:counter_address_7\.
  Information: Selecting D register equation as minimal for signal \sp_read:counter_address_6\
  Information: Sum-Splitting output logic for signal \sp_read:counter_address_6\.
  Information: Selecting D register equation as minimal for signal \sp_read:counter_address_5\
  Information: Sum-Splitting output logic for signal \sp_read:counter_address_5\.
  Information: Selecting D register equation as minimal for signal \sp_read:counter_address_4\
  Information: Sum-Splitting output logic for signal \sp_read:counter_address_4\.
  Information: Selecting D register equation as minimal for signal \sp_read:counter_address_3\
  Information: Sum-Splitting output logic for signal \sp_read:counter_address_3\.
  Information: Selecting D register equation as minimal for signal \sp_read:counter_address_2\
  Information: Sum-Splitting output logic for signal \sp_read:counter_address_2\.
  Information: Selecting D register equation as minimal for signal \sp_read:counter_address_1\
  Information: Sum-Splitting output logic for signal \sp_read:counter_address_1\.
  Information: Selecting D register equation as minimal for signal \sp_read:counter_address_0\
  Information: Sum-Splitting output logic for signal \sp_read:counter_address_0\.
  Information: Selecting T register equation as minimal for signal \ibus_writer:timeout_3\
  Information: Selecting T register equation as minimal for signal \ibus_writer:timeout_2\
  Information: Selecting T register equation as minimal for signal \ibus_writer:timeout_1\
  Information: Selecting D register equation as minimal for signal \ibus_writer:timeout_0\
  Information: Selecting D register equation as minimal for signal \ibus_writer:iu_writeSBV_1\
  Information: Selecting T register equation as minimal for signal \ibus_writer:iu_writeSBV_0\
  Information: Selecting D register equation as minimal for signal \ibus_reader:timeout_3\
  Information: Selecting T register equation as minimal for signal \ibus_reader:timeout_2\
  Information: Selecting D register equation as minimal for signal \ibus_reader:timeout_1\
  Information: Sum-Splitting output logic for signal \ibus_reader:timeout_1\.
  Information: Selecting D register equation as minimal for signal \ibus_reader:timeout_0\
  Information: Selecting T register equation as minimal for signal \ibus_reader:il_read_stateSBV_2\
  Information: Selecting T register equation as minimal for signal \ibus_reader:il_read_stateSBV_1\
  Information: Selecting T register equation as minimal for signal \ibus_reader:il_read_stateSBV_0\
  Information: Selecting T register equation as minimal for signal \bp_io:timeout_2\
  Information: Selecting T register equation as minimal for signal \bp_io:timeout_1\
  Information: Selecting D register equation as minimal for signal \bp_io:timeout_0\
  Information: Selecting T register equation as minimal for signal \bp_io:bp_access_stateSBV_2\
  Information: Selecting T register equation as minimal for signal \bp_io:bp_access_stateSBV_1\
  Information: Selecting T register equation as minimal for signal \bp_io:bp_access_stateSBV_0\
  Information: Optimizing Banked Preset/Reset requirements.
  Information: Selecting T register equation as minimal for signal \bp_io:bp_access_stateSBV_0\
  Information: Selecting T register equation as minimal for signal \bp_io:bp_access_stateSBV_1\
  Information: Selecting T register equation as minimal for signal \bp_io:bp_access_stateSBV_2\
  Information: Selecting D register equation as minimal for signal \bp_io:timeout_0\
  Information: Selecting T register equation as minimal for signal \bp_io:timeout_1\
  Information: Selecting T register equation as minimal for signal \bp_io:timeout_2\
  Information: Selecting T register equation as minimal for signal \ibus_reader:il_read_stateSBV_0\
  Information: Selecting T register equation as minimal for signal \ibus_reader:il_read_stateSBV_1\
  Information: Selecting T register equation as minimal for signal \ibus_reader:il_read_stateSBV_2\
  Information: Selecting D register equation as minimal for signal \ibus_reader:timeout_0\
  Information: Selecting D register equation as minimal for signal \ibus_reader:timeout_1\
  Information: Selecting T register equation as minimal for signal \ibus_reader:timeout_2\
  Information: Selecting D register equation as minimal for signal \ibus_reader:timeout_3\
  Information: Selecting T register equation as minimal for signal \ibus_writer:iu_writeSBV_0\
  Information: Selecting D register equation as minimal for signal \ibus_writer:iu_writeSBV_1\
  Information: Selecting D register equation as minimal for signal \ibus_writer:timeout_0\
  Information: Selecting T register equation as minimal for signal \ibus_writer:timeout_1\
  Information: Selecting T register equation as minimal for signal \ibus_writer:timeout_2\
  Information: Selecting T register equation as minimal for signal \ibus_writer:timeout_3\
  Information: Selecting D register equation as minimal for signal \sp_read:counter_address_0\
  Information: Selecting D register equation as minimal for signal \sp_read:counter_address_1\
  Information: Selecting D register equation as minimal for signal \sp_read:counter_address_2\
  Information: Selecting D register equation as minimal for signal \sp_read:counter_address_3\
  Information: Selecting D register equation as minimal for signal \sp_read:counter_address_4\
  Information: Selecting D register equation as minimal for signal \sp_read:counter_address_5\
  Information: Selecting D register equation as minimal for signal \sp_read:counter_address_6\
  Information: Selecting D register equation as minimal for signal \sp_read:counter_address_7\
  Information: Selecting D register equation as minimal for signal \sp_read:counter_read_stateSBV_0\
  Information: Selecting T register equation as minimal for signal \sp_read:counter_read_stateSBV_1\
  Information: Selecting T register equation as minimal for signal \sp_read:counter_read_stateSBV_2\
  Information: Selecting D register equation as minimal for signal \sp_read:counter_read_stateSBV_3\
  Information: Selecting D register equation as minimal for signal \sp_read:delay_count_0\
  Information: Selecting D register equation as minimal for signal \sp_read:delay_count_1\
  Information: Selecting D register equation as minimal for signal \sp_read:delay_count_2\
  Information: Selecting D register equation as minimal for signal \sp_read:delay_count_3\
  Information: Selecting D register equation as minimal for signal \sp_read:delay_count_4\
  Information: Selecting D register equation as minimal for signal \sp_read:delay_count_5\
  Information: Selecting D register equation as minimal for signal \sp_read:delay_count_6\
  Information: Selecting D register equation as minimal for signal \sp_read:delay_count_7\
  Information: Selecting D register equation as minimal for signal \sp_read:delay_count_8\
  Information: Selecting D register equation as minimal for signal \sp_read:delay_count_9\
  Information: Selecting D register equation as minimal for signal \sp_read:reset_count_0\
  Information: Selecting D register equation as minimal for signal \sp_read:reset_count_1\
  Information: Selecting D register equation as minimal for signal \sp_read:reset_count_2\
  Information: Selecting T register equation as minimal for signal address_from_pc_0
  Information: Selecting T register equation as minimal for signal address_from_pc_1
  Information: Selecting T register equation as minimal for signal address_from_pc_2
  Information: Selecting T register equation as minimal for signal address_from_pc_3
  Information: Selecting T register equation as minimal for signal address_from_pc_4
  Information: Selecting T register equation as minimal for signal address_from_pc_5
  Information: Selecting T register equation as minimal for signal address_from_pc_6
  Information: Selecting T register equation as minimal for signal address_from_pc_7
  Information: Selecting T register equation as minimal for signal data_from_pc_13
  Information: Selecting T register equation as minimal for signal data_from_pc_14
  Information: Selecting T register equation as minimal for signal data_from_pc_15
  Information: Selecting D register equation as minimal for signal from_pc_req
  Information: Selecting D register equation as minimal for signal il_tristate
  Information: Selecting T register equation as minimal for signal sensor_address_0
  Information: Selecting T register equation as minimal for signal sensor_address_1
  Information: Selecting T register equation as minimal for signal sensor_address_2
  Information: Selecting T register equation as minimal for signal sensor_address_3
  Information: Selecting T register equation as minimal for signal sensor_address_4
  Information: Selecting T register equation as minimal for signal sensor_address_5
  Information: Selecting T register equation as minimal for signal sensor_address_6
  Information: Selecting T register equation as minimal for signal sensor_address_7
  Information: Selecting T register equation as minimal for signal sensor_data_0
  Information: Selecting T register equation as minimal for signal sensor_data_1
  Information: Selecting T register equation as minimal for signal sensor_data_10
  Information: Selecting T register equation as minimal for signal sensor_data_11
  Information: Selecting T register equation as minimal for signal sensor_data_12
  Information: Selecting T register equation as minimal for signal sensor_data_13
  Information: Selecting T register equation as minimal for signal sensor_data_14
  Information: Selecting T register equation as minimal for signal sensor_data_15
  Information: Selecting T register equation as minimal for signal sensor_data_2
  Information: Selecting T register equation as minimal for signal sensor_data_3
  Information: Selecting T register equation as minimal for signal sensor_data_4
  Information: Selecting T register equation as minimal for signal sensor_data_5
  Information: Selecting T register equation as minimal for signal sensor_data_6
  Information: Selecting T register equation as minimal for signal sensor_data_7
  Information: Selecting T register equation as minimal for signal sensor_data_8
  Information: Selecting T register equation as minimal for signal sensor_data_9
  Information: Selecting D register equation as minimal for signal sensor_to_bp_read_ack
  Information: Selecting D register equation as minimal for signal sensor_to_bp_read_req
  Information: Selecting D register equation as minimal for signal sensor_to_ibus_req
  Information: Selecting D register equation as minimal for signal to_pc_ack
  Information: Selecting D register equation as minimal for signal tristate_stateSBV_0
  Information: Selecting D register equation as minimal for signal write_to_bp_ack
  Information: Selecting T register equation as minimal for signal bpd(15)
  Information: Selecting T register equation as minimal for signal bpd(14)
  Information: Selecting T register equation as minimal for signal bpd(13)
  Information: Selecting T register equation as minimal for signal bpd(12)
  Information: Selecting T register equation as minimal for signal bpd(11)
  Information: Selecting T register equation as minimal for signal bpd(10)
  Information: Selecting T register equation as minimal for signal d(31)
  Information: Selecting T register equation as minimal for signal d(30)
  Information: Selecting T register equation as minimal for signal d(29)
  Information: Selecting T register equation as minimal for signal d(28)
  Information: Selecting T register equation as minimal for signal d(27)
  Information: Selecting T register equation as minimal for signal d(26)
  Information: Selecting T register equation as minimal for signal d(25)
  Information: Selecting T register equation as minimal for signal d(24)
  Information: Selecting T register equation as minimal for signal d(23)
  Information: Selecting T register equation as minimal for signal d(22)
  Information: Selecting T register equation as minimal for signal d(21)
  Information: Selecting T register equation as minimal for signal d(20)
  Information: Selecting T register equation as minimal for signal d(19)
  Information: Selecting T register equation as minimal for signal d(18)
  Information: Selecting T register equation as minimal for signal d(17)
  Information: Selecting T register equation as minimal for signal d(16)
  Information: Selecting D register equation as minimal for signal ao_from_pc_ack
  Information: Selecting D register equation as minimal for signal ao_to_pc_strobe
  Information: Selecting D register equation as minimal for signal led1
  Information: Selecting D register equation as minimal for signal bpaddr_tristate
  Information: Selecting D register equation as minimal for signal bpd_h_tristate
  Information: Selecting T register equation as minimal for signal bpaddr(7)
  Information: Selecting T register equation as minimal for signal bpaddr(6)
  Information: Selecting T register equation as minimal for signal bpaddr(5)
  Information: Selecting T register equation as minimal for signal bpaddr(4)
  Information: Selecting T register equation as minimal for signal bpaddr(3)
  Information: Selecting T register equation as minimal for signal bpaddr(2)
  Information: Selecting T register equation as minimal for signal bpaddr(1)
  Information: Selecting T register equation as minimal for signal bpaddr(0)
  Information: Selecting T register equation as minimal for signal bpctrl(11)
  Information: Selecting T register equation as minimal for signal bpctrl(10)
  Information: Selecting T register equation as minimal for signal bpctrl(8)
  Information: Selecting T register equation as minimal for signal bpctrl(7)
  Information: Selecting T register equation as minimal for signal bpctrl(6)
  Information: Selecting T register equation as minimal for signal bpctrl(5)
  Information: Selecting T register equation as minimal for signal bpctrl(4)
  Information: Selecting D register equation as minimal for signal bpctrl(3)
  Information: Selecting D register equation as minimal for signal bpctrl(2)
  Information: Selecting D register equation as minimal for signal bpctrl(0)
  Information: Selecting D register equation as minimal for signal \ibus_reader:this_is_a_ctrl_transaction\
  Information: Selecting T register equation as minimal for signal bp_end_address_0
  Information: Selecting T register equation as minimal for signal bp_end_address_1
  Information: Selecting T register equation as minimal for signal bp_end_address_2
  Information: Selecting T register equation as minimal for signal bp_end_address_3
  Information: Selecting T register equation as minimal for signal bp_end_address_4
  Information: Selecting T register equation as minimal for signal bp_end_address_5
  Information: Selecting T register equation as minimal for signal bp_end_address_6
  Information: Selecting T register equation as minimal for signal bp_end_address_7
  Information: Selecting T register equation as minimal for signal bp_start_address_0
  Information: Selecting T register equation as minimal for signal bp_start_address_1
  Information: Selecting T register equation as minimal for signal bp_start_address_2
  Information: Selecting T register equation as minimal for signal bp_start_address_3
  Information: Selecting T register equation as minimal for signal bp_start_address_4
  Information: Selecting T register equation as minimal for signal bp_start_address_5
  Information: Selecting T register equation as minimal for signal bp_start_address_6
  Information: Selecting T register equation as minimal for signal bp_start_address_7
  Information: Selecting D register equation as minimal for signal this_chip_selected
  Information: Selecting T register equation as minimal for signal loopback_state
  Information: Selecting D register equation as minimal for signal \sp_read:old_phase\
  Information: Optimizing logic without changing polarity for signals:
         \bp_io:bp_access_stateSBV_0\.T \bp_io:bp_access_stateSBV_1\.T
         \bp_io:bp_access_stateSBV_2\.T \bp_io:timeout_0\.D
         \bp_io:timeout_1\.T \bp_io:timeout_2\.T
         \ibus_reader:il_read_stateSBV_0\.T \ibus_reader:il_read_stateSBV_1\.T
         \ibus_reader:il_read_stateSBV_2\.T
         \ibus_reader:this_is_a_ctrl_transaction\.D \ibus_reader:timeout_0\.D
         \ibus_reader:timeout_1\.D \ibus_reader:timeout_2\.T
         \ibus_reader:timeout_3\.D \ibus_writer:iu_writeSBV_0\.T
         \ibus_writer:iu_writeSBV_1\.D \ibus_writer:timeout_0\.D
         \ibus_writer:timeout_1\.T \ibus_writer:timeout_2\.T
         \ibus_writer:timeout_3\.T \sp_read:cmp_vv_us_MODGEN_10\
         \sp_read:counter_address_0\.D \sp_read:counter_address_1\.D
         \sp_read:counter_address_2\.D \sp_read:counter_address_3\.D
         \sp_read:counter_address_4\.D \sp_read:counter_address_5\.D
         \sp_read:counter_address_6\.D \sp_read:counter_address_7\.D
         \sp_read:counter_read_stateSBV_0\.D
         \sp_read:counter_read_stateSBV_1\.T
         \sp_read:counter_read_stateSBV_2\.T
         \sp_read:counter_read_stateSBV_3\.D \sp_read:delay_count_0\.D
         \sp_read:delay_count_1\.D \sp_read:delay_count_2\.D
         \sp_read:delay_count_3\.D \sp_read:delay_count_4\.D
         \sp_read:delay_count_5\.D \sp_read:delay_count_6\.D
         \sp_read:delay_count_7\.D \sp_read:delay_count_8\.D
         \sp_read:delay_count_9\.D \sp_read:old_phase\.D
         \sp_read:reset_count_0\.D \sp_read:reset_count_1\.D
         \sp_read:reset_count_2\.D address_from_pc_0.T address_from_pc_1.T
         address_from_pc_2.T address_from_pc_3.T address_from_pc_4.T
         address_from_pc_5.T address_from_pc_6.T address_from_pc_7.T
         ao_from_pc_ack.D ao_to_pc_strobe.D bp_end_address_0.T
         bp_end_address_1.T bp_end_address_2.T bp_end_address_3.T
         bp_end_address_4.T bp_end_address_5.T bp_end_address_6.T
         bp_end_address_7.T bp_start_address_0.T bp_start_address_1.T
         bp_start_address_2.T bp_start_address_3.T bp_start_address_4.T
         bp_start_address_5.T bp_start_address_6.T bp_start_address_7.T
         bpaddr(0).T bpaddr(1).T bpaddr(2).T bpaddr(3).T bpaddr(4).T
         bpaddr(5).T bpaddr(6).T bpaddr(7).T bpaddr_tristate.D bpctrl(0).D
         bpctrl(10).T bpctrl(11).T bpctrl(2).D bpctrl(3).D bpctrl(4).T
         bpctrl(5).T bpctrl(6).T bpctrl(7).T bpctrl(8).T bpd(10).T bpd(11).T
         bpd(12).T bpd(13).T bpd(14).T bpd(15).T bpd_h_tristate.D d(16).T
         d(17).T d(18).T d(19).T d(20).T d(21).T d(22).T d(23).T d(24).T
         d(25).T d(26).T d(27).T d(28).T d(29).T d(30).T d(31).T
         data_from_pc_13.T data_from_pc_14.T data_from_pc_15.T from_pc_req.D
         il_tristate.D led1.D loopback_state.T sensor_address_0.T
         sensor_address_1.T sensor_address_2.T sensor_address_3.T
         sensor_address_4.T sensor_address_5.T sensor_address_6.T
         sensor_address_7.T sensor_data_0.T sensor_data_1.T sensor_data_10.T
         sensor_data_11.T sensor_data_12.T sensor_data_13.T sensor_data_14.T
         sensor_data_15.T sensor_data_2.T sensor_data_3.T sensor_data_4.T
         sensor_data_5.T sensor_data_6.T sensor_data_7.T sensor_data_8.T
         sensor_data_9.T sensor_to_bp_read_ack.D sensor_to_bp_read_req.D
         sensor_to_ibus_req.D this_chip_selected.D to_pc_ack.D
         tristate_stateSBV_0.D write_to_bp_ack.D

  Information: Optimizing logic using best output polarity for signals:
         S_1 S_10 S_11 S_12 S_13 S_14 S_15 S_16 S_17 S_18 S_19 S_2 S_20 S_3
         S_4 S_5 S_6 S_7 S_8 S_9

  Information: Selected logic optimization OFF for signals:
         \bp_io:bp_access_stateSBV_0\.C \bp_io:bp_access_stateSBV_1\.C
         \bp_io:bp_access_stateSBV_2\.C \bp_io:timeout_0\.C
         \bp_io:timeout_1\.C \bp_io:timeout_2\.C
         \ibus_reader:il_read_stateSBV_0\.C \ibus_reader:il_read_stateSBV_1\.C
         \ibus_reader:il_read_stateSBV_2\.C
         \ibus_reader:this_is_a_ctrl_transaction\.AP
         \ibus_reader:this_is_a_ctrl_transaction\.AR
         \ibus_reader:this_is_a_ctrl_transaction\.C \ibus_reader:timeout_0\.C
         \ibus_reader:timeout_1\.C \ibus_reader:timeout_2\.C
         \ibus_reader:timeout_3\.C \ibus_writer:iu_writeSBV_0\.C
         \ibus_writer:iu_writeSBV_1\.C \ibus_writer:timeout_0\.C
         \ibus_writer:timeout_1\.C \ibus_writer:timeout_2\.C
         \ibus_writer:timeout_3\.C \sp_read:counter_address_0\.C
         \sp_read:counter_address_1\.C \sp_read:counter_address_2\.C
         \sp_read:counter_address_3\.C \sp_read:counter_address_4\.C
         \sp_read:counter_address_5\.C \sp_read:counter_address_6\.C
         \sp_read:counter_address_7\.C \sp_read:counter_read_stateSBV_0\.C
         \sp_read:counter_read_stateSBV_1\.C
         \sp_read:counter_read_stateSBV_2\.C
         \sp_read:counter_read_stateSBV_3\.C \sp_read:delay_count_0\.C
         \sp_read:delay_count_1\.C \sp_read:delay_count_2\.C
         \sp_read:delay_count_3\.C \sp_read:delay_count_4\.C
         \sp_read:delay_count_5\.C \sp_read:delay_count_6\.C
         \sp_read:delay_count_7\.C \sp_read:delay_count_8\.C
         \sp_read:delay_count_9\.C \sp_read:old_phase\.AP
         \sp_read:old_phase\.AR \sp_read:old_phase\.C
         \sp_read:reset_count_0\.C \sp_read:reset_count_1\.C
         \sp_read:reset_count_2\.C address_from_pc_0.C address_from_pc_1.C
         address_from_pc_2.C address_from_pc_3.C address_from_pc_4.C
         address_from_pc_5.C address_from_pc_6.C address_from_pc_7.C
         ao_from_pc_ack.C ao_from_pc_ack.OE ao_to_pc_strobe.C
         bp_end_address_0.AP bp_end_address_0.AR bp_end_address_0.C
         bp_end_address_1.AP bp_end_address_1.AR bp_end_address_1.C
         bp_end_address_2.AP bp_end_address_2.AR bp_end_address_2.C
         bp_end_address_3.AP bp_end_address_3.AR bp_end_address_3.C
         bp_end_address_4.AP bp_end_address_4.AR bp_end_address_4.C
         bp_end_address_5.AP bp_end_address_5.AR bp_end_address_5.C
         bp_end_address_6.AP bp_end_address_6.AR bp_end_address_6.C
         bp_end_address_7.AP bp_end_address_7.AR bp_end_address_7.C
         bp_start_address_0.AP bp_start_address_0.AR bp_start_address_0.C
         bp_start_address_1.AP bp_start_address_1.AR bp_start_address_1.C
         bp_start_address_2.AP bp_start_address_2.AR bp_start_address_2.C
         bp_start_address_3.AP bp_start_address_3.AR bp_start_address_3.C
         bp_start_address_4.AP bp_start_address_4.AR bp_start_address_4.C
         bp_start_address_5.AP bp_start_address_5.AR bp_start_address_5.C
         bp_start_address_6.AP bp_start_address_6.AR bp_start_address_6.C
         bp_start_address_7.AP bp_start_address_7.AR bp_start_address_7.C
         bpaddr(0).C bpaddr(1).C bpaddr(2).C bpaddr(3).C bpaddr(4).C
         bpaddr(5).C bpaddr(6).C bpaddr(7).C bpaddr_dir bpaddr_tristate.C
         bpctrl(0).C bpctrl(1) bpctrl(10).C bpctrl(10).OE bpctrl(11).C
         bpctrl(11).OE bpctrl(2).C bpctrl(3).C bpctrl(4).C bpctrl(4).OE
         bpctrl(5).C bpctrl(5).OE bpctrl(6).C bpctrl(6).OE bpctrl(7).C
         bpctrl(7).OE bpctrl(8).C bpctrl(8).OE bpctrl_h_dir bpctrl_h_tristate
         bpctrl_l_dir bpctrl_l_tristate bpd(10).C bpd(10).OE bpd(11).C
         bpd(11).OE bpd(12).C bpd(12).OE bpd(13).C bpd(13).OE bpd(14).C
         bpd(14).OE bpd(15).C bpd(15).OE bpd_h_dir bpd_h_tristate.C bpd_l_dir
         bpd_l_tristate d(16).C d(17).C d(18).C d(19).C d(20).C d(21).C
         d(22).C d(23).C d(24).C d(25).C d(26).C d(27).C d(28).C d(29).C
         d(30).C d(31).C data_from_pc_13.C data_from_pc_14.C data_from_pc_15.C
         from_pc_req.C il_tristate.C led1.C led2 led3 loopback_state.AP
         loopback_state.AR loopback_state.C reset sensor_address_0.C
         sensor_address_1.C sensor_address_2.C sensor_address_3.C
         sensor_address_4.C sensor_address_5.C sensor_address_6.C
         sensor_address_7.C sensor_data_0.C sensor_data_1.C sensor_data_10.C
         sensor_data_11.C sensor_data_12.C sensor_data_13.C sensor_data_14.C
         sensor_data_15.C sensor_data_2.C sensor_data_3.C sensor_data_4.C
         sensor_data_5.C sensor_data_6.C sensor_data_7.C sensor_data_8.C
         sensor_data_9.C sensor_to_bp_read_ack.C sensor_to_bp_read_req.C
         sensor_to_ibus_req.C this_chip_selected.AP this_chip_selected.AR
         this_chip_selected.C to_pc_ack.C tristate_stateSBV_0.C
         write_to_bp_ack.C



Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully  
----------------------------------------------------------------------------
PLD Optimizer Software:       MINOPT.EXE     01/NOV/1999  [v4.02 ] 6.2 IR 27

LOGIC MINIMIZATION         ()

Messages:


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully
----------------------------------------------------------------------------
PLD Optimizer Software:       DSGNOPT.EXE    31/03/2000  [v4.02 ] 6.2 IR 27

OPTIMIZATION OPTIONS       (20:13:13)

Messages:


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully  
----------------------------------------------------------------------------
PLD Compiler Software:        C37KFIT.EXE    22/DEC/2000  [v4.02 ] 6.2 IR 27

DESIGN EQUATIONS           (20:13:13)


    S_1 =
          /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          /bp_end_address_0.Q * /bp_end_address_1.Q * /bp_end_address_2.Q * 
          /bp_end_address_3.Q * /bp_end_address_4.Q * /bp_end_address_5.Q * 
          /bp_end_address_6.Q * /bp_end_address_7.Q * sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          /bp_end_address_0.Q * /bp_end_address_1.Q * /bp_end_address_2.Q * 
          /bp_end_address_3.Q * /bp_end_address_4.Q * /bp_end_address_5.Q * 
          /bp_end_address_6.Q * /bp_end_address_7.Q * /sinphase_zeros 

    /S_10 =
          \sp_read:counter_address_0\.Q * \sp_read:counter_address_1\.Q * 
          \sp_read:counter_address_2\.Q * \sp_read:counter_address_3\.Q * 
          /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          \sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          /bp_end_address_6.Q * /bp_end_address_7.Q * sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          /bp_start_address_4.Q * sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          /sinphase_zeros 
        + /\sp_read:counter_address_4\.Q * \sp_read:old_phase\.Q 
        + /\sp_read:counter_address_4\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q 
        + /\sp_read:counter_address_4\.Q * 
          \sp_read:counter_read_stateSBV_2\.Q 
        + /\sp_read:counter_address_4\.Q * 
          \sp_read:counter_read_stateSBV_1\.Q 
        + /\sp_read:counter_address_4\.Q * 
          \sp_read:counter_read_stateSBV_0\.Q 
        + /\sp_read:counter_address_4\.Q * /sinphase_zeros 

    S_11 =
          \sp_read:counter_address_3\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * /bp_end_address_0.Q * 
          /bp_end_address_1.Q * /bp_end_address_2.Q * /bp_end_address_3.Q * 
          /bp_end_address_4.Q * /bp_end_address_5.Q * /bp_end_address_6.Q * 
          /bp_end_address_7.Q 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          bp_end_address_6.Q * bp_start_address_3.Q * sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          bp_end_address_5.Q * bp_start_address_3.Q * sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          bp_end_address_4.Q * bp_start_address_3.Q * sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          bp_end_address_3.Q * bp_start_address_3.Q * sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          bp_end_address_2.Q * bp_start_address_3.Q * sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          bp_end_address_1.Q * bp_start_address_3.Q * sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          bp_end_address_0.Q * bp_start_address_3.Q * sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          bp_end_address_7.Q * bp_start_address_3.Q * /sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          bp_end_address_6.Q * bp_start_address_3.Q * /sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          bp_end_address_5.Q * bp_start_address_3.Q * /sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          bp_end_address_4.Q * bp_start_address_3.Q * /sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          bp_end_address_3.Q * bp_start_address_3.Q * /sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          bp_end_address_2.Q * bp_start_address_3.Q * /sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          bp_end_address_1.Q * bp_start_address_3.Q * /sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          bp_end_address_0.Q * bp_start_address_3.Q * /sinphase_zeros 

    S_12 =
          /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          bp_end_address_7.Q * bp_start_address_3.Q * sinphase_zeros 
        + \sp_read:counter_address_0\.Q * \sp_read:counter_address_1\.Q * 
          \sp_read:counter_address_2\.Q * /\sp_read:counter_address_3\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          \sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q 
        + \sp_read:counter_address_3\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * \sp_read:old_phase\.Q * 
          sinphase_zeros 
        + \sp_read:counter_address_3\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * /\sp_read:old_phase\.Q * 
          /sinphase_zeros 
        + /\sp_read:counter_address_0\.Q * \sp_read:counter_address_3\.Q * 
          \sp_read:counter_read_stateSBV_2\.Q 
        + /\sp_read:counter_address_1\.Q * \sp_read:counter_address_3\.Q * 
          \sp_read:counter_read_stateSBV_2\.Q 
        + /\sp_read:counter_address_2\.Q * \sp_read:counter_address_3\.Q * 
          \sp_read:counter_read_stateSBV_2\.Q 
        + \sp_read:counter_address_3\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q 
        + \sp_read:counter_address_3\.Q * 
          \sp_read:counter_read_stateSBV_1\.Q 
        + \sp_read:counter_address_3\.Q * 
          \sp_read:counter_read_stateSBV_0\.Q 

    S_13 =
          \sp_read:counter_address_2\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * /bp_end_address_0.Q * 
          /bp_end_address_1.Q * /bp_end_address_2.Q * /bp_end_address_3.Q * 
          /bp_end_address_4.Q * /bp_end_address_5.Q * /bp_end_address_6.Q * 
          /bp_end_address_7.Q 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          bp_end_address_7.Q * bp_start_address_2.Q * sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          bp_end_address_6.Q * bp_start_address_2.Q * sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          bp_end_address_5.Q * bp_start_address_2.Q * sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          bp_end_address_4.Q * bp_start_address_2.Q * sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          bp_end_address_3.Q * bp_start_address_2.Q * sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          bp_end_address_2.Q * bp_start_address_2.Q * sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          bp_end_address_1.Q * bp_start_address_2.Q * sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          bp_end_address_0.Q * bp_start_address_2.Q * sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          bp_end_address_7.Q * bp_start_address_2.Q * /sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          bp_end_address_6.Q * bp_start_address_2.Q * /sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          bp_end_address_5.Q * bp_start_address_2.Q * /sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          bp_end_address_4.Q * bp_start_address_2.Q * /sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          bp_end_address_3.Q * bp_start_address_2.Q * /sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          bp_end_address_2.Q * bp_start_address_2.Q * /sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          bp_end_address_1.Q * bp_start_address_2.Q * /sinphase_zeros 

    S_14 =
          /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          bp_end_address_0.Q * bp_start_address_2.Q * /sinphase_zeros 
        + \sp_read:counter_address_0\.Q * \sp_read:counter_address_1\.Q * 
          /\sp_read:counter_address_2\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          \sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q 
        + \sp_read:counter_address_2\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * \sp_read:old_phase\.Q * 
          sinphase_zeros 
        + \sp_read:counter_address_2\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * /\sp_read:old_phase\.Q * 
          /sinphase_zeros 
        + /\sp_read:counter_address_0\.Q * \sp_read:counter_address_2\.Q * 
          \sp_read:counter_read_stateSBV_2\.Q 
        + /\sp_read:counter_address_1\.Q * \sp_read:counter_address_2\.Q * 
          \sp_read:counter_read_stateSBV_2\.Q 
        + \sp_read:counter_address_2\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q 
        + \sp_read:counter_address_2\.Q * 
          \sp_read:counter_read_stateSBV_1\.Q 
        + \sp_read:counter_address_2\.Q * 
          \sp_read:counter_read_stateSBV_0\.Q 

    S_15 =
          \sp_read:counter_address_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * /bp_end_address_0.Q * 
          /bp_end_address_1.Q * /bp_end_address_2.Q * /bp_end_address_3.Q * 
          /bp_end_address_4.Q * /bp_end_address_5.Q * /bp_end_address_6.Q * 
          /bp_end_address_7.Q 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          bp_end_address_7.Q * bp_start_address_1.Q * sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          bp_end_address_6.Q * bp_start_address_1.Q * sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          bp_end_address_5.Q * bp_start_address_1.Q * sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          bp_end_address_4.Q * bp_start_address_1.Q * sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          bp_end_address_3.Q * bp_start_address_1.Q * sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          bp_end_address_2.Q * bp_start_address_1.Q * sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          bp_end_address_1.Q * bp_start_address_1.Q * sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          bp_end_address_0.Q * bp_start_address_1.Q * sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          bp_end_address_7.Q * bp_start_address_1.Q * /sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          bp_end_address_6.Q * bp_start_address_1.Q * /sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          bp_end_address_5.Q * bp_start_address_1.Q * /sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          bp_end_address_4.Q * bp_start_address_1.Q * /sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          bp_end_address_3.Q * bp_start_address_1.Q * /sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          bp_end_address_2.Q * bp_start_address_1.Q * /sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          bp_end_address_1.Q * bp_start_address_1.Q * /sinphase_zeros 

    S_16 =
          /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          bp_end_address_0.Q * bp_start_address_1.Q * /sinphase_zeros 
        + \sp_read:counter_address_0\.Q * /\sp_read:counter_address_1\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          \sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q 
        + \sp_read:counter_address_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * \sp_read:old_phase\.Q * 
          sinphase_zeros 
        + \sp_read:counter_address_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * /\sp_read:old_phase\.Q * 
          /sinphase_zeros 
        + /\sp_read:counter_address_0\.Q * \sp_read:counter_address_1\.Q * 
          \sp_read:counter_read_stateSBV_2\.Q 
        + \sp_read:counter_address_1\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q 
        + \sp_read:counter_address_1\.Q * 
          \sp_read:counter_read_stateSBV_1\.Q 
        + \sp_read:counter_address_1\.Q * 
          \sp_read:counter_read_stateSBV_0\.Q 

    S_17 =
          \sp_read:counter_address_0\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * /bp_end_address_0.Q * 
          /bp_end_address_1.Q * /bp_end_address_2.Q * /bp_end_address_3.Q * 
          /bp_end_address_4.Q * /bp_end_address_5.Q * /bp_end_address_6.Q * 
          /bp_end_address_7.Q 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          bp_end_address_7.Q * bp_start_address_0.Q * sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          bp_end_address_6.Q * bp_start_address_0.Q * sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          bp_end_address_5.Q * bp_start_address_0.Q * sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          bp_end_address_4.Q * bp_start_address_0.Q * sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          bp_end_address_3.Q * bp_start_address_0.Q * sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          bp_end_address_2.Q * bp_start_address_0.Q * sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          bp_end_address_1.Q * bp_start_address_0.Q * sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          bp_end_address_0.Q * bp_start_address_0.Q * sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          bp_end_address_7.Q * bp_start_address_0.Q * /sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          bp_end_address_6.Q * bp_start_address_0.Q * /sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          bp_end_address_5.Q * bp_start_address_0.Q * /sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          bp_end_address_4.Q * bp_start_address_0.Q * /sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          bp_end_address_2.Q * bp_start_address_0.Q * /sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          bp_end_address_1.Q * bp_start_address_0.Q * /sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          bp_end_address_0.Q * bp_start_address_0.Q * /sinphase_zeros 

    S_18 =
          /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          bp_end_address_3.Q * bp_start_address_0.Q * /sinphase_zeros 
        + \sp_read:counter_address_0\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * \sp_read:old_phase\.Q * 
          sinphase_zeros 
        + /\sp_read:counter_address_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          \sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q 
        + \sp_read:counter_address_0\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * /\sp_read:old_phase\.Q * 
          /sinphase_zeros 
        + \sp_read:counter_address_0\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q 
        + \sp_read:counter_address_0\.Q * 
          \sp_read:counter_read_stateSBV_1\.Q 
        + \sp_read:counter_address_0\.Q * 
          \sp_read:counter_read_stateSBV_0\.Q 

    S_19 =
          \ibus_reader:il_read_stateSBV_0\.Q * 
          \ibus_reader:il_read_stateSBV_1\.Q * \ibus_reader:timeout_0\.Q * 
          /\ibus_reader:timeout_1\.Q * loopback_state.Q * to_pc_ack.Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          \ibus_reader:il_read_stateSBV_1\.Q * \ibus_reader:timeout_0\.Q * 
          /\ibus_reader:timeout_1\.Q * /loopback_state.Q * 
          write_to_bp_ack.Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * \ibus_reader:timeout_1\.Q * 
          \ibus_reader:timeout_2\.Q * \ibus_reader:timeout_3\.Q * 
          loopback_state.Q * /to_pc_ack.Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          \ibus_reader:il_read_stateSBV_2\.Q * \ibus_reader:timeout_0\.Q * 
          /\ibus_reader:timeout_1\.Q * loopback_state.Q * /to_pc_ack.Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * \ibus_reader:timeout_1\.Q * 
          \ibus_reader:timeout_2\.Q * \ibus_reader:timeout_3\.Q * 
          /loopback_state.Q * /write_to_bp_ack.Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          \ibus_reader:il_read_stateSBV_2\.Q * \ibus_reader:timeout_0\.Q * 
          /\ibus_reader:timeout_1\.Q * /loopback_state.Q * 
          /write_to_bp_ack.Q 
        + /\ibus_reader:il_read_stateSBV_0\.Q * 
          \ibus_reader:il_read_stateSBV_1\.Q * \ibus_reader:timeout_0\.Q * 
          /\ibus_reader:timeout_1\.Q * ao_from_pc_strobe 
        + /\ibus_reader:il_read_stateSBV_2\.Q * \ibus_reader:timeout_1\.Q * 
          \ibus_reader:timeout_2\.Q * \ibus_reader:timeout_3\.Q * 
          /ao_from_pc_strobe 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * \ibus_reader:timeout_1\.Q * 
          loopback_state.Q * /to_pc_ack.Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * /\ibus_reader:timeout_0\.Q * 
          \ibus_reader:timeout_1\.Q * loopback_state.Q * /to_pc_ack.Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * \ibus_reader:timeout_1\.Q * 
          /loopback_state.Q * /write_to_bp_ack.Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * /\ibus_reader:timeout_0\.Q * 
          \ibus_reader:timeout_1\.Q * /loopback_state.Q * 
          /write_to_bp_ack.Q 
        + /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          \ibus_reader:il_read_stateSBV_2\.Q * \ibus_reader:timeout_1\.Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * \ibus_reader:timeout_1\.Q 
        + \ibus_reader:il_read_stateSBV_1\.Q * /\ibus_reader:timeout_0\.Q * 
          \ibus_reader:timeout_1\.Q * ao_from_pc_strobe 
        + /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * \ibus_reader:timeout_1\.Q * 
          /ao_from_pc_strobe 

    S_2 =
          \sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * 
          /\sp_read:delay_count_0\.Q * \sp_read:delay_count_1\.Q * 
          \sp_read:delay_count_2\.Q * /\sp_read:delay_count_3\.Q * 
          /\sp_read:delay_count_4\.Q * /\sp_read:delay_count_5\.Q * 
          /\sp_read:delay_count_6\.Q * /\sp_read:delay_count_7\.Q * 
          \sp_read:delay_count_8\.Q * /\sp_read:delay_count_9\.Q 
        + \sp_read:counter_address_0\.Q * /\sp_read:counter_address_1\.Q * 
          /\sp_read:counter_address_2\.Q * /\sp_read:counter_address_3\.Q * 
          \sp_read:counter_address_4\.Q * \sp_read:counter_address_5\.Q * 
          \sp_read:counter_address_6\.Q * /\sp_read:counter_address_7\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          \sp_read:counter_read_stateSBV_2\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q 
        + \sp_read:counter_address_0\.Q * \sp_read:counter_address_1\.Q * 
          /\sp_read:counter_address_3\.Q * /\sp_read:counter_address_4\.Q * 
          /\sp_read:counter_address_7\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          \sp_read:counter_read_stateSBV_2\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q 
        + \sp_read:counter_address_0\.Q * \sp_read:counter_address_1\.Q * 
          /\sp_read:counter_address_3\.Q * /\sp_read:counter_address_5\.Q * 
          /\sp_read:counter_address_7\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          \sp_read:counter_read_stateSBV_2\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q 
        + \sp_read:counter_address_0\.Q * \sp_read:counter_address_1\.Q * 
          /\sp_read:counter_address_4\.Q * /\sp_read:counter_address_5\.Q * 
          /\sp_read:counter_address_7\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          \sp_read:counter_read_stateSBV_2\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q 
        + \sp_read:counter_address_0\.Q * \sp_read:counter_address_1\.Q * 
          /\sp_read:counter_address_3\.Q * /\sp_read:counter_address_6\.Q * 
          /\sp_read:counter_address_7\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          \sp_read:counter_read_stateSBV_2\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q 
        + \sp_read:counter_address_0\.Q * \sp_read:counter_address_1\.Q * 
          /\sp_read:counter_address_4\.Q * /\sp_read:counter_address_6\.Q * 
          /\sp_read:counter_address_7\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          \sp_read:counter_read_stateSBV_2\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q 
        + \sp_read:counter_address_3\.Q * \sp_read:counter_address_4\.Q * 
          /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q 
        + \sp_read:counter_read_stateSBV_1\.Q * 
          \sp_read:counter_read_stateSBV_2\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q * /loopback_state.Q * 
          to_pc_ack.Q 
        + /\sp_read:counter_read_stateSBV_1\.Q * 
          \sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /loopback_state.Q * 
          to_pc_ack.Q 
        + \sp_read:cmp_vv_us_MODGEN_10\.CMB * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          \sp_read:counter_read_stateSBV_2\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q 
        + \sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q * sensor_to_bp_read_ack.Q 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          \sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q 
        + \sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * loopback_state.Q 
        + \sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /to_pc_ack.Q 

    S_20 =
          \ibus_reader:il_read_stateSBV_1\.Q * \ibus_reader:timeout_1\.Q * 
          \ibus_reader:timeout_2\.Q * \ibus_reader:timeout_3\.Q * 
          ao_from_pc_strobe 
        + /\ibus_reader:il_read_stateSBV_0\.Q * 
          \ibus_reader:this_is_a_ctrl_transaction\.Q * 
          \ibus_reader:timeout_1\.Q * /ao_from_pc_strobe 
        + /\ibus_reader:il_read_stateSBV_2\.Q * /\ibus_reader:timeout_0\.Q * 
          \ibus_reader:timeout_1\.Q * /ao_from_pc_strobe 

    S_3 =
          \sp_read:counter_address_0\.Q * \sp_read:counter_address_1\.Q * 
          \sp_read:counter_address_2\.Q * \sp_read:counter_address_3\.Q * 
          \sp_read:counter_address_4\.Q * \sp_read:counter_address_5\.Q * 
          \sp_read:counter_address_6\.Q * /\sp_read:counter_address_7\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          \sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q 
        + \sp_read:counter_address_7\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * /bp_end_address_0.Q * 
          /bp_end_address_1.Q * /bp_end_address_2.Q * /bp_end_address_3.Q * 
          /bp_end_address_4.Q * /bp_end_address_5.Q * /bp_end_address_6.Q * 
          /bp_end_address_7.Q 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          bp_end_address_7.Q * bp_start_address_7.Q * sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          bp_end_address_6.Q * bp_start_address_7.Q * sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          bp_end_address_5.Q * bp_start_address_7.Q * sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          bp_end_address_4.Q * bp_start_address_7.Q * sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          bp_end_address_1.Q * bp_start_address_7.Q * sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          bp_end_address_0.Q * bp_start_address_7.Q * sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          bp_end_address_7.Q * bp_start_address_7.Q * /sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          bp_end_address_6.Q * bp_start_address_7.Q * /sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          bp_end_address_5.Q * bp_start_address_7.Q * /sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          bp_end_address_4.Q * bp_start_address_7.Q * /sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          bp_end_address_3.Q * bp_start_address_7.Q * /sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          bp_end_address_2.Q * bp_start_address_7.Q * /sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          bp_end_address_1.Q * bp_start_address_7.Q * /sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          bp_end_address_0.Q * bp_start_address_7.Q * /sinphase_zeros 

    /S_4 =
          \sp_read:counter_address_0\.Q * \sp_read:counter_address_1\.Q * 
          \sp_read:counter_address_2\.Q * \sp_read:counter_address_3\.Q * 
          \sp_read:counter_address_4\.Q * \sp_read:counter_address_5\.Q * 
          \sp_read:counter_address_6\.Q * 
          /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          \sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          /bp_end_address_2.Q * /bp_end_address_3.Q * sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          /bp_start_address_7.Q * sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          /sinphase_zeros 
        + /\sp_read:counter_address_7\.Q * \sp_read:old_phase\.Q 
        + /\sp_read:counter_address_7\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q 
        + /\sp_read:counter_address_7\.Q * 
          \sp_read:counter_read_stateSBV_2\.Q 
        + /\sp_read:counter_address_7\.Q * 
          \sp_read:counter_read_stateSBV_1\.Q 
        + /\sp_read:counter_address_7\.Q * 
          \sp_read:counter_read_stateSBV_0\.Q 
        + /\sp_read:counter_address_7\.Q * /sinphase_zeros 

    S_5 =
          \sp_read:counter_address_6\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * /bp_end_address_0.Q * 
          /bp_end_address_1.Q * /bp_end_address_2.Q * /bp_end_address_3.Q * 
          /bp_end_address_4.Q * /bp_end_address_5.Q * /bp_end_address_6.Q * 
          /bp_end_address_7.Q 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          bp_end_address_4.Q * bp_start_address_6.Q * sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          bp_end_address_3.Q * bp_start_address_6.Q * sinphase_zeros 
        + \sp_read:counter_address_6\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * \sp_read:old_phase\.Q * 
          sinphase_zeros 
        + \sp_read:counter_address_6\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * /\sp_read:old_phase\.Q * 
          /sinphase_zeros 
        + /\sp_read:counter_address_0\.Q * \sp_read:counter_address_6\.Q * 
          \sp_read:counter_read_stateSBV_2\.Q 
        + /\sp_read:counter_address_1\.Q * \sp_read:counter_address_6\.Q * 
          \sp_read:counter_read_stateSBV_2\.Q 
        + /\sp_read:counter_address_2\.Q * \sp_read:counter_address_6\.Q * 
          \sp_read:counter_read_stateSBV_2\.Q 
        + /\sp_read:counter_address_3\.Q * \sp_read:counter_address_6\.Q * 
          \sp_read:counter_read_stateSBV_2\.Q 
        + /\sp_read:counter_address_4\.Q * \sp_read:counter_address_6\.Q * 
          \sp_read:counter_read_stateSBV_2\.Q 
        + /\sp_read:counter_address_5\.Q * \sp_read:counter_address_6\.Q * 
          \sp_read:counter_read_stateSBV_2\.Q 
        + \sp_read:counter_address_6\.Q * 
          \sp_read:counter_read_stateSBV_1\.Q 
        + \sp_read:counter_address_6\.Q * 
          \sp_read:counter_read_stateSBV_0\.Q 

    /S_6 =
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /bp_end_address_0.Q * 
          /bp_end_address_1.Q * /bp_end_address_2.Q * /bp_end_address_3.Q * 
          /bp_end_address_4.Q * /bp_end_address_5.Q * /bp_end_address_6.Q * 
          /bp_end_address_7.Q 
        + /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /bp_end_address_0.Q * 
          /bp_end_address_1.Q * /bp_end_address_2.Q * /bp_end_address_5.Q * 
          /bp_end_address_6.Q * /bp_end_address_7.Q * sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          /sinphase_zeros 
        + \sp_read:counter_address_6\.Q * 
          \sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q 
        + /\sp_read:counter_address_0\.Q * 
          \sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q 
        + /\sp_read:counter_address_1\.Q * 
          \sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q 
        + /\sp_read:counter_address_2\.Q * 
          \sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q 
        + /\sp_read:counter_address_3\.Q * 
          \sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q 
        + /\sp_read:counter_address_4\.Q * 
          \sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q 
        + /\sp_read:counter_address_5\.Q * 
          \sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q 
        + \sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q 
        + /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /bp_start_address_6.Q 
        + /\sp_read:counter_address_6\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q 
        + \sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q 

    S_7 =
          \sp_read:counter_address_5\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * /bp_end_address_0.Q * 
          /bp_end_address_1.Q * /bp_end_address_2.Q * /bp_end_address_3.Q * 
          /bp_end_address_4.Q * /bp_end_address_5.Q * /bp_end_address_6.Q * 
          /bp_end_address_7.Q 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          bp_end_address_5.Q * bp_start_address_5.Q * sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          bp_end_address_4.Q * bp_start_address_5.Q * sinphase_zeros 
        + \sp_read:counter_address_5\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * \sp_read:old_phase\.Q * 
          sinphase_zeros 
        + \sp_read:counter_address_5\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * /\sp_read:old_phase\.Q * 
          /sinphase_zeros 
        + /\sp_read:counter_address_0\.Q * \sp_read:counter_address_5\.Q * 
          \sp_read:counter_read_stateSBV_2\.Q 
        + /\sp_read:counter_address_1\.Q * \sp_read:counter_address_5\.Q * 
          \sp_read:counter_read_stateSBV_2\.Q 
        + /\sp_read:counter_address_2\.Q * \sp_read:counter_address_5\.Q * 
          \sp_read:counter_read_stateSBV_2\.Q 
        + /\sp_read:counter_address_3\.Q * \sp_read:counter_address_5\.Q * 
          \sp_read:counter_read_stateSBV_2\.Q 
        + /\sp_read:counter_address_4\.Q * \sp_read:counter_address_5\.Q * 
          \sp_read:counter_read_stateSBV_2\.Q 
        + \sp_read:counter_address_5\.Q * 
          \sp_read:counter_read_stateSBV_1\.Q 
        + \sp_read:counter_address_5\.Q * 
          \sp_read:counter_read_stateSBV_0\.Q 

    /S_8 =
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /bp_end_address_0.Q * 
          /bp_end_address_1.Q * /bp_end_address_2.Q * /bp_end_address_3.Q * 
          /bp_end_address_4.Q * /bp_end_address_5.Q * /bp_end_address_6.Q * 
          /bp_end_address_7.Q 
        + /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /bp_end_address_0.Q * 
          /bp_end_address_1.Q * /bp_end_address_2.Q * /bp_end_address_3.Q * 
          /bp_end_address_6.Q * /bp_end_address_7.Q * sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          /sinphase_zeros 
        + \sp_read:counter_address_5\.Q * 
          \sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q 
        + /\sp_read:counter_address_0\.Q * 
          \sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q 
        + /\sp_read:counter_address_1\.Q * 
          \sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q 
        + /\sp_read:counter_address_2\.Q * 
          \sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q 
        + /\sp_read:counter_address_3\.Q * 
          \sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q 
        + /\sp_read:counter_address_4\.Q * 
          \sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q 
        + \sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q 
        + /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /bp_start_address_5.Q 
        + /\sp_read:counter_address_5\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q 
        + \sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q 

    S_9 =
          \sp_read:counter_address_4\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * /bp_end_address_0.Q * 
          /bp_end_address_1.Q * /bp_end_address_2.Q * /bp_end_address_3.Q * 
          /bp_end_address_4.Q * /bp_end_address_5.Q * /bp_end_address_6.Q * 
          /bp_end_address_7.Q 
        + \sp_read:counter_address_0\.Q * \sp_read:counter_address_1\.Q * 
          \sp_read:counter_address_2\.Q * \sp_read:counter_address_3\.Q * 
          /\sp_read:counter_address_4\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          \sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          bp_end_address_5.Q * bp_start_address_4.Q * sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          bp_end_address_4.Q * bp_start_address_4.Q * sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          bp_end_address_3.Q * bp_start_address_4.Q * sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          bp_end_address_2.Q * bp_start_address_4.Q * sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          bp_end_address_1.Q * bp_start_address_4.Q * sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          bp_end_address_0.Q * bp_start_address_4.Q * sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          bp_end_address_7.Q * bp_start_address_4.Q * /sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          bp_end_address_6.Q * bp_start_address_4.Q * /sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          bp_end_address_5.Q * bp_start_address_4.Q * /sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          bp_end_address_4.Q * bp_start_address_4.Q * /sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          bp_end_address_3.Q * bp_start_address_4.Q * /sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          bp_end_address_2.Q * bp_start_address_4.Q * /sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          bp_end_address_1.Q * bp_start_address_4.Q * /sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          bp_end_address_0.Q * bp_start_address_4.Q * /sinphase_zeros 

    \bp_io:bp_access_stateSBV_0\.T =
          \bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_1\.Q * 
          \bp_io:bp_access_stateSBV_2\.Q * \bp_io:timeout_0\.Q * 
          \bp_io:timeout_1\.Q * \bp_io:timeout_2\.Q 
        + \bp_io:bp_access_stateSBV_0\.Q * /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * \bp_io:timeout_0\.Q * 
          \bp_io:timeout_1\.Q * \bp_io:timeout_2\.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_1\.Q * 
          \bp_io:bp_access_stateSBV_2\.Q * /\bp_io:timeout_0\.Q * 
          \bp_io:timeout_1\.Q * /\bp_io:timeout_2\.Q 
        + /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * loopback_state.Q * 
          sensor_to_bp_read_req.Q 
        + \bp_io:bp_access_stateSBV_0\.Q * /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * loopback_state.Q 
        + /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /from_pc_req.Q * 
          sensor_to_bp_read_req.Q 
        + \bp_io:bp_access_stateSBV_0\.Q * /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /from_pc_req.Q 
        + \bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_1\.Q * 
          \bp_io:bp_access_stateSBV_2\.Q * /sensor_to_bp_read_req.Q 

    \bp_io:bp_access_stateSBV_0\.C =
          clk 

    \bp_io:bp_access_stateSBV_1\.T =
          \bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_1\.Q * 
          \bp_io:bp_access_stateSBV_2\.Q * \bp_io:timeout_0\.Q * 
          \bp_io:timeout_1\.Q * \bp_io:timeout_2\.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_2\.Q * 
          /\bp_io:timeout_0\.Q * \bp_io:timeout_1\.Q * 
          /\bp_io:timeout_2\.Q 
        + /\bp_io:bp_access_stateSBV_1\.Q * \bp_io:bp_access_stateSBV_2\.Q * 
          /\bp_io:timeout_0\.Q * \bp_io:timeout_1\.Q * 
          /\bp_io:timeout_2\.Q 
        + \bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_1\.Q * 
          \bp_io:bp_access_stateSBV_2\.Q * /sensor_to_bp_read_req.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_1\.Q * \bp_io:bp_access_stateSBV_2\.Q 

    \bp_io:bp_access_stateSBV_1\.C =
          clk 

    \bp_io:bp_access_stateSBV_2\.T =
          \bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_1\.Q * 
          \bp_io:bp_access_stateSBV_2\.Q * \bp_io:timeout_0\.Q * 
          \bp_io:timeout_1\.Q * \bp_io:timeout_2\.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_2\.Q * 
          /\bp_io:timeout_0\.Q * \bp_io:timeout_1\.Q * 
          /\bp_io:timeout_2\.Q 
        + /\bp_io:bp_access_stateSBV_1\.Q * \bp_io:bp_access_stateSBV_2\.Q * 
          /\bp_io:timeout_0\.Q * \bp_io:timeout_1\.Q * 
          /\bp_io:timeout_2\.Q 
        + \bp_io:bp_access_stateSBV_1\.Q * /\bp_io:bp_access_stateSBV_2\.Q * 
          /\bp_io:timeout_0\.Q * \bp_io:timeout_1\.Q * 
          /\bp_io:timeout_2\.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_1\.Q * from_pc_req.Q * 
          /loopback_state.Q 
        + \bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_1\.Q * 
          \bp_io:bp_access_stateSBV_2\.Q * /sensor_to_bp_read_req.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_1\.Q * sensor_to_bp_read_req.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_1\.Q * \bp_io:bp_access_stateSBV_2\.Q 

    \bp_io:bp_access_stateSBV_2\.C =
          clk 

    \bp_io:timeout_0\.D =
          \bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_1\.Q * 
          \bp_io:bp_access_stateSBV_2\.Q * \bp_io:timeout_1\.Q * 
          \bp_io:timeout_2\.Q * sensor_to_bp_read_req.Q 
        + \bp_io:bp_access_stateSBV_0\.Q * /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * \bp_io:timeout_0\.Q * 
          \bp_io:timeout_1\.Q * \bp_io:timeout_2\.Q 
        + \bp_io:bp_access_stateSBV_0\.Q * /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * \bp_io:timeout_0\.Q * 
          loopback_state.Q 
        + \bp_io:bp_access_stateSBV_0\.Q * /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * \bp_io:timeout_0\.Q * 
          /from_pc_req.Q 
        + \bp_io:bp_access_stateSBV_0\.Q * /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:timeout_0\.Q * from_pc_req.Q * /loopback_state.Q 
        + \bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_1\.Q * 
          \bp_io:bp_access_stateSBV_2\.Q * \bp_io:timeout_0\.Q * 
          /sensor_to_bp_read_req.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_1\.Q * \bp_io:bp_access_stateSBV_2\.Q * 
          \bp_io:timeout_0\.Q 
        + \bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_2\.Q * 
          /\bp_io:timeout_0\.Q * sensor_to_bp_read_req.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:timeout_0\.Q * \bp_io:timeout_2\.Q 
        + \bp_io:bp_access_stateSBV_0\.Q * /\bp_io:bp_access_stateSBV_1\.Q * 
          \bp_io:bp_access_stateSBV_2\.Q * /\bp_io:timeout_0\.Q 
        + \bp_io:bp_access_stateSBV_1\.Q * /\bp_io:bp_access_stateSBV_2\.Q * 
          /\bp_io:timeout_0\.Q * \bp_io:timeout_2\.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:timeout_0\.Q * /\bp_io:timeout_1\.Q 
        + \bp_io:bp_access_stateSBV_1\.Q * /\bp_io:bp_access_stateSBV_2\.Q * 
          /\bp_io:timeout_0\.Q * /\bp_io:timeout_1\.Q 

    \bp_io:timeout_0\.C =
          clk 

    \bp_io:timeout_1\.T =
          \bp_io:bp_access_stateSBV_0\.Q * /\bp_io:bp_access_stateSBV_2\.Q * 
          \bp_io:timeout_0\.Q * /\bp_io:timeout_1\.Q * from_pc_req.Q * 
          /loopback_state.Q 
        + \bp_io:bp_access_stateSBV_0\.Q * /\bp_io:bp_access_stateSBV_2\.Q * 
          \bp_io:timeout_0\.Q * /\bp_io:timeout_2\.Q * from_pc_req.Q * 
          /loopback_state.Q 
        + \bp_io:bp_access_stateSBV_0\.Q * /\bp_io:bp_access_stateSBV_1\.Q * 
          \bp_io:bp_access_stateSBV_2\.Q * \bp_io:timeout_0\.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * \bp_io:timeout_1\.Q 
        + \bp_io:bp_access_stateSBV_1\.Q * \bp_io:timeout_0\.Q * 
          /\bp_io:timeout_1\.Q * sensor_to_bp_read_req.Q 
        + \bp_io:bp_access_stateSBV_1\.Q * \bp_io:timeout_0\.Q * 
          /\bp_io:timeout_2\.Q * sensor_to_bp_read_req.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_1\.Q * 
          \bp_io:timeout_1\.Q * /\bp_io:timeout_2\.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_1\.Q * 
          \bp_io:timeout_0\.Q 
        + \bp_io:bp_access_stateSBV_1\.Q * /\bp_io:bp_access_stateSBV_2\.Q * 
          \bp_io:timeout_0\.Q 

    \bp_io:timeout_1\.C =
          clk 

    \bp_io:timeout_2\.T =
          \bp_io:bp_access_stateSBV_0\.Q * /\bp_io:bp_access_stateSBV_2\.Q * 
          \bp_io:timeout_0\.Q * \bp_io:timeout_1\.Q * /\bp_io:timeout_2\.Q * 
          from_pc_req.Q * /loopback_state.Q 
        + \bp_io:bp_access_stateSBV_0\.Q * /\bp_io:bp_access_stateSBV_1\.Q * 
          \bp_io:bp_access_stateSBV_2\.Q * \bp_io:timeout_0\.Q * 
          \bp_io:timeout_1\.Q 
        + \bp_io:bp_access_stateSBV_1\.Q * \bp_io:timeout_0\.Q * 
          \bp_io:timeout_1\.Q * /\bp_io:timeout_2\.Q * 
          sensor_to_bp_read_req.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_1\.Q * 
          \bp_io:timeout_0\.Q * \bp_io:timeout_1\.Q 
        + \bp_io:bp_access_stateSBV_1\.Q * /\bp_io:bp_access_stateSBV_2\.Q * 
          \bp_io:timeout_0\.Q * \bp_io:timeout_1\.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * \bp_io:timeout_2\.Q 

    \bp_io:timeout_2\.C =
          clk 

    \ibus_reader:il_read_stateSBV_0\.T =
          \ibus_reader:il_read_stateSBV_0\.Q * 
          \ibus_reader:il_read_stateSBV_2\.Q * \ibus_reader:timeout_0\.Q * 
          \ibus_reader:timeout_1\.Q * \ibus_reader:timeout_2\.Q * 
          \ibus_reader:timeout_3\.Q * ao_from_pc_strobe * loopback_state.Q * 
          /to_pc_ack.Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          \ibus_reader:il_read_stateSBV_2\.Q * \ibus_reader:timeout_0\.Q * 
          \ibus_reader:timeout_1\.Q * \ibus_reader:timeout_2\.Q * 
          \ibus_reader:timeout_3\.Q * loopback_state.Q * /to_pc_ack.Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * \ibus_reader:timeout_0\.Q * 
          \ibus_reader:timeout_1\.Q * \ibus_reader:timeout_2\.Q * 
          \ibus_reader:timeout_3\.Q * ao_from_pc_strobe * 
          /loopback_state.Q * /write_to_bp_ack.Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * \ibus_reader:timeout_0\.Q * 
          \ibus_reader:timeout_1\.Q * \ibus_reader:timeout_2\.Q * 
          \ibus_reader:timeout_3\.Q * /loopback_state.Q * 
          /write_to_bp_ack.Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          \ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * \ibus_reader:timeout_0\.Q * 
          \ibus_reader:timeout_1\.Q * \ibus_reader:timeout_2\.Q * 
          \ibus_reader:timeout_3\.Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          \ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * loopback_state.Q * 
          /to_pc_ack.Q 
        + /\ibus_reader:il_read_stateSBV_0\.Q * 
          \ibus_reader:il_read_stateSBV_1\.Q * /ao_from_pc_strobe * 
          loopback_state.Q 
        + /\ibus_reader:il_read_stateSBV_0\.Q * 
          \ibus_reader:il_read_stateSBV_1\.Q * 
          \ibus_reader:il_read_stateSBV_2\.Q * /ao_from_pc_strobe 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * /loopback_state.Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * /loopback_state.Q * 
          /write_to_bp_ack.Q 

    \ibus_reader:il_read_stateSBV_0\.C =
          clk 

    \ibus_reader:il_read_stateSBV_1\.T =
          /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          \ibus_reader:il_read_stateSBV_2\.Q * /bpctrl(10).Q * 
          bpctrl(11).Q * /bpctrl(7).Q * /bpctrl(8).Q * data_from_pc_15.Q 
        + /\ibus_reader:il_read_stateSBV_0\.Q * 
          \ibus_reader:il_read_stateSBV_1\.Q * \ibus_reader:timeout_0\.Q * 
          \ibus_reader:timeout_1\.Q * \ibus_reader:timeout_2\.Q * 
          \ibus_reader:timeout_3\.Q 
        + \ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * \ibus_reader:timeout_0\.Q * 
          \ibus_reader:timeout_1\.Q * \ibus_reader:timeout_2\.Q * 
          \ibus_reader:timeout_3\.Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          \ibus_reader:il_read_stateSBV_2\.Q * loopback_state.Q * 
          to_pc_ack.Q 
        + /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          \ibus_reader:il_read_stateSBV_2\.Q * /data_from_pc_15.Q * 
          this_chip_selected.Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          \ibus_reader:il_read_stateSBV_2\.Q * /loopback_state.Q * 
          write_to_bp_ack.Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          \ibus_reader:il_read_stateSBV_1\.Q * loopback_state.Q * 
          /to_pc_ack.Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          \ibus_reader:il_read_stateSBV_1\.Q * /loopback_state.Q * 
          /write_to_bp_ack.Q 
        + /\ibus_reader:il_read_stateSBV_0\.Q * 
          \ibus_reader:il_read_stateSBV_1\.Q * /ao_from_pc_strobe 

    \ibus_reader:il_read_stateSBV_1\.C =
          clk 

    \ibus_reader:il_read_stateSBV_2\.T =
          \ibus_reader:il_read_stateSBV_1\.Q * 
          \ibus_reader:il_read_stateSBV_2\.Q * \ibus_reader:timeout_0\.Q * 
          \ibus_reader:timeout_1\.Q * \ibus_reader:timeout_2\.Q * 
          \ibus_reader:timeout_3\.Q * ao_from_pc_strobe 
        + \ibus_reader:il_read_stateSBV_1\.Q * 
          \ibus_reader:il_read_stateSBV_2\.Q * 
          \ibus_reader:this_is_a_ctrl_transaction\.Q * 
          \ibus_reader:timeout_0\.Q * \ibus_reader:timeout_1\.Q * 
          \ibus_reader:timeout_2\.Q * \ibus_reader:timeout_3\.Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          \ibus_reader:il_read_stateSBV_2\.Q * \ibus_reader:timeout_0\.Q * 
          \ibus_reader:timeout_1\.Q * \ibus_reader:timeout_2\.Q * 
          \ibus_reader:timeout_3\.Q 
        + \ibus_reader:il_read_stateSBV_1\.Q * 
          \ibus_reader:il_read_stateSBV_2\.Q * 
          \ibus_reader:this_is_a_ctrl_transaction\.Q * /ao_from_pc_strobe * 
          loopback_state.Q * to_pc_ack.Q 
        + \ibus_reader:il_read_stateSBV_1\.Q * 
          \ibus_reader:il_read_stateSBV_2\.Q * 
          \ibus_reader:this_is_a_ctrl_transaction\.Q * /ao_from_pc_strobe * 
          /loopback_state.Q * write_to_bp_ack.Q 
        + /\ibus_reader:il_read_stateSBV_0\.Q * 
          \ibus_reader:il_read_stateSBV_1\.Q * 
          \ibus_reader:il_read_stateSBV_2\.Q * 
          \ibus_reader:this_is_a_ctrl_transaction\.Q * /ao_from_pc_strobe 
        + /\ibus_reader:il_read_stateSBV_0\.Q * 
          \ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * /ao_from_pc_strobe * 
          loopback_state.Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          \ibus_reader:il_read_stateSBV_2\.Q * /loopback_state.Q * 
          write_to_bp_ack.Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * loopback_state.Q * 
          to_pc_ack.Q 
        + /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          \ibus_reader:il_read_stateSBV_2\.Q * data_from_pc_15.Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * loopback_state.Q 
        + /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * ao_from_pc_strobe 
        + /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          \ibus_reader:il_read_stateSBV_2\.Q * /this_chip_selected.Q 

    \ibus_reader:il_read_stateSBV_2\.C =
          clk 

    \ibus_reader:this_is_a_ctrl_transaction\.D =
          /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          \ibus_reader:il_read_stateSBV_2\.Q * /bpctrl(10).Q * 
          bpctrl(11).Q * bpctrl(6).Q * /bpctrl(7).Q * /bpctrl(8).Q * 
          data_from_pc_15.Q 
        + \ibus_reader:il_read_stateSBV_1\.Q * 
          \ibus_reader:this_is_a_ctrl_transaction\.Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          \ibus_reader:this_is_a_ctrl_transaction\.Q 
        + /\ibus_reader:il_read_stateSBV_2\.Q * 
          \ibus_reader:this_is_a_ctrl_transaction\.Q 
        + \ibus_reader:this_is_a_ctrl_transaction\.Q * /data_from_pc_15.Q 

    \ibus_reader:this_is_a_ctrl_transaction\.AP =
          GND

    \ibus_reader:this_is_a_ctrl_transaction\.AR =
          reset.CMB 

    \ibus_reader:this_is_a_ctrl_transaction\.C =
          clk 

    \ibus_reader:timeout_0\.D =
          \ibus_reader:il_read_stateSBV_0\.Q * \ibus_reader:timeout_0\.Q * 
          \ibus_reader:timeout_1\.Q * \ibus_reader:timeout_2\.Q * 
          \ibus_reader:timeout_3\.Q * loopback_state.Q * /to_pc_ack.Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * \ibus_reader:timeout_0\.Q * 
          \ibus_reader:timeout_1\.Q * \ibus_reader:timeout_2\.Q * 
          \ibus_reader:timeout_3\.Q * /loopback_state.Q * 
          /write_to_bp_ack.Q 
        + \ibus_reader:il_read_stateSBV_1\.Q * \ibus_reader:timeout_0\.Q * 
          \ibus_reader:timeout_1\.Q * \ibus_reader:timeout_2\.Q * 
          \ibus_reader:timeout_3\.Q * ao_from_pc_strobe 
        + /\ibus_reader:il_read_stateSBV_2\.Q * \ibus_reader:timeout_0\.Q * 
          \ibus_reader:timeout_1\.Q * \ibus_reader:timeout_2\.Q * 
          \ibus_reader:timeout_3\.Q * /ao_from_pc_strobe 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          \ibus_reader:il_read_stateSBV_1\.Q * /\ibus_reader:timeout_0\.Q * 
          loopback_state.Q * to_pc_ack.Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          \ibus_reader:il_read_stateSBV_1\.Q * /\ibus_reader:timeout_0\.Q * 
          /loopback_state.Q * write_to_bp_ack.Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * \ibus_reader:timeout_0\.Q * 
          loopback_state.Q * /to_pc_ack.Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          \ibus_reader:il_read_stateSBV_2\.Q * /\ibus_reader:timeout_0\.Q * 
          loopback_state.Q * /to_pc_ack.Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * \ibus_reader:timeout_0\.Q * 
          /loopback_state.Q * /write_to_bp_ack.Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          \ibus_reader:il_read_stateSBV_2\.Q * /\ibus_reader:timeout_0\.Q * 
          /loopback_state.Q * /write_to_bp_ack.Q 
        + /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          \ibus_reader:il_read_stateSBV_2\.Q * \ibus_reader:timeout_0\.Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * \ibus_reader:timeout_0\.Q 
        + /\ibus_reader:il_read_stateSBV_0\.Q * 
          \ibus_reader:il_read_stateSBV_1\.Q * /\ibus_reader:timeout_0\.Q * 
          ao_from_pc_strobe 
        + /\ibus_reader:il_read_stateSBV_0\.Q * 
          \ibus_reader:this_is_a_ctrl_transaction\.Q * 
          \ibus_reader:timeout_0\.Q * /ao_from_pc_strobe 
        + /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * \ibus_reader:timeout_0\.Q * 
          /ao_from_pc_strobe 

    \ibus_reader:timeout_0\.C =
          clk 

    \ibus_reader:timeout_1\.D =
          S_20.CMB 
        + S_19.CMB 

    \ibus_reader:timeout_1\.C =
          clk 

    \ibus_reader:timeout_2\.T =
          \ibus_reader:il_read_stateSBV_0\.Q * 
          \ibus_reader:il_read_stateSBV_1\.Q * \ibus_reader:timeout_0\.Q * 
          \ibus_reader:timeout_1\.Q * /\ibus_reader:timeout_2\.Q * 
          loopback_state.Q * to_pc_ack.Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          \ibus_reader:il_read_stateSBV_1\.Q * \ibus_reader:timeout_0\.Q * 
          \ibus_reader:timeout_1\.Q * /\ibus_reader:timeout_3\.Q * 
          loopback_state.Q * to_pc_ack.Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          \ibus_reader:il_read_stateSBV_1\.Q * \ibus_reader:timeout_0\.Q * 
          \ibus_reader:timeout_1\.Q * /\ibus_reader:timeout_2\.Q * 
          /loopback_state.Q * write_to_bp_ack.Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          \ibus_reader:il_read_stateSBV_1\.Q * \ibus_reader:timeout_0\.Q * 
          \ibus_reader:timeout_1\.Q * /\ibus_reader:timeout_3\.Q * 
          /loopback_state.Q * write_to_bp_ack.Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          \ibus_reader:il_read_stateSBV_2\.Q * \ibus_reader:timeout_0\.Q * 
          \ibus_reader:timeout_1\.Q * /\ibus_reader:timeout_2\.Q * 
          loopback_state.Q * /to_pc_ack.Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          \ibus_reader:il_read_stateSBV_2\.Q * \ibus_reader:timeout_0\.Q * 
          \ibus_reader:timeout_1\.Q * /\ibus_reader:timeout_2\.Q * 
          /loopback_state.Q * /write_to_bp_ack.Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          \ibus_reader:il_read_stateSBV_2\.Q * \ibus_reader:timeout_2\.Q * 
          loopback_state.Q * to_pc_ack.Q 
        + /\ibus_reader:il_read_stateSBV_0\.Q * 
          \ibus_reader:il_read_stateSBV_1\.Q * \ibus_reader:timeout_0\.Q * 
          \ibus_reader:timeout_1\.Q * /\ibus_reader:timeout_2\.Q * 
          ao_from_pc_strobe 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          \ibus_reader:il_read_stateSBV_2\.Q * \ibus_reader:timeout_0\.Q * 
          \ibus_reader:timeout_1\.Q * \ibus_reader:timeout_2\.Q * 
          /\ibus_reader:timeout_3\.Q 
        + /\ibus_reader:il_read_stateSBV_0\.Q * 
          \ibus_reader:il_read_stateSBV_1\.Q * \ibus_reader:timeout_0\.Q * 
          \ibus_reader:timeout_1\.Q * /\ibus_reader:timeout_3\.Q * 
          ao_from_pc_strobe 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          \ibus_reader:il_read_stateSBV_2\.Q * \ibus_reader:timeout_2\.Q * 
          /ao_from_pc_strobe * loopback_state.Q * to_pc_ack.Q 
        + /\ibus_reader:il_read_stateSBV_0\.Q * 
          \ibus_reader:il_read_stateSBV_1\.Q * 
          \ibus_reader:il_read_stateSBV_2\.Q * 
          /\ibus_reader:this_is_a_ctrl_transaction\.Q * 
          \ibus_reader:timeout_2\.Q * /ao_from_pc_strobe 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          \ibus_reader:il_read_stateSBV_2\.Q * \ibus_reader:timeout_2\.Q * 
          /loopback_state.Q * write_to_bp_ack.Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          \ibus_reader:il_read_stateSBV_2\.Q * \ibus_reader:timeout_2\.Q * 
          /ao_from_pc_strobe * /loopback_state.Q * write_to_bp_ack.Q 
        + /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * \ibus_reader:timeout_2\.Q * 
          ao_from_pc_strobe 

    \ibus_reader:timeout_2\.C =
          clk 

    \ibus_reader:timeout_3\.D =
          \ibus_reader:il_read_stateSBV_0\.Q * 
          \ibus_reader:il_read_stateSBV_1\.Q * \ibus_reader:timeout_0\.Q * 
          \ibus_reader:timeout_1\.Q * \ibus_reader:timeout_2\.Q * 
          loopback_state.Q * to_pc_ack.Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          \ibus_reader:il_read_stateSBV_1\.Q * \ibus_reader:timeout_0\.Q * 
          \ibus_reader:timeout_1\.Q * \ibus_reader:timeout_2\.Q * 
          /loopback_state.Q * write_to_bp_ack.Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          \ibus_reader:il_read_stateSBV_2\.Q * \ibus_reader:timeout_0\.Q * 
          \ibus_reader:timeout_1\.Q * \ibus_reader:timeout_2\.Q * 
          loopback_state.Q * /to_pc_ack.Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          \ibus_reader:il_read_stateSBV_2\.Q * \ibus_reader:timeout_0\.Q * 
          \ibus_reader:timeout_1\.Q * \ibus_reader:timeout_2\.Q * 
          /loopback_state.Q * /write_to_bp_ack.Q 
        + /\ibus_reader:il_read_stateSBV_0\.Q * 
          \ibus_reader:il_read_stateSBV_1\.Q * \ibus_reader:timeout_0\.Q * 
          \ibus_reader:timeout_1\.Q * \ibus_reader:timeout_2\.Q * 
          ao_from_pc_strobe 
        + /\ibus_reader:il_read_stateSBV_0\.Q * 
          \ibus_reader:il_read_stateSBV_2\.Q * \ibus_reader:timeout_3\.Q * 
          ao_from_pc_strobe 
        + /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * \ibus_reader:timeout_3\.Q * 
          /ao_from_pc_strobe 
        + \ibus_reader:il_read_stateSBV_0\.Q * \ibus_reader:timeout_3\.Q * 
          loopback_state.Q * /to_pc_ack.Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * \ibus_reader:timeout_3\.Q * 
          /loopback_state.Q * /write_to_bp_ack.Q 
        + \ibus_reader:il_read_stateSBV_1\.Q * 
          \ibus_reader:this_is_a_ctrl_transaction\.Q * 
          \ibus_reader:timeout_3\.Q 
        + \ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * \ibus_reader:timeout_3\.Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * \ibus_reader:timeout_3\.Q 

    \ibus_reader:timeout_3\.C =
          clk 

    \ibus_writer:iu_writeSBV_0\.T =
          /\ibus_writer:iu_writeSBV_0\.Q * \ibus_writer:iu_writeSBV_1\.Q * 
          \ibus_writer:timeout_0\.Q * \ibus_writer:timeout_1\.Q * 
          \ibus_writer:timeout_2\.Q * \ibus_writer:timeout_3\.Q 
        + \ibus_writer:iu_writeSBV_0\.Q * \ibus_writer:timeout_0\.Q * 
          \ibus_writer:timeout_1\.Q * \ibus_writer:timeout_2\.Q * 
          \ibus_writer:timeout_3\.Q * /ao_to_pc_ack 
        + /\ibus_writer:iu_writeSBV_0\.Q * \ibus_writer:iu_writeSBV_1\.Q * 
          /from_pc_req.Q * loopback_state.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * \ibus_writer:iu_writeSBV_1\.Q * 
          /loopback_state.Q * /sensor_to_ibus_req.Q 
        + \ibus_writer:iu_writeSBV_0\.Q * \ibus_writer:iu_writeSBV_1\.Q * 
          /ao_to_pc_ack 

    \ibus_writer:iu_writeSBV_0\.C =
          clk 

    /\ibus_writer:iu_writeSBV_1\.D =
          /\ibus_writer:iu_writeSBV_0\.Q * \ibus_writer:iu_writeSBV_1\.Q * 
          \ibus_writer:timeout_0\.Q * \ibus_writer:timeout_1\.Q * 
          \ibus_writer:timeout_2\.Q * \ibus_writer:timeout_3\.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /from_pc_req.Q * 
          loopback_state.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /loopback_state.Q * 
          /sensor_to_ibus_req.Q 
        + \ibus_writer:iu_writeSBV_0\.Q * /ao_to_pc_ack 

    \ibus_writer:iu_writeSBV_1\.C =
          clk 

    \ibus_writer:timeout_0\.D =
          \ibus_writer:iu_writeSBV_0\.Q * \ibus_writer:timeout_0\.Q * 
          \ibus_writer:timeout_1\.Q * \ibus_writer:timeout_2\.Q * 
          \ibus_writer:timeout_3\.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * \ibus_writer:iu_writeSBV_1\.Q * 
          /\ibus_writer:timeout_0\.Q * from_pc_req.Q * loopback_state.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          \ibus_writer:timeout_0\.Q * /from_pc_req.Q * loopback_state.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * \ibus_writer:iu_writeSBV_1\.Q * 
          /\ibus_writer:timeout_0\.Q * /loopback_state.Q * 
          sensor_to_ibus_req.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          \ibus_writer:timeout_0\.Q * /loopback_state.Q * 
          /sensor_to_ibus_req.Q 
        + \ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          /\ibus_writer:timeout_0\.Q * /ao_to_pc_ack 
        + \ibus_writer:iu_writeSBV_0\.Q * \ibus_writer:timeout_0\.Q * 
          ao_to_pc_ack 
        + \ibus_writer:iu_writeSBV_0\.Q * \ibus_writer:iu_writeSBV_1\.Q * 
          \ibus_writer:timeout_0\.Q 

    \ibus_writer:timeout_0\.C =
          clk 

    \ibus_writer:timeout_1\.T =
          /\ibus_writer:iu_writeSBV_0\.Q * \ibus_writer:iu_writeSBV_1\.Q * 
          \ibus_writer:timeout_0\.Q * from_pc_req.Q * loopback_state.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          \ibus_writer:timeout_1\.Q * from_pc_req.Q * loopback_state.Q 
        + \ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          \ibus_writer:timeout_0\.Q * /\ibus_writer:timeout_1\.Q * 
          /ao_to_pc_ack 
        + \ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          \ibus_writer:timeout_0\.Q * /\ibus_writer:timeout_2\.Q * 
          /ao_to_pc_ack 
        + \ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          \ibus_writer:timeout_0\.Q * /\ibus_writer:timeout_3\.Q * 
          /ao_to_pc_ack 
        + /\ibus_writer:iu_writeSBV_0\.Q * \ibus_writer:iu_writeSBV_1\.Q * 
          \ibus_writer:timeout_1\.Q * /from_pc_req.Q * loopback_state.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * \ibus_writer:iu_writeSBV_1\.Q * 
          \ibus_writer:timeout_0\.Q * /loopback_state.Q * 
          sensor_to_ibus_req.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          \ibus_writer:timeout_1\.Q * /loopback_state.Q * 
          sensor_to_ibus_req.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * \ibus_writer:iu_writeSBV_1\.Q * 
          \ibus_writer:timeout_1\.Q * /loopback_state.Q * 
          /sensor_to_ibus_req.Q 

    \ibus_writer:timeout_1\.C =
          clk 

    \ibus_writer:timeout_2\.T =
          /\ibus_writer:iu_writeSBV_0\.Q * \ibus_writer:iu_writeSBV_1\.Q * 
          \ibus_writer:timeout_0\.Q * \ibus_writer:timeout_1\.Q * 
          from_pc_req.Q * loopback_state.Q 
        + \ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          \ibus_writer:timeout_0\.Q * \ibus_writer:timeout_1\.Q * 
          /\ibus_writer:timeout_2\.Q * /ao_to_pc_ack 
        + \ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          \ibus_writer:timeout_0\.Q * \ibus_writer:timeout_1\.Q * 
          /\ibus_writer:timeout_3\.Q * /ao_to_pc_ack 
        + /\ibus_writer:iu_writeSBV_0\.Q * \ibus_writer:iu_writeSBV_1\.Q * 
          \ibus_writer:timeout_0\.Q * \ibus_writer:timeout_1\.Q * 
          /loopback_state.Q * sensor_to_ibus_req.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          \ibus_writer:timeout_2\.Q * from_pc_req.Q * loopback_state.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * \ibus_writer:iu_writeSBV_1\.Q * 
          \ibus_writer:timeout_2\.Q * /from_pc_req.Q * loopback_state.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          \ibus_writer:timeout_2\.Q * /loopback_state.Q * 
          sensor_to_ibus_req.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * \ibus_writer:iu_writeSBV_1\.Q * 
          \ibus_writer:timeout_2\.Q * /loopback_state.Q * 
          /sensor_to_ibus_req.Q 

    \ibus_writer:timeout_2\.C =
          clk 

    \ibus_writer:timeout_3\.T =
          /\ibus_writer:iu_writeSBV_0\.Q * \ibus_writer:iu_writeSBV_1\.Q * 
          \ibus_writer:timeout_0\.Q * \ibus_writer:timeout_1\.Q * 
          \ibus_writer:timeout_2\.Q * from_pc_req.Q * loopback_state.Q 
        + \ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          \ibus_writer:timeout_0\.Q * \ibus_writer:timeout_1\.Q * 
          \ibus_writer:timeout_2\.Q * /\ibus_writer:timeout_3\.Q * 
          /ao_to_pc_ack 
        + /\ibus_writer:iu_writeSBV_0\.Q * \ibus_writer:iu_writeSBV_1\.Q * 
          \ibus_writer:timeout_0\.Q * \ibus_writer:timeout_1\.Q * 
          \ibus_writer:timeout_2\.Q * /loopback_state.Q * 
          sensor_to_ibus_req.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          \ibus_writer:timeout_3\.Q * from_pc_req.Q * loopback_state.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * \ibus_writer:iu_writeSBV_1\.Q * 
          \ibus_writer:timeout_3\.Q * /from_pc_req.Q * loopback_state.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          \ibus_writer:timeout_3\.Q * /loopback_state.Q * 
          sensor_to_ibus_req.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * \ibus_writer:iu_writeSBV_1\.Q * 
          \ibus_writer:timeout_3\.Q * /loopback_state.Q * 
          /sensor_to_ibus_req.Q 

    \ibus_writer:timeout_3\.C =
          clk 

    /\sp_read:cmp_vv_us_MODGEN_10\ =
          /\sp_read:counter_address_0\.Q * bp_end_address_0.Q 
        + /\sp_read:counter_address_1\.Q * bp_end_address_1.Q 
        + /\sp_read:counter_address_2\.Q * bp_end_address_2.Q 
        + /\sp_read:counter_address_3\.Q * bp_end_address_3.Q 
        + /\sp_read:counter_address_4\.Q * bp_end_address_4.Q 
        + /\sp_read:counter_address_5\.Q * bp_end_address_5.Q 
        + /\sp_read:counter_address_6\.Q * bp_end_address_6.Q 
        + /\sp_read:counter_address_7\.Q * bp_end_address_7.Q 
        + \sp_read:counter_address_0\.Q * /bp_end_address_0.Q 
        + \sp_read:counter_address_1\.Q * /bp_end_address_1.Q 
        + \sp_read:counter_address_2\.Q * /bp_end_address_2.Q 
        + \sp_read:counter_address_3\.Q * /bp_end_address_3.Q 
        + \sp_read:counter_address_4\.Q * /bp_end_address_4.Q 
        + \sp_read:counter_address_5\.Q * /bp_end_address_5.Q 
        + \sp_read:counter_address_6\.Q * /bp_end_address_6.Q 
        + \sp_read:counter_address_7\.Q * /bp_end_address_7.Q 

    \sp_read:counter_address_0\.D =
          S_18.CMB 
        + S_17.CMB 

    \sp_read:counter_address_0\.C =
          clk 

    \sp_read:counter_address_1\.D =
          S_16.CMB 
        + S_15.CMB 

    \sp_read:counter_address_1\.C =
          clk 

    \sp_read:counter_address_2\.D =
          S_14.CMB 
        + S_13.CMB 

    \sp_read:counter_address_2\.C =
          clk 

    \sp_read:counter_address_3\.D =
          S_12.CMB 
        + S_11.CMB 

    \sp_read:counter_address_3\.C =
          clk 

    \sp_read:counter_address_4\.D =
          S_9.CMB 
        + S_10.CMB 

    \sp_read:counter_address_4\.C =
          clk 

    \sp_read:counter_address_5\.D =
          S_8.CMB 
        + S_7.CMB 

    \sp_read:counter_address_5\.C =
          clk 

    \sp_read:counter_address_6\.D =
          S_6.CMB 
        + S_5.CMB 

    \sp_read:counter_address_6\.C =
          clk 

    \sp_read:counter_address_7\.D =
          S_4.CMB 
        + S_3.CMB 

    \sp_read:counter_address_7\.C =
          clk 

    \sp_read:counter_read_stateSBV_0\.D =
          \sp_read:counter_read_stateSBV_1\.Q * 
          \sp_read:counter_read_stateSBV_2\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q * /loopback_state.Q * 
          to_pc_ack.Q 
        + \sp_read:cmp_vv_us_MODGEN_10\.CMB * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          \sp_read:counter_read_stateSBV_2\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q 
        + \sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /loopback_state.Q * 
          to_pc_ack.Q 
        + \sp_read:counter_read_stateSBV_0\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q * /\sp_read:reset_count_0\.Q 
        + \sp_read:counter_read_stateSBV_0\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q * /\sp_read:reset_count_1\.Q 
        + \sp_read:counter_read_stateSBV_0\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q * /\sp_read:reset_count_2\.Q 

    \sp_read:counter_read_stateSBV_0\.C =
          clk 

    \sp_read:counter_read_stateSBV_1\.T =
          \sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * 
          /\sp_read:delay_count_0\.Q * \sp_read:delay_count_1\.Q * 
          \sp_read:delay_count_2\.Q * /\sp_read:delay_count_3\.Q * 
          /\sp_read:delay_count_4\.Q * /\sp_read:delay_count_5\.Q * 
          /\sp_read:delay_count_6\.Q * /\sp_read:delay_count_7\.Q * 
          \sp_read:delay_count_8\.Q * /\sp_read:delay_count_9\.Q 
        + /\sp_read:cmp_vv_us_MODGEN_10\.CMB * 
          \sp_read:counter_address_0\.Q * /\sp_read:counter_address_1\.Q * 
          /\sp_read:counter_address_2\.Q * /\sp_read:counter_address_3\.Q * 
          \sp_read:counter_address_4\.Q * \sp_read:counter_address_5\.Q * 
          \sp_read:counter_address_6\.Q * /\sp_read:counter_address_7\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          \sp_read:counter_read_stateSBV_2\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q 
        + /\sp_read:cmp_vv_us_MODGEN_10\.CMB * 
          \sp_read:counter_address_0\.Q * \sp_read:counter_address_1\.Q * 
          /\sp_read:counter_address_3\.Q * /\sp_read:counter_address_4\.Q * 
          /\sp_read:counter_address_7\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          \sp_read:counter_read_stateSBV_2\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q 
        + /\sp_read:cmp_vv_us_MODGEN_10\.CMB * 
          \sp_read:counter_address_0\.Q * \sp_read:counter_address_1\.Q * 
          /\sp_read:counter_address_3\.Q * /\sp_read:counter_address_5\.Q * 
          /\sp_read:counter_address_7\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          \sp_read:counter_read_stateSBV_2\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q 
        + /\sp_read:cmp_vv_us_MODGEN_10\.CMB * 
          \sp_read:counter_address_0\.Q * \sp_read:counter_address_1\.Q * 
          /\sp_read:counter_address_4\.Q * /\sp_read:counter_address_5\.Q * 
          /\sp_read:counter_address_7\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          \sp_read:counter_read_stateSBV_2\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q 
        + /\sp_read:cmp_vv_us_MODGEN_10\.CMB * 
          \sp_read:counter_address_0\.Q * \sp_read:counter_address_1\.Q * 
          /\sp_read:counter_address_3\.Q * /\sp_read:counter_address_6\.Q * 
          /\sp_read:counter_address_7\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          \sp_read:counter_read_stateSBV_2\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q 
        + /\sp_read:cmp_vv_us_MODGEN_10\.CMB * 
          \sp_read:counter_address_0\.Q * \sp_read:counter_address_1\.Q * 
          /\sp_read:counter_address_4\.Q * /\sp_read:counter_address_6\.Q * 
          /\sp_read:counter_address_7\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          \sp_read:counter_read_stateSBV_2\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q 
        + /\sp_read:counter_address_3\.Q * 
          /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q 
        + /\sp_read:counter_address_4\.Q * 
          /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q 
        + \sp_read:counter_read_stateSBV_1\.Q * 
          \sp_read:counter_read_stateSBV_2\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q * /loopback_state.Q * 
          to_pc_ack.Q 

    \sp_read:counter_read_stateSBV_1\.C =
          clk 

    \sp_read:counter_read_stateSBV_2\.T =
          S_2.CMB 
        + S_1.CMB 

    \sp_read:counter_read_stateSBV_2\.C =
          clk 

    /\sp_read:counter_read_stateSBV_3\.D =
          \sp_read:counter_read_stateSBV_1\.Q * 
          \sp_read:counter_read_stateSBV_2\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q * \sp_read:reset_count_0\.Q * 
          \sp_read:reset_count_1\.Q * \sp_read:reset_count_2\.Q * 
          /loopback_state.Q * to_pc_ack.Q 
        + /\sp_read:cmp_vv_us_MODGEN_10\.CMB * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          \sp_read:counter_read_stateSBV_2\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q * \sp_read:reset_count_0\.Q * 
          \sp_read:reset_count_1\.Q * \sp_read:reset_count_2\.Q 
        + \sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q * \sp_read:reset_count_0\.Q * 
          \sp_read:reset_count_1\.Q * \sp_read:reset_count_2\.Q * 
          sensor_to_bp_read_ack.Q 
        + \sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q * \sp_read:reset_count_0\.Q * 
          \sp_read:reset_count_1\.Q * \sp_read:reset_count_2\.Q 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          \sp_read:counter_read_stateSBV_1\.Q * 
          \sp_read:counter_read_stateSBV_2\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q * /loopback_state.Q * 
          to_pc_ack.Q 
        + /\sp_read:cmp_vv_us_MODGEN_10\.CMB * 
          /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          \sp_read:counter_read_stateSBV_2\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:old_phase\.Q * 
          sinphase_zeros 
        + \sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /loopback_state.Q * 
          sensor_to_bp_read_ack.Q * to_pc_ack.Q 
        + \sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /loopback_state.Q * 
          to_pc_ack.Q 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * /\sp_read:old_phase\.Q * 
          /sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          \sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * sensor_to_bp_read_ack.Q 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          \sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * sensor_to_bp_read_ack.Q 
        + /\sp_read:counter_read_stateSBV_0\.Q * 
          \sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q 

    \sp_read:counter_read_stateSBV_3\.C =
          clk 

    \sp_read:delay_count_0\.D =
          /\sp_read:counter_read_stateSBV_1\.Q * \sp_read:delay_count_0\.Q * 
          /bp_end_address_0.Q * /bp_end_address_1.Q * /bp_end_address_2.Q * 
          /bp_end_address_3.Q * /bp_end_address_4.Q * /bp_end_address_5.Q * 
          /bp_end_address_6.Q * /bp_end_address_7.Q 
        + \sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * 
          /\sp_read:delay_count_0\.Q * \sp_read:delay_count_9\.Q 
        + \sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * 
          /\sp_read:delay_count_0\.Q * \sp_read:delay_count_7\.Q 
        + \sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * 
          /\sp_read:delay_count_0\.Q * \sp_read:delay_count_6\.Q 
        + \sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * 
          /\sp_read:delay_count_0\.Q * \sp_read:delay_count_5\.Q 
        + \sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * 
          /\sp_read:delay_count_0\.Q * \sp_read:delay_count_4\.Q 
        + \sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * 
          /\sp_read:delay_count_0\.Q * \sp_read:delay_count_3\.Q 
        + \sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * 
          /\sp_read:delay_count_0\.Q * /\sp_read:delay_count_1\.Q 
        + \sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * 
          /\sp_read:delay_count_0\.Q * /\sp_read:delay_count_2\.Q 
        + \sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * 
          /\sp_read:delay_count_0\.Q * /\sp_read:delay_count_8\.Q 
        + /\sp_read:counter_read_stateSBV_1\.Q * \sp_read:delay_count_0\.Q * 
          \sp_read:old_phase\.Q * sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_1\.Q * \sp_read:delay_count_0\.Q * 
          /\sp_read:old_phase\.Q * /sinphase_zeros 
        + \sp_read:counter_read_stateSBV_3\.Q * \sp_read:delay_count_0\.Q 
        + \sp_read:counter_read_stateSBV_2\.Q * \sp_read:delay_count_0\.Q 
        + \sp_read:counter_read_stateSBV_0\.Q * \sp_read:delay_count_0\.Q 

    \sp_read:delay_count_0\.C =
          clk 

    \sp_read:delay_count_1\.D =
          /\sp_read:counter_read_stateSBV_1\.Q * \sp_read:delay_count_1\.Q * 
          /bp_end_address_0.Q * /bp_end_address_1.Q * /bp_end_address_2.Q * 
          /bp_end_address_3.Q * /bp_end_address_4.Q * /bp_end_address_5.Q * 
          /bp_end_address_6.Q * /bp_end_address_7.Q 
        + \sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:delay_count_0\.Q * 
          /\sp_read:delay_count_1\.Q 
        + /\sp_read:counter_read_stateSBV_1\.Q * \sp_read:delay_count_1\.Q * 
          \sp_read:old_phase\.Q * sinphase_zeros 
        + \sp_read:counter_read_stateSBV_1\.Q * /\sp_read:delay_count_0\.Q * 
          \sp_read:delay_count_1\.Q * \sp_read:delay_count_9\.Q 
        + \sp_read:counter_read_stateSBV_1\.Q * /\sp_read:delay_count_0\.Q * 
          \sp_read:delay_count_1\.Q * \sp_read:delay_count_7\.Q 
        + \sp_read:counter_read_stateSBV_1\.Q * /\sp_read:delay_count_0\.Q * 
          \sp_read:delay_count_1\.Q * \sp_read:delay_count_6\.Q 
        + \sp_read:counter_read_stateSBV_1\.Q * /\sp_read:delay_count_0\.Q * 
          \sp_read:delay_count_1\.Q * \sp_read:delay_count_5\.Q 
        + \sp_read:counter_read_stateSBV_1\.Q * /\sp_read:delay_count_0\.Q * 
          \sp_read:delay_count_1\.Q * \sp_read:delay_count_4\.Q 
        + \sp_read:counter_read_stateSBV_1\.Q * /\sp_read:delay_count_0\.Q * 
          \sp_read:delay_count_1\.Q * \sp_read:delay_count_3\.Q 
        + \sp_read:counter_read_stateSBV_1\.Q * /\sp_read:delay_count_0\.Q * 
          \sp_read:delay_count_1\.Q * /\sp_read:delay_count_2\.Q 
        + \sp_read:counter_read_stateSBV_1\.Q * /\sp_read:delay_count_0\.Q * 
          \sp_read:delay_count_1\.Q * /\sp_read:delay_count_8\.Q 
        + /\sp_read:counter_read_stateSBV_1\.Q * \sp_read:delay_count_1\.Q * 
          /\sp_read:old_phase\.Q * /sinphase_zeros 
        + \sp_read:counter_read_stateSBV_3\.Q * \sp_read:delay_count_1\.Q 
        + \sp_read:counter_read_stateSBV_2\.Q * \sp_read:delay_count_1\.Q 
        + \sp_read:counter_read_stateSBV_0\.Q * \sp_read:delay_count_1\.Q 

    \sp_read:delay_count_1\.C =
          clk 

    \sp_read:delay_count_2\.D =
          /\sp_read:counter_read_stateSBV_1\.Q * \sp_read:delay_count_2\.Q * 
          /bp_end_address_0.Q * /bp_end_address_1.Q * /bp_end_address_2.Q * 
          /bp_end_address_3.Q * /bp_end_address_4.Q * /bp_end_address_5.Q * 
          /bp_end_address_6.Q * /bp_end_address_7.Q 
        + \sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:delay_count_0\.Q * 
          \sp_read:delay_count_1\.Q * /\sp_read:delay_count_2\.Q 
        + /\sp_read:counter_read_stateSBV_1\.Q * \sp_read:delay_count_2\.Q * 
          \sp_read:old_phase\.Q * sinphase_zeros 
        + \sp_read:counter_read_stateSBV_1\.Q * /\sp_read:delay_count_0\.Q * 
          \sp_read:delay_count_2\.Q * \sp_read:delay_count_9\.Q 
        + \sp_read:counter_read_stateSBV_1\.Q * /\sp_read:delay_count_0\.Q * 
          \sp_read:delay_count_2\.Q * \sp_read:delay_count_7\.Q 
        + \sp_read:counter_read_stateSBV_1\.Q * /\sp_read:delay_count_0\.Q * 
          \sp_read:delay_count_2\.Q * \sp_read:delay_count_6\.Q 
        + \sp_read:counter_read_stateSBV_1\.Q * /\sp_read:delay_count_0\.Q * 
          \sp_read:delay_count_2\.Q * \sp_read:delay_count_5\.Q 
        + \sp_read:counter_read_stateSBV_1\.Q * /\sp_read:delay_count_0\.Q * 
          \sp_read:delay_count_2\.Q * \sp_read:delay_count_4\.Q 
        + \sp_read:counter_read_stateSBV_1\.Q * /\sp_read:delay_count_0\.Q * 
          \sp_read:delay_count_2\.Q * \sp_read:delay_count_3\.Q 
        + \sp_read:counter_read_stateSBV_1\.Q * /\sp_read:delay_count_0\.Q * 
          \sp_read:delay_count_2\.Q * /\sp_read:delay_count_8\.Q 
        + /\sp_read:counter_read_stateSBV_1\.Q * \sp_read:delay_count_2\.Q * 
          /\sp_read:old_phase\.Q * /sinphase_zeros 
        + \sp_read:counter_read_stateSBV_1\.Q * /\sp_read:delay_count_1\.Q * 
          \sp_read:delay_count_2\.Q 
        + \sp_read:counter_read_stateSBV_3\.Q * \sp_read:delay_count_2\.Q 
        + \sp_read:counter_read_stateSBV_2\.Q * \sp_read:delay_count_2\.Q 
        + \sp_read:counter_read_stateSBV_0\.Q * \sp_read:delay_count_2\.Q 

    \sp_read:delay_count_2\.C =
          clk 

    \sp_read:delay_count_3\.D =
          /\sp_read:counter_read_stateSBV_1\.Q * \sp_read:delay_count_3\.Q * 
          /bp_end_address_0.Q * /bp_end_address_1.Q * /bp_end_address_2.Q * 
          /bp_end_address_3.Q * /bp_end_address_4.Q * /bp_end_address_5.Q * 
          /bp_end_address_6.Q * /bp_end_address_7.Q 
        + \sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:delay_count_0\.Q * 
          \sp_read:delay_count_1\.Q * \sp_read:delay_count_2\.Q * 
          /\sp_read:delay_count_3\.Q 
        + /\sp_read:counter_read_stateSBV_1\.Q * \sp_read:delay_count_3\.Q * 
          \sp_read:old_phase\.Q * sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_1\.Q * \sp_read:delay_count_3\.Q * 
          /\sp_read:old_phase\.Q * /sinphase_zeros 
        + \sp_read:counter_read_stateSBV_1\.Q * /\sp_read:delay_count_0\.Q * 
          \sp_read:delay_count_3\.Q 
        + \sp_read:counter_read_stateSBV_1\.Q * /\sp_read:delay_count_1\.Q * 
          \sp_read:delay_count_3\.Q 
        + \sp_read:counter_read_stateSBV_1\.Q * /\sp_read:delay_count_2\.Q * 
          \sp_read:delay_count_3\.Q 
        + \sp_read:counter_read_stateSBV_3\.Q * \sp_read:delay_count_3\.Q 
        + \sp_read:counter_read_stateSBV_2\.Q * \sp_read:delay_count_3\.Q 
        + \sp_read:counter_read_stateSBV_0\.Q * \sp_read:delay_count_3\.Q 

    \sp_read:delay_count_3\.C =
          clk 

    \sp_read:delay_count_4\.D =
          /\sp_read:counter_read_stateSBV_1\.Q * \sp_read:delay_count_4\.Q * 
          /bp_end_address_0.Q * /bp_end_address_1.Q * /bp_end_address_2.Q * 
          /bp_end_address_3.Q * /bp_end_address_4.Q * /bp_end_address_5.Q * 
          /bp_end_address_6.Q * /bp_end_address_7.Q 
        + \sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:delay_count_0\.Q * 
          \sp_read:delay_count_1\.Q * \sp_read:delay_count_2\.Q * 
          \sp_read:delay_count_3\.Q * /\sp_read:delay_count_4\.Q 
        + /\sp_read:counter_read_stateSBV_1\.Q * \sp_read:delay_count_4\.Q * 
          \sp_read:old_phase\.Q * sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_1\.Q * \sp_read:delay_count_4\.Q * 
          /\sp_read:old_phase\.Q * /sinphase_zeros 
        + \sp_read:counter_read_stateSBV_1\.Q * /\sp_read:delay_count_0\.Q * 
          \sp_read:delay_count_4\.Q 
        + \sp_read:counter_read_stateSBV_1\.Q * /\sp_read:delay_count_1\.Q * 
          \sp_read:delay_count_4\.Q 
        + \sp_read:counter_read_stateSBV_1\.Q * /\sp_read:delay_count_2\.Q * 
          \sp_read:delay_count_4\.Q 
        + \sp_read:counter_read_stateSBV_1\.Q * /\sp_read:delay_count_3\.Q * 
          \sp_read:delay_count_4\.Q 
        + \sp_read:counter_read_stateSBV_3\.Q * \sp_read:delay_count_4\.Q 
        + \sp_read:counter_read_stateSBV_2\.Q * \sp_read:delay_count_4\.Q 
        + \sp_read:counter_read_stateSBV_0\.Q * \sp_read:delay_count_4\.Q 

    \sp_read:delay_count_4\.C =
          clk 

    \sp_read:delay_count_5\.D =
          /\sp_read:counter_read_stateSBV_1\.Q * \sp_read:delay_count_5\.Q * 
          /bp_end_address_0.Q * /bp_end_address_1.Q * /bp_end_address_2.Q * 
          /bp_end_address_3.Q * /bp_end_address_4.Q * /bp_end_address_5.Q * 
          /bp_end_address_6.Q * /bp_end_address_7.Q 
        + \sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:delay_count_0\.Q * 
          \sp_read:delay_count_1\.Q * \sp_read:delay_count_2\.Q * 
          \sp_read:delay_count_3\.Q * \sp_read:delay_count_4\.Q * 
          /\sp_read:delay_count_5\.Q 
        + /\sp_read:counter_read_stateSBV_1\.Q * \sp_read:delay_count_5\.Q * 
          \sp_read:old_phase\.Q * sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_1\.Q * \sp_read:delay_count_5\.Q * 
          /\sp_read:old_phase\.Q * /sinphase_zeros 
        + \sp_read:counter_read_stateSBV_1\.Q * /\sp_read:delay_count_0\.Q * 
          \sp_read:delay_count_5\.Q 
        + \sp_read:counter_read_stateSBV_1\.Q * /\sp_read:delay_count_1\.Q * 
          \sp_read:delay_count_5\.Q 
        + \sp_read:counter_read_stateSBV_1\.Q * /\sp_read:delay_count_2\.Q * 
          \sp_read:delay_count_5\.Q 
        + \sp_read:counter_read_stateSBV_1\.Q * /\sp_read:delay_count_3\.Q * 
          \sp_read:delay_count_5\.Q 
        + \sp_read:counter_read_stateSBV_1\.Q * /\sp_read:delay_count_4\.Q * 
          \sp_read:delay_count_5\.Q 
        + \sp_read:counter_read_stateSBV_3\.Q * \sp_read:delay_count_5\.Q 
        + \sp_read:counter_read_stateSBV_2\.Q * \sp_read:delay_count_5\.Q 
        + \sp_read:counter_read_stateSBV_0\.Q * \sp_read:delay_count_5\.Q 

    \sp_read:delay_count_5\.C =
          clk 

    \sp_read:delay_count_6\.D =
          \sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:delay_count_0\.Q * 
          \sp_read:delay_count_1\.Q * \sp_read:delay_count_2\.Q * 
          \sp_read:delay_count_3\.Q * \sp_read:delay_count_4\.Q * 
          \sp_read:delay_count_5\.Q * /\sp_read:delay_count_6\.Q 
        + /\sp_read:counter_read_stateSBV_1\.Q * \sp_read:delay_count_6\.Q * 
          /bp_end_address_0.Q * /bp_end_address_1.Q * /bp_end_address_2.Q * 
          /bp_end_address_3.Q * /bp_end_address_4.Q * /bp_end_address_5.Q * 
          /bp_end_address_6.Q * /bp_end_address_7.Q 
        + /\sp_read:counter_read_stateSBV_1\.Q * \sp_read:delay_count_6\.Q * 
          \sp_read:old_phase\.Q * sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_1\.Q * \sp_read:delay_count_6\.Q * 
          /\sp_read:old_phase\.Q * /sinphase_zeros 
        + \sp_read:counter_read_stateSBV_1\.Q * /\sp_read:delay_count_0\.Q * 
          \sp_read:delay_count_6\.Q 
        + \sp_read:counter_read_stateSBV_1\.Q * /\sp_read:delay_count_1\.Q * 
          \sp_read:delay_count_6\.Q 
        + \sp_read:counter_read_stateSBV_1\.Q * /\sp_read:delay_count_2\.Q * 
          \sp_read:delay_count_6\.Q 
        + \sp_read:counter_read_stateSBV_1\.Q * /\sp_read:delay_count_3\.Q * 
          \sp_read:delay_count_6\.Q 
        + \sp_read:counter_read_stateSBV_1\.Q * /\sp_read:delay_count_4\.Q * 
          \sp_read:delay_count_6\.Q 
        + \sp_read:counter_read_stateSBV_1\.Q * /\sp_read:delay_count_5\.Q * 
          \sp_read:delay_count_6\.Q 
        + \sp_read:counter_read_stateSBV_3\.Q * \sp_read:delay_count_6\.Q 
        + \sp_read:counter_read_stateSBV_2\.Q * \sp_read:delay_count_6\.Q 
        + \sp_read:counter_read_stateSBV_0\.Q * \sp_read:delay_count_6\.Q 

    \sp_read:delay_count_6\.C =
          clk 

    \sp_read:delay_count_7\.D =
          \sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:delay_count_0\.Q * 
          \sp_read:delay_count_1\.Q * \sp_read:delay_count_2\.Q * 
          \sp_read:delay_count_3\.Q * \sp_read:delay_count_4\.Q * 
          \sp_read:delay_count_5\.Q * \sp_read:delay_count_6\.Q * 
          /\sp_read:delay_count_7\.Q 
        + /\sp_read:counter_read_stateSBV_1\.Q * \sp_read:delay_count_7\.Q * 
          /bp_end_address_0.Q * /bp_end_address_1.Q * /bp_end_address_2.Q * 
          /bp_end_address_3.Q * /bp_end_address_4.Q * /bp_end_address_5.Q * 
          /bp_end_address_6.Q * /bp_end_address_7.Q 
        + /\sp_read:counter_read_stateSBV_1\.Q * \sp_read:delay_count_7\.Q * 
          \sp_read:old_phase\.Q * sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_1\.Q * \sp_read:delay_count_7\.Q * 
          /\sp_read:old_phase\.Q * /sinphase_zeros 
        + \sp_read:counter_read_stateSBV_1\.Q * /\sp_read:delay_count_0\.Q * 
          \sp_read:delay_count_7\.Q 
        + \sp_read:counter_read_stateSBV_1\.Q * /\sp_read:delay_count_1\.Q * 
          \sp_read:delay_count_7\.Q 
        + \sp_read:counter_read_stateSBV_1\.Q * /\sp_read:delay_count_2\.Q * 
          \sp_read:delay_count_7\.Q 
        + \sp_read:counter_read_stateSBV_1\.Q * /\sp_read:delay_count_3\.Q * 
          \sp_read:delay_count_7\.Q 
        + \sp_read:counter_read_stateSBV_1\.Q * /\sp_read:delay_count_4\.Q * 
          \sp_read:delay_count_7\.Q 
        + \sp_read:counter_read_stateSBV_1\.Q * /\sp_read:delay_count_5\.Q * 
          \sp_read:delay_count_7\.Q 
        + \sp_read:counter_read_stateSBV_1\.Q * /\sp_read:delay_count_6\.Q * 
          \sp_read:delay_count_7\.Q 
        + \sp_read:counter_read_stateSBV_3\.Q * \sp_read:delay_count_7\.Q 
        + \sp_read:counter_read_stateSBV_2\.Q * \sp_read:delay_count_7\.Q 
        + \sp_read:counter_read_stateSBV_0\.Q * \sp_read:delay_count_7\.Q 

    \sp_read:delay_count_7\.C =
          clk 

    \sp_read:delay_count_8\.D =
          \sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:delay_count_0\.Q * 
          \sp_read:delay_count_1\.Q * \sp_read:delay_count_2\.Q * 
          \sp_read:delay_count_3\.Q * \sp_read:delay_count_4\.Q * 
          \sp_read:delay_count_5\.Q * \sp_read:delay_count_6\.Q * 
          \sp_read:delay_count_7\.Q * /\sp_read:delay_count_8\.Q 
        + /\sp_read:counter_read_stateSBV_1\.Q * \sp_read:delay_count_8\.Q * 
          /bp_end_address_0.Q * /bp_end_address_1.Q * /bp_end_address_2.Q * 
          /bp_end_address_3.Q * /bp_end_address_4.Q * /bp_end_address_5.Q * 
          /bp_end_address_6.Q * /bp_end_address_7.Q 
        + /\sp_read:counter_read_stateSBV_1\.Q * \sp_read:delay_count_8\.Q * 
          \sp_read:old_phase\.Q * sinphase_zeros 
        + \sp_read:counter_read_stateSBV_1\.Q * /\sp_read:delay_count_0\.Q * 
          \sp_read:delay_count_8\.Q * \sp_read:delay_count_9\.Q 
        + \sp_read:counter_read_stateSBV_1\.Q * /\sp_read:delay_count_0\.Q * 
          \sp_read:delay_count_5\.Q * \sp_read:delay_count_8\.Q 
        + \sp_read:counter_read_stateSBV_1\.Q * /\sp_read:delay_count_3\.Q * 
          \sp_read:delay_count_4\.Q * \sp_read:delay_count_8\.Q 
        + \sp_read:counter_read_stateSBV_1\.Q * /\sp_read:delay_count_4\.Q * 
          \sp_read:delay_count_6\.Q * \sp_read:delay_count_8\.Q 
        + \sp_read:counter_read_stateSBV_1\.Q * /\sp_read:delay_count_5\.Q * 
          \sp_read:delay_count_7\.Q * \sp_read:delay_count_8\.Q 
        + \sp_read:counter_read_stateSBV_1\.Q * \sp_read:delay_count_0\.Q * 
          /\sp_read:delay_count_6\.Q * \sp_read:delay_count_8\.Q 
        + \sp_read:counter_read_stateSBV_1\.Q * \sp_read:delay_count_3\.Q * 
          /\sp_read:delay_count_7\.Q * \sp_read:delay_count_8\.Q 
        + /\sp_read:counter_read_stateSBV_1\.Q * \sp_read:delay_count_8\.Q * 
          /\sp_read:old_phase\.Q * /sinphase_zeros 
        + \sp_read:counter_read_stateSBV_1\.Q * /\sp_read:delay_count_1\.Q * 
          \sp_read:delay_count_8\.Q 
        + \sp_read:counter_read_stateSBV_1\.Q * /\sp_read:delay_count_2\.Q * 
          \sp_read:delay_count_8\.Q 
        + \sp_read:counter_read_stateSBV_3\.Q * \sp_read:delay_count_8\.Q 
        + \sp_read:counter_read_stateSBV_2\.Q * \sp_read:delay_count_8\.Q 
        + \sp_read:counter_read_stateSBV_0\.Q * \sp_read:delay_count_8\.Q 

    \sp_read:delay_count_8\.C =
          clk 

    \sp_read:delay_count_9\.D =
          \sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q * \sp_read:delay_count_0\.Q * 
          \sp_read:delay_count_1\.Q * \sp_read:delay_count_2\.Q * 
          \sp_read:delay_count_3\.Q * \sp_read:delay_count_4\.Q * 
          \sp_read:delay_count_5\.Q * \sp_read:delay_count_6\.Q * 
          \sp_read:delay_count_7\.Q * \sp_read:delay_count_8\.Q * 
          /\sp_read:delay_count_9\.Q 
        + /\sp_read:counter_read_stateSBV_1\.Q * \sp_read:delay_count_9\.Q * 
          /bp_end_address_0.Q * /bp_end_address_1.Q * /bp_end_address_2.Q * 
          /bp_end_address_3.Q * /bp_end_address_4.Q * /bp_end_address_5.Q * 
          /bp_end_address_6.Q * /bp_end_address_7.Q 
        + /\sp_read:counter_read_stateSBV_1\.Q * \sp_read:delay_count_9\.Q * 
          \sp_read:old_phase\.Q * sinphase_zeros 
        + /\sp_read:counter_read_stateSBV_1\.Q * \sp_read:delay_count_9\.Q * 
          /\sp_read:old_phase\.Q * /sinphase_zeros 
        + \sp_read:counter_read_stateSBV_1\.Q * /\sp_read:delay_count_0\.Q * 
          \sp_read:delay_count_9\.Q 
        + \sp_read:counter_read_stateSBV_1\.Q * /\sp_read:delay_count_1\.Q * 
          \sp_read:delay_count_9\.Q 
        + \sp_read:counter_read_stateSBV_1\.Q * /\sp_read:delay_count_2\.Q * 
          \sp_read:delay_count_9\.Q 
        + \sp_read:counter_read_stateSBV_1\.Q * /\sp_read:delay_count_3\.Q * 
          \sp_read:delay_count_9\.Q 
        + \sp_read:counter_read_stateSBV_1\.Q * /\sp_read:delay_count_4\.Q * 
          \sp_read:delay_count_9\.Q 
        + \sp_read:counter_read_stateSBV_1\.Q * /\sp_read:delay_count_5\.Q * 
          \sp_read:delay_count_9\.Q 
        + \sp_read:counter_read_stateSBV_1\.Q * /\sp_read:delay_count_6\.Q * 
          \sp_read:delay_count_9\.Q 
        + \sp_read:counter_read_stateSBV_1\.Q * /\sp_read:delay_count_7\.Q * 
          \sp_read:delay_count_9\.Q 
        + \sp_read:counter_read_stateSBV_1\.Q * /\sp_read:delay_count_8\.Q * 
          \sp_read:delay_count_9\.Q 
        + \sp_read:counter_read_stateSBV_3\.Q * \sp_read:delay_count_9\.Q 
        + \sp_read:counter_read_stateSBV_2\.Q * \sp_read:delay_count_9\.Q 
        + \sp_read:counter_read_stateSBV_0\.Q * \sp_read:delay_count_9\.Q 

    \sp_read:delay_count_9\.C =
          clk 

    \sp_read:old_phase\.D =
          sinphase_zeros 

    \sp_read:old_phase\.AP =
          fast * sinphase_zeros * /slow 

    \sp_read:old_phase\.AR =
          fast * /sinphase_zeros * /slow 

    \sp_read:old_phase\.C =
          clk 

    \sp_read:reset_count_0\.D =
          \sp_read:counter_read_stateSBV_0\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q * /\sp_read:reset_count_0\.Q 

    \sp_read:reset_count_0\.C =
          clk 

    \sp_read:reset_count_1\.D =
          \sp_read:counter_read_stateSBV_0\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q * /\sp_read:reset_count_0\.Q * 
          \sp_read:reset_count_1\.Q 
        + \sp_read:counter_read_stateSBV_0\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q * \sp_read:reset_count_0\.Q * 
          /\sp_read:reset_count_1\.Q 

    \sp_read:reset_count_1\.C =
          clk 

    \sp_read:reset_count_2\.D =
          \sp_read:counter_read_stateSBV_0\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q * \sp_read:reset_count_0\.Q * 
          \sp_read:reset_count_1\.Q * /\sp_read:reset_count_2\.Q 
        + \sp_read:counter_read_stateSBV_0\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q * /\sp_read:reset_count_0\.Q * 
          \sp_read:reset_count_2\.Q 
        + \sp_read:counter_read_stateSBV_0\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q * /\sp_read:reset_count_1\.Q * 
          \sp_read:reset_count_2\.Q 

    \sp_read:reset_count_2\.C =
          clk 

    address_from_pc_0.T =
          /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          \ibus_reader:il_read_stateSBV_2\.Q * /address_from_pc_0.Q * 
          /bpctrl(10).Q * bpctrl(11).Q * /bpctrl(7).Q * /bpctrl(8).Q * 
          bpd(10).Q * data_from_pc_15.Q 
        + /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          \ibus_reader:il_read_stateSBV_2\.Q * address_from_pc_0.Q * 
          /bpctrl(10).Q * bpctrl(11).Q * /bpctrl(7).Q * /bpctrl(8).Q * 
          /bpd(10).Q * data_from_pc_15.Q 

    address_from_pc_0.C =
          clk 

    address_from_pc_1.T =
          /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          \ibus_reader:il_read_stateSBV_2\.Q * /address_from_pc_1.Q * 
          /bpctrl(10).Q * bpctrl(11).Q * /bpctrl(7).Q * /bpctrl(8).Q * 
          bpd(11).Q * data_from_pc_15.Q 
        + /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          \ibus_reader:il_read_stateSBV_2\.Q * address_from_pc_1.Q * 
          /bpctrl(10).Q * bpctrl(11).Q * /bpctrl(7).Q * /bpctrl(8).Q * 
          /bpd(11).Q * data_from_pc_15.Q 

    address_from_pc_1.C =
          clk 

    address_from_pc_2.T =
          /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          \ibus_reader:il_read_stateSBV_2\.Q * /address_from_pc_2.Q * 
          /bpctrl(10).Q * bpctrl(11).Q * /bpctrl(7).Q * /bpctrl(8).Q * 
          bpd(12).Q * data_from_pc_15.Q 
        + /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          \ibus_reader:il_read_stateSBV_2\.Q * address_from_pc_2.Q * 
          /bpctrl(10).Q * bpctrl(11).Q * /bpctrl(7).Q * /bpctrl(8).Q * 
          /bpd(12).Q * data_from_pc_15.Q 

    address_from_pc_2.C =
          clk 

    address_from_pc_3.T =
          /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          \ibus_reader:il_read_stateSBV_2\.Q * /address_from_pc_3.Q * 
          /bpctrl(10).Q * bpctrl(11).Q * /bpctrl(7).Q * /bpctrl(8).Q * 
          bpd(13).Q * data_from_pc_15.Q 
        + /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          \ibus_reader:il_read_stateSBV_2\.Q * address_from_pc_3.Q * 
          /bpctrl(10).Q * bpctrl(11).Q * /bpctrl(7).Q * /bpctrl(8).Q * 
          /bpd(13).Q * data_from_pc_15.Q 

    address_from_pc_3.C =
          clk 

    address_from_pc_4.T =
          /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          \ibus_reader:il_read_stateSBV_2\.Q * /address_from_pc_4.Q * 
          /bpctrl(10).Q * bpctrl(11).Q * /bpctrl(7).Q * /bpctrl(8).Q * 
          bpd(14).Q * data_from_pc_15.Q 
        + /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          \ibus_reader:il_read_stateSBV_2\.Q * address_from_pc_4.Q * 
          /bpctrl(10).Q * bpctrl(11).Q * /bpctrl(7).Q * /bpctrl(8).Q * 
          /bpd(14).Q * data_from_pc_15.Q 

    address_from_pc_4.C =
          clk 

    address_from_pc_5.T =
          /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          \ibus_reader:il_read_stateSBV_2\.Q * /address_from_pc_5.Q * 
          /bpctrl(10).Q * bpctrl(11).Q * /bpctrl(7).Q * /bpctrl(8).Q * 
          bpd(15).Q * data_from_pc_15.Q 
        + /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          \ibus_reader:il_read_stateSBV_2\.Q * address_from_pc_5.Q * 
          /bpctrl(10).Q * bpctrl(11).Q * /bpctrl(7).Q * /bpctrl(8).Q * 
          /bpd(15).Q * data_from_pc_15.Q 

    address_from_pc_5.C =
          clk 

    address_from_pc_6.T =
          /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          \ibus_reader:il_read_stateSBV_2\.Q * /address_from_pc_6.Q * 
          /bpctrl(10).Q * bpctrl(11).Q * bpctrl(4).Q * /bpctrl(7).Q * 
          /bpctrl(8).Q * data_from_pc_15.Q 
        + /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          \ibus_reader:il_read_stateSBV_2\.Q * address_from_pc_6.Q * 
          /bpctrl(10).Q * bpctrl(11).Q * /bpctrl(4).Q * /bpctrl(7).Q * 
          /bpctrl(8).Q * data_from_pc_15.Q 

    address_from_pc_6.C =
          clk 

    address_from_pc_7.T =
          /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          \ibus_reader:il_read_stateSBV_2\.Q * /address_from_pc_7.Q * 
          /bpctrl(10).Q * bpctrl(11).Q * bpctrl(5).Q * /bpctrl(7).Q * 
          /bpctrl(8).Q * data_from_pc_15.Q 
        + /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          \ibus_reader:il_read_stateSBV_2\.Q * address_from_pc_7.Q * 
          /bpctrl(10).Q * bpctrl(11).Q * /bpctrl(5).Q * /bpctrl(7).Q * 
          /bpctrl(8).Q * data_from_pc_15.Q 

    address_from_pc_7.C =
          clk 

    ao_from_pc_ack.D =
          /\ibus_reader:il_read_stateSBV_0\.Q * 
          \ibus_reader:il_read_stateSBV_1\.Q 

    ao_from_pc_ack.C =
          clk 

    ao_from_pc_ack.OE =
          /il_tristate.Q 

    ao_to_pc_strobe.D =
          \ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          /ao_to_pc_ack 
        + /\ibus_writer:iu_writeSBV_0\.Q * \ibus_writer:iu_writeSBV_1\.Q 

    ao_to_pc_strobe.C =
          clk 

    /bp_end_address_0.T =
          \ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * address_from_pc_0.Q * 
          /address_from_pc_1.Q * /bp_end_address_0.Q * bpctrl(6).Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * address_from_pc_0.Q * 
          /address_from_pc_1.Q * bp_end_address_0.Q * /bpctrl(6).Q 

    bp_end_address_0.AP =
          GND

    bp_end_address_0.AR =
          reset.CMB 

    bp_end_address_0.C =
          clk 

    /bp_end_address_1.T =
          \ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * address_from_pc_0.Q * 
          /address_from_pc_1.Q * /bp_end_address_1.Q * bpctrl(7).Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * address_from_pc_0.Q * 
          /address_from_pc_1.Q * bp_end_address_1.Q * /bpctrl(7).Q 

    bp_end_address_1.AP =
          GND

    bp_end_address_1.AR =
          reset.CMB 

    bp_end_address_1.C =
          clk 

    /bp_end_address_2.T =
          \ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * address_from_pc_0.Q * 
          /address_from_pc_1.Q * /bp_end_address_2.Q * bpctrl(8).Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * address_from_pc_0.Q * 
          /address_from_pc_1.Q * bp_end_address_2.Q * /bpctrl(8).Q 

    bp_end_address_2.AP =
          GND

    bp_end_address_2.AR =
          reset.CMB 

    bp_end_address_2.C =
          clk 

    /bp_end_address_3.T =
          \ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * address_from_pc_0.Q * 
          /address_from_pc_1.Q * /bp_end_address_3.Q * bpctrl(10).Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * address_from_pc_0.Q * 
          /address_from_pc_1.Q * bp_end_address_3.Q * /bpctrl(10).Q 

    bp_end_address_3.AP =
          GND

    bp_end_address_3.AR =
          reset.CMB 

    bp_end_address_3.C =
          clk 

    /bp_end_address_4.T =
          \ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * address_from_pc_0.Q * 
          /address_from_pc_1.Q * /bp_end_address_4.Q * bpctrl(11).Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * address_from_pc_0.Q * 
          /address_from_pc_1.Q * bp_end_address_4.Q * /bpctrl(11).Q 

    bp_end_address_4.AP =
          GND

    bp_end_address_4.AR =
          reset.CMB 

    bp_end_address_4.C =
          clk 

    /bp_end_address_5.T =
          \ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * address_from_pc_0.Q * 
          /address_from_pc_1.Q * /bp_end_address_5.Q * data_from_pc_13.Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * address_from_pc_0.Q * 
          /address_from_pc_1.Q * bp_end_address_5.Q * /data_from_pc_13.Q 

    bp_end_address_5.AP =
          GND

    bp_end_address_5.AR =
          reset.CMB 

    bp_end_address_5.C =
          clk 

    /bp_end_address_6.T =
          \ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * address_from_pc_0.Q * 
          /address_from_pc_1.Q * /bp_end_address_6.Q * data_from_pc_14.Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * address_from_pc_0.Q * 
          /address_from_pc_1.Q * bp_end_address_6.Q * /data_from_pc_14.Q 

    bp_end_address_6.AP =
          GND

    bp_end_address_6.AR =
          reset.CMB 

    bp_end_address_6.C =
          clk 

    /bp_end_address_7.T =
          \ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * address_from_pc_0.Q * 
          /address_from_pc_1.Q * /bp_end_address_7.Q * data_from_pc_15.Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * address_from_pc_0.Q * 
          /address_from_pc_1.Q * bp_end_address_7.Q * /data_from_pc_15.Q 

    bp_end_address_7.AP =
          GND

    bp_end_address_7.AR =
          reset.CMB 

    bp_end_address_7.C =
          clk 

    /bp_start_address_0.T =
          \ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * address_from_pc_0.Q * 
          /address_from_pc_1.Q * /bp_start_address_0.Q * bpd(10).Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * address_from_pc_0.Q * 
          /address_from_pc_1.Q * bp_start_address_0.Q * /bpd(10).Q 

    bp_start_address_0.AP =
          GND

    bp_start_address_0.AR =
          reset.CMB 

    bp_start_address_0.C =
          clk 

    /bp_start_address_1.T =
          \ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * address_from_pc_0.Q * 
          /address_from_pc_1.Q * /bp_start_address_1.Q * bpd(11).Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * address_from_pc_0.Q * 
          /address_from_pc_1.Q * bp_start_address_1.Q * /bpd(11).Q 

    bp_start_address_1.AP =
          GND

    bp_start_address_1.AR =
          reset.CMB 

    bp_start_address_1.C =
          clk 

    /bp_start_address_2.T =
          \ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * address_from_pc_0.Q * 
          /address_from_pc_1.Q * /bp_start_address_2.Q * bpd(12).Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * address_from_pc_0.Q * 
          /address_from_pc_1.Q * bp_start_address_2.Q * /bpd(12).Q 

    bp_start_address_2.AP =
          GND

    bp_start_address_2.AR =
          reset.CMB 

    bp_start_address_2.C =
          clk 

    /bp_start_address_3.T =
          \ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * address_from_pc_0.Q * 
          /address_from_pc_1.Q * /bp_start_address_3.Q * bpd(13).Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * address_from_pc_0.Q * 
          /address_from_pc_1.Q * bp_start_address_3.Q * /bpd(13).Q 

    bp_start_address_3.AP =
          GND

    bp_start_address_3.AR =
          reset.CMB 

    bp_start_address_3.C =
          clk 

    /bp_start_address_4.T =
          \ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * address_from_pc_0.Q * 
          /address_from_pc_1.Q * /bp_start_address_4.Q * bpd(14).Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * address_from_pc_0.Q * 
          /address_from_pc_1.Q * bp_start_address_4.Q * /bpd(14).Q 

    bp_start_address_4.AP =
          GND

    bp_start_address_4.AR =
          reset.CMB 

    bp_start_address_4.C =
          clk 

    /bp_start_address_5.T =
          \ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * address_from_pc_0.Q * 
          /address_from_pc_1.Q * /bp_start_address_5.Q * bpd(15).Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * address_from_pc_0.Q * 
          /address_from_pc_1.Q * bp_start_address_5.Q * /bpd(15).Q 

    bp_start_address_5.AP =
          GND

    bp_start_address_5.AR =
          reset.CMB 

    bp_start_address_5.C =
          clk 

    /bp_start_address_6.T =
          \ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * address_from_pc_0.Q * 
          /address_from_pc_1.Q * /bp_start_address_6.Q * bpctrl(4).Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * address_from_pc_0.Q * 
          /address_from_pc_1.Q * bp_start_address_6.Q * /bpctrl(4).Q 

    bp_start_address_6.AP =
          GND

    bp_start_address_6.AR =
          reset.CMB 

    bp_start_address_6.C =
          clk 

    /bp_start_address_7.T =
          \ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * address_from_pc_0.Q * 
          /address_from_pc_1.Q * /bp_start_address_7.Q * bpctrl(5).Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * address_from_pc_0.Q * 
          /address_from_pc_1.Q * bp_start_address_7.Q * /bpctrl(5).Q 

    bp_start_address_7.AP =
          GND

    bp_start_address_7.AR =
          reset.CMB 

    bp_start_address_7.C =
          clk 

    bpaddr(0).T =
          /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /bpaddr(0).Q * 
          loopback_state.Q * sensor_address_0.Q * sensor_to_bp_read_req.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /bpaddr(0).Q * /from_pc_req.Q * 
          sensor_address_0.Q * sensor_to_bp_read_req.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /address_from_pc_0.Q * 
          bpaddr(0).Q * from_pc_req.Q * /loopback_state.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * address_from_pc_0.Q * 
          /bpaddr(0).Q * from_pc_req.Q * /loopback_state.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * bpaddr(0).Q * loopback_state.Q * 
          /sensor_address_0.Q * sensor_to_bp_read_req.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * bpaddr(0).Q * /from_pc_req.Q * 
          /sensor_address_0.Q * sensor_to_bp_read_req.Q 

    bpaddr(0).C =
          clk 

    bpaddr(1).T =
          /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /bpaddr(1).Q * 
          loopback_state.Q * sensor_address_1.Q * sensor_to_bp_read_req.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /bpaddr(1).Q * /from_pc_req.Q * 
          sensor_address_1.Q * sensor_to_bp_read_req.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /address_from_pc_1.Q * 
          bpaddr(1).Q * from_pc_req.Q * /loopback_state.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * address_from_pc_1.Q * 
          /bpaddr(1).Q * from_pc_req.Q * /loopback_state.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * bpaddr(1).Q * loopback_state.Q * 
          /sensor_address_1.Q * sensor_to_bp_read_req.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * bpaddr(1).Q * /from_pc_req.Q * 
          /sensor_address_1.Q * sensor_to_bp_read_req.Q 

    bpaddr(1).C =
          clk 

    bpaddr(2).T =
          /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /bpaddr(2).Q * 
          loopback_state.Q * sensor_address_2.Q * sensor_to_bp_read_req.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /bpaddr(2).Q * /from_pc_req.Q * 
          sensor_address_2.Q * sensor_to_bp_read_req.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /address_from_pc_2.Q * 
          bpaddr(2).Q * from_pc_req.Q * /loopback_state.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * address_from_pc_2.Q * 
          /bpaddr(2).Q * from_pc_req.Q * /loopback_state.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * bpaddr(2).Q * loopback_state.Q * 
          /sensor_address_2.Q * sensor_to_bp_read_req.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * bpaddr(2).Q * /from_pc_req.Q * 
          /sensor_address_2.Q * sensor_to_bp_read_req.Q 

    bpaddr(2).C =
          clk 

    bpaddr(3).T =
          /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /bpaddr(3).Q * 
          loopback_state.Q * sensor_address_3.Q * sensor_to_bp_read_req.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /bpaddr(3).Q * /from_pc_req.Q * 
          sensor_address_3.Q * sensor_to_bp_read_req.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /address_from_pc_3.Q * 
          bpaddr(3).Q * from_pc_req.Q * /loopback_state.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * address_from_pc_3.Q * 
          /bpaddr(3).Q * from_pc_req.Q * /loopback_state.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * bpaddr(3).Q * loopback_state.Q * 
          /sensor_address_3.Q * sensor_to_bp_read_req.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * bpaddr(3).Q * /from_pc_req.Q * 
          /sensor_address_3.Q * sensor_to_bp_read_req.Q 

    bpaddr(3).C =
          clk 

    bpaddr(4).T =
          /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /bpaddr(4).Q * 
          loopback_state.Q * sensor_address_4.Q * sensor_to_bp_read_req.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /bpaddr(4).Q * /from_pc_req.Q * 
          sensor_address_4.Q * sensor_to_bp_read_req.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /address_from_pc_4.Q * 
          bpaddr(4).Q * from_pc_req.Q * /loopback_state.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * address_from_pc_4.Q * 
          /bpaddr(4).Q * from_pc_req.Q * /loopback_state.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * bpaddr(4).Q * loopback_state.Q * 
          /sensor_address_4.Q * sensor_to_bp_read_req.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * bpaddr(4).Q * /from_pc_req.Q * 
          /sensor_address_4.Q * sensor_to_bp_read_req.Q 

    bpaddr(4).C =
          clk 

    bpaddr(5).T =
          /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /bpaddr(5).Q * 
          loopback_state.Q * sensor_address_5.Q * sensor_to_bp_read_req.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /bpaddr(5).Q * /from_pc_req.Q * 
          sensor_address_5.Q * sensor_to_bp_read_req.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /address_from_pc_5.Q * 
          bpaddr(5).Q * from_pc_req.Q * /loopback_state.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * address_from_pc_5.Q * 
          /bpaddr(5).Q * from_pc_req.Q * /loopback_state.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * bpaddr(5).Q * loopback_state.Q * 
          /sensor_address_5.Q * sensor_to_bp_read_req.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * bpaddr(5).Q * /from_pc_req.Q * 
          /sensor_address_5.Q * sensor_to_bp_read_req.Q 

    bpaddr(5).C =
          clk 

    bpaddr(6).T =
          /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /bpaddr(6).Q * 
          loopback_state.Q * sensor_address_6.Q * sensor_to_bp_read_req.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /bpaddr(6).Q * /from_pc_req.Q * 
          sensor_address_6.Q * sensor_to_bp_read_req.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /address_from_pc_6.Q * 
          bpaddr(6).Q * from_pc_req.Q * /loopback_state.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * address_from_pc_6.Q * 
          /bpaddr(6).Q * from_pc_req.Q * /loopback_state.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * bpaddr(6).Q * loopback_state.Q * 
          /sensor_address_6.Q * sensor_to_bp_read_req.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * bpaddr(6).Q * /from_pc_req.Q * 
          /sensor_address_6.Q * sensor_to_bp_read_req.Q 

    bpaddr(6).C =
          clk 

    bpaddr(7).T =
          /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /bpaddr(7).Q * 
          loopback_state.Q * sensor_address_7.Q * sensor_to_bp_read_req.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /bpaddr(7).Q * /from_pc_req.Q * 
          sensor_address_7.Q * sensor_to_bp_read_req.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /address_from_pc_7.Q * 
          bpaddr(7).Q * from_pc_req.Q * /loopback_state.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * address_from_pc_7.Q * 
          /bpaddr(7).Q * from_pc_req.Q * /loopback_state.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * bpaddr(7).Q * loopback_state.Q * 
          /sensor_address_7.Q * sensor_to_bp_read_req.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * bpaddr(7).Q * /from_pc_req.Q * 
          /sensor_address_7.Q * sensor_to_bp_read_req.Q 

    bpaddr(7).C =
          clk 

    bpaddr_dir =
          GND

    bpaddr_tristate.D =
          \bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_1\.Q * 
          \bp_io:bp_access_stateSBV_2\.Q 
        + /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q 

    bpaddr_tristate.C =
          clk 

    bpctrl(0).D =
          /\bp_io:bp_access_stateSBV_0\.Q * from_pc_req.Q * 
          /loopback_state.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_2\.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_1\.Q 

    bpctrl(0).C =
          clk 

    bpctrl(1) =
          sinphase_zeros 

    bpctrl(10).T =
          /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * ao_from_pc_strobe * 
          /bpctrl(10).Q * d(11) 
        + /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * ao_from_pc_strobe * 
          bpctrl(10).Q * /d(11) 

    bpctrl(10).C =
          clk 

    bpctrl(10).OE =
          bpctrl(0).Q 

    bpctrl(11).T =
          /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * ao_from_pc_strobe * 
          /bpctrl(11).Q * d(12) 
        + /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * ao_from_pc_strobe * 
          bpctrl(11).Q * /d(12) 

    bpctrl(11).C =
          clk 

    bpctrl(11).OE =
          bpctrl(0).Q 

    bpctrl(2).D =
          /\bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_1\.Q * 
          \bp_io:bp_access_stateSBV_2\.Q 
        + \bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q 

    bpctrl(2).C =
          clk 

    bpctrl(3).D =
          \sp_read:counter_read_stateSBV_0\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q 

    bpctrl(3).C =
          clk 

    bpctrl(4).T =
          /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * ao_from_pc_strobe * 
          /bpctrl(4).Q * d(6) 
        + /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * ao_from_pc_strobe * 
          bpctrl(4).Q * /d(6) 

    bpctrl(4).C =
          clk 

    bpctrl(4).OE =
          bpctrl(0).Q 

    bpctrl(5).T =
          /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * ao_from_pc_strobe * 
          /bpctrl(5).Q * d(7) 
        + /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * ao_from_pc_strobe * 
          bpctrl(5).Q * /d(7) 

    bpctrl(5).C =
          clk 

    bpctrl(5).OE =
          bpctrl(0).Q 

    bpctrl(6).T =
          /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * ao_from_pc_strobe * 
          /bpctrl(6).Q * d(8) 
        + /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * ao_from_pc_strobe * 
          bpctrl(6).Q * /d(8) 

    bpctrl(6).C =
          clk 

    bpctrl(6).OE =
          bpctrl(0).Q 

    bpctrl(7).T =
          /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * ao_from_pc_strobe * 
          /bpctrl(7).Q * d(9) 
        + /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * ao_from_pc_strobe * 
          bpctrl(7).Q * /d(9) 

    bpctrl(7).C =
          clk 

    bpctrl(7).OE =
          bpctrl(0).Q 

    bpctrl(8).T =
          /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * ao_from_pc_strobe * 
          /bpctrl(8).Q * d(10) 
        + /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * ao_from_pc_strobe * 
          bpctrl(8).Q * /d(10) 

    bpctrl(8).C =
          clk 

    bpctrl(8).OE =
          bpctrl(0).Q 

    bpctrl_h_dir =
          GND

    bpctrl_h_tristate =
          bpd_h_tristate.Q 

    bpctrl_l_dir =
          GND

    bpctrl_l_tristate =
          GND

    bpd(10).T =
          /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * ao_from_pc_strobe * 
          /bpd(10).Q * d(0) 
        + /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * ao_from_pc_strobe * 
          bpd(10).Q * /d(0) 

    bpd(10).C =
          clk 

    bpd(10).OE =
          bpctrl(0).Q 

    bpd(11).T =
          /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * ao_from_pc_strobe * 
          /bpd(11).Q * d(1) 
        + /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * ao_from_pc_strobe * 
          bpd(11).Q * /d(1) 

    bpd(11).C =
          clk 

    bpd(11).OE =
          bpctrl(0).Q 

    bpd(12).T =
          /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * ao_from_pc_strobe * 
          /bpd(12).Q * d(2) 
        + /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * ao_from_pc_strobe * 
          bpd(12).Q * /d(2) 

    bpd(12).C =
          clk 

    bpd(12).OE =
          bpctrl(0).Q 

    bpd(13).T =
          /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * ao_from_pc_strobe * 
          /bpd(13).Q * d(3) 
        + /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * ao_from_pc_strobe * 
          bpd(13).Q * /d(3) 

    bpd(13).C =
          clk 

    bpd(13).OE =
          bpctrl(0).Q 

    bpd(14).T =
          /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * ao_from_pc_strobe * 
          /bpd(14).Q * d(4) 
        + /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * ao_from_pc_strobe * 
          bpd(14).Q * /d(4) 

    bpd(14).C =
          clk 

    bpd(14).OE =
          bpctrl(0).Q 

    bpd(15).T =
          /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * ao_from_pc_strobe * 
          /bpd(15).Q * d(5) 
        + /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * ao_from_pc_strobe * 
          bpd(15).Q * /d(5) 

    bpd(15).C =
          clk 

    bpd(15).OE =
          bpctrl(0).Q 

    bpd_h_dir =
          /bpctrl(0).Q 

    bpd_h_tristate.D =
          /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * from_pc_req.Q * 
          /loopback_state.Q 
        + \bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_1\.Q * 
          \bp_io:bp_access_stateSBV_2\.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * 
          /\bp_io:bp_access_stateSBV_1\.Q * \bp_io:bp_access_stateSBV_2\.Q 
        + \bp_io:bp_access_stateSBV_0\.Q * /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q 
        + /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /sensor_to_bp_read_req.Q 

    bpd_h_tristate.C =
          clk 

    bpd_l_dir =
          /bpctrl(0).Q 

    bpd_l_tristate =
          bpd_h_tristate.Q 

    d(16).T =
          /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          /bpd(10).Q * d(16).Q * from_pc_req.Q * loopback_state.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          bpd(10).Q * /d(16).Q * from_pc_req.Q * loopback_state.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          /d(16).Q * /loopback_state.Q * sensor_data_0.Q * 
          sensor_to_ibus_req.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          d(16).Q * /loopback_state.Q * /sensor_data_0.Q * 
          sensor_to_ibus_req.Q 

    d(16).C =
          clk 

    d(17).T =
          /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          /bpd(11).Q * d(17).Q * from_pc_req.Q * loopback_state.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          bpd(11).Q * /d(17).Q * from_pc_req.Q * loopback_state.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          /d(17).Q * /loopback_state.Q * sensor_data_1.Q * 
          sensor_to_ibus_req.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          d(17).Q * /loopback_state.Q * /sensor_data_1.Q * 
          sensor_to_ibus_req.Q 

    d(17).C =
          clk 

    d(18).T =
          /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          /bpd(12).Q * d(18).Q * from_pc_req.Q * loopback_state.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          bpd(12).Q * /d(18).Q * from_pc_req.Q * loopback_state.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          /d(18).Q * /loopback_state.Q * sensor_data_2.Q * 
          sensor_to_ibus_req.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          d(18).Q * /loopback_state.Q * /sensor_data_2.Q * 
          sensor_to_ibus_req.Q 

    d(18).C =
          clk 

    d(19).T =
          /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          /bpd(13).Q * d(19).Q * from_pc_req.Q * loopback_state.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          bpd(13).Q * /d(19).Q * from_pc_req.Q * loopback_state.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          /d(19).Q * /loopback_state.Q * sensor_data_3.Q * 
          sensor_to_ibus_req.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          d(19).Q * /loopback_state.Q * /sensor_data_3.Q * 
          sensor_to_ibus_req.Q 

    d(19).C =
          clk 

    d(20).T =
          /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          /bpd(14).Q * d(20).Q * from_pc_req.Q * loopback_state.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          bpd(14).Q * /d(20).Q * from_pc_req.Q * loopback_state.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          /d(20).Q * /loopback_state.Q * sensor_data_4.Q * 
          sensor_to_ibus_req.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          d(20).Q * /loopback_state.Q * /sensor_data_4.Q * 
          sensor_to_ibus_req.Q 

    d(20).C =
          clk 

    d(21).T =
          /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          /bpd(15).Q * d(21).Q * from_pc_req.Q * loopback_state.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          bpd(15).Q * /d(21).Q * from_pc_req.Q * loopback_state.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          /d(21).Q * /loopback_state.Q * sensor_data_5.Q * 
          sensor_to_ibus_req.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          d(21).Q * /loopback_state.Q * /sensor_data_5.Q * 
          sensor_to_ibus_req.Q 

    d(21).C =
          clk 

    d(22).T =
          /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          /bpctrl(4).Q * d(22).Q * from_pc_req.Q * loopback_state.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          bpctrl(4).Q * /d(22).Q * from_pc_req.Q * loopback_state.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          /d(22).Q * /loopback_state.Q * sensor_data_6.Q * 
          sensor_to_ibus_req.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          d(22).Q * /loopback_state.Q * /sensor_data_6.Q * 
          sensor_to_ibus_req.Q 

    d(22).C =
          clk 

    d(23).T =
          /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          /bpctrl(5).Q * d(23).Q * from_pc_req.Q * loopback_state.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          bpctrl(5).Q * /d(23).Q * from_pc_req.Q * loopback_state.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          /d(23).Q * /loopback_state.Q * sensor_data_7.Q * 
          sensor_to_ibus_req.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          d(23).Q * /loopback_state.Q * /sensor_data_7.Q * 
          sensor_to_ibus_req.Q 

    d(23).C =
          clk 

    d(24).T =
          /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          /bpctrl(6).Q * d(24).Q * from_pc_req.Q * loopback_state.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          bpctrl(6).Q * /d(24).Q * from_pc_req.Q * loopback_state.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          /d(24).Q * /loopback_state.Q * sensor_data_8.Q * 
          sensor_to_ibus_req.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          d(24).Q * /loopback_state.Q * /sensor_data_8.Q * 
          sensor_to_ibus_req.Q 

    d(24).C =
          clk 

    d(25).T =
          /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          /bpctrl(7).Q * d(25).Q * from_pc_req.Q * loopback_state.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          bpctrl(7).Q * /d(25).Q * from_pc_req.Q * loopback_state.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          /d(25).Q * /loopback_state.Q * sensor_data_9.Q * 
          sensor_to_ibus_req.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          d(25).Q * /loopback_state.Q * /sensor_data_9.Q * 
          sensor_to_ibus_req.Q 

    d(25).C =
          clk 

    d(26).T =
          /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          /bpctrl(8).Q * d(26).Q * from_pc_req.Q * loopback_state.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          bpctrl(8).Q * /d(26).Q * from_pc_req.Q * loopback_state.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          /d(26).Q * /loopback_state.Q * sensor_data_10.Q * 
          sensor_to_ibus_req.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          d(26).Q * /loopback_state.Q * /sensor_data_10.Q * 
          sensor_to_ibus_req.Q 

    d(26).C =
          clk 

    d(27).T =
          /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          /bpctrl(10).Q * d(27).Q * from_pc_req.Q * loopback_state.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          bpctrl(10).Q * /d(27).Q * from_pc_req.Q * loopback_state.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          /d(27).Q * /loopback_state.Q * sensor_data_11.Q * 
          sensor_to_ibus_req.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          d(27).Q * /loopback_state.Q * /sensor_data_11.Q * 
          sensor_to_ibus_req.Q 

    d(27).C =
          clk 

    d(28).T =
          /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          /bpctrl(11).Q * d(28).Q * from_pc_req.Q * loopback_state.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          bpctrl(11).Q * /d(28).Q * from_pc_req.Q * loopback_state.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          /d(28).Q * /loopback_state.Q * sensor_data_12.Q * 
          sensor_to_ibus_req.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          d(28).Q * /loopback_state.Q * /sensor_data_12.Q * 
          sensor_to_ibus_req.Q 

    d(28).C =
          clk 

    d(29).T =
          /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          /d(29).Q * data_from_pc_13.Q * from_pc_req.Q * loopback_state.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          d(29).Q * /data_from_pc_13.Q * from_pc_req.Q * loopback_state.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          /d(29).Q * /loopback_state.Q * sensor_data_13.Q * 
          sensor_to_ibus_req.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          d(29).Q * /loopback_state.Q * /sensor_data_13.Q * 
          sensor_to_ibus_req.Q 

    d(29).C =
          clk 

    d(30).T =
          /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          /d(30).Q * data_from_pc_14.Q * from_pc_req.Q * loopback_state.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          d(30).Q * /data_from_pc_14.Q * from_pc_req.Q * loopback_state.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          /d(30).Q * /loopback_state.Q * sensor_data_14.Q * 
          sensor_to_ibus_req.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          d(30).Q * /loopback_state.Q * /sensor_data_14.Q * 
          sensor_to_ibus_req.Q 

    d(30).C =
          clk 

    d(31).T =
          /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          /d(31).Q * data_from_pc_15.Q * from_pc_req.Q * loopback_state.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          d(31).Q * /data_from_pc_15.Q * from_pc_req.Q * loopback_state.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          /d(31).Q * /loopback_state.Q * sensor_data_15.Q * 
          sensor_to_ibus_req.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /\ibus_writer:iu_writeSBV_1\.Q * 
          d(31).Q * /loopback_state.Q * /sensor_data_15.Q * 
          sensor_to_ibus_req.Q 

    d(31).C =
          clk 

    data_from_pc_13.T =
          /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * ao_from_pc_strobe * /d(13) * 
          data_from_pc_13.Q 
        + /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * ao_from_pc_strobe * d(13) * 
          /data_from_pc_13.Q 

    data_from_pc_13.C =
          clk 

    data_from_pc_14.T =
          /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * ao_from_pc_strobe * /d(14) * 
          data_from_pc_14.Q 
        + /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * ao_from_pc_strobe * d(14) * 
          /data_from_pc_14.Q 

    data_from_pc_14.C =
          clk 

    data_from_pc_15.T =
          /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * ao_from_pc_strobe * /d(15) * 
          data_from_pc_15.Q 
        + /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * ao_from_pc_strobe * d(15) * 
          /data_from_pc_15.Q 

    data_from_pc_15.C =
          clk 

    from_pc_req.D =
          \ibus_reader:il_read_stateSBV_0\.Q * 
          \ibus_reader:il_read_stateSBV_2\.Q * loopback_state.Q * 
          /to_pc_ack.Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * 
          \ibus_reader:il_read_stateSBV_2\.Q * /loopback_state.Q * 
          /write_to_bp_ack.Q 
        + \ibus_reader:il_read_stateSBV_1\.Q * 
          \ibus_reader:il_read_stateSBV_2\.Q * 
          /\ibus_reader:this_is_a_ctrl_transaction\.Q 

    from_pc_req.C =
          clk 

    il_tristate.D =
          il_tristate.Q * this_chip_selected.Q * tristate_stateSBV_0.Q 
        + /this_chip_selected.Q * /tristate_stateSBV_0.Q 

    il_tristate.C =
          clk 

    /led1.D =
          /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * from_pc_req.Q * 
          /loopback_state.Q 
        + \bp_io:bp_access_stateSBV_0\.Q * /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q 
        + /\bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_1\.Q 

    led1.C =
          clk 

    led2 =
          fast 

    led3 =
          slow 

    loopback_state.T =
          /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          /\ibus_reader:il_read_stateSBV_2\.Q * loopback_state.Q 

    loopback_state.AP =
          GND

    loopback_state.AR =
          reset.CMB 

    loopback_state.C =
          clk 

    reset =
          fast * /slow 

    sensor_address_0.T =
          /\sp_read:counter_address_0\.Q * /\sp_read:counter_address_3\.Q * 
          /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q * sensor_address_0.Q 
        + /\sp_read:counter_address_0\.Q * /\sp_read:counter_address_4\.Q * 
          /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q * sensor_address_0.Q 
        + \sp_read:counter_address_0\.Q * /\sp_read:counter_address_3\.Q * 
          /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q * /sensor_address_0.Q 
        + \sp_read:counter_address_0\.Q * /\sp_read:counter_address_4\.Q * 
          /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q * /sensor_address_0.Q 

    sensor_address_0.C =
          clk 

    sensor_address_1.T =
          /\sp_read:counter_address_1\.Q * /\sp_read:counter_address_3\.Q * 
          /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q * sensor_address_1.Q 
        + /\sp_read:counter_address_1\.Q * /\sp_read:counter_address_4\.Q * 
          /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q * sensor_address_1.Q 
        + \sp_read:counter_address_1\.Q * /\sp_read:counter_address_3\.Q * 
          /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q * /sensor_address_1.Q 
        + \sp_read:counter_address_1\.Q * /\sp_read:counter_address_4\.Q * 
          /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q * /sensor_address_1.Q 

    sensor_address_1.C =
          clk 

    sensor_address_2.T =
          /\sp_read:counter_address_2\.Q * /\sp_read:counter_address_3\.Q * 
          /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q * sensor_address_2.Q 
        + /\sp_read:counter_address_2\.Q * /\sp_read:counter_address_4\.Q * 
          /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q * sensor_address_2.Q 
        + \sp_read:counter_address_2\.Q * /\sp_read:counter_address_3\.Q * 
          /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q * /sensor_address_2.Q 
        + \sp_read:counter_address_2\.Q * /\sp_read:counter_address_4\.Q * 
          /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q * /sensor_address_2.Q 

    sensor_address_2.C =
          clk 

    sensor_address_3.T =
          \sp_read:counter_address_3\.Q * /\sp_read:counter_address_4\.Q * 
          /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q * /sensor_address_3.Q 
        + /\sp_read:counter_address_3\.Q * 
          /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q * sensor_address_3.Q 

    sensor_address_3.C =
          clk 

    sensor_address_4.T =
          /\sp_read:counter_address_3\.Q * \sp_read:counter_address_4\.Q * 
          /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q * /sensor_address_4.Q 
        + /\sp_read:counter_address_4\.Q * 
          /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q * sensor_address_4.Q 

    sensor_address_4.C =
          clk 

    sensor_address_5.T =
          /\sp_read:counter_address_3\.Q * /\sp_read:counter_address_5\.Q * 
          /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q * sensor_address_5.Q 
        + /\sp_read:counter_address_4\.Q * /\sp_read:counter_address_5\.Q * 
          /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q * sensor_address_5.Q 
        + /\sp_read:counter_address_3\.Q * \sp_read:counter_address_5\.Q * 
          /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q * /sensor_address_5.Q 
        + /\sp_read:counter_address_4\.Q * \sp_read:counter_address_5\.Q * 
          /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q * /sensor_address_5.Q 

    sensor_address_5.C =
          clk 

    sensor_address_6.T =
          /\sp_read:counter_address_3\.Q * /\sp_read:counter_address_6\.Q * 
          /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q * sensor_address_6.Q 
        + /\sp_read:counter_address_4\.Q * /\sp_read:counter_address_6\.Q * 
          /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q * sensor_address_6.Q 
        + /\sp_read:counter_address_3\.Q * \sp_read:counter_address_6\.Q * 
          /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q * /sensor_address_6.Q 
        + /\sp_read:counter_address_4\.Q * \sp_read:counter_address_6\.Q * 
          /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q * /sensor_address_6.Q 

    sensor_address_6.C =
          clk 

    sensor_address_7.T =
          /\sp_read:counter_address_3\.Q * /\sp_read:counter_address_7\.Q * 
          /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q * sensor_address_7.Q 
        + /\sp_read:counter_address_4\.Q * /\sp_read:counter_address_7\.Q * 
          /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q * sensor_address_7.Q 
        + /\sp_read:counter_address_3\.Q * \sp_read:counter_address_7\.Q * 
          /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q * /sensor_address_7.Q 
        + /\sp_read:counter_address_4\.Q * \sp_read:counter_address_7\.Q * 
          /\sp_read:counter_read_stateSBV_0\.Q * 
          /\sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q * /sensor_address_7.Q 

    sensor_address_7.C =
          clk 

    sensor_data_0.T =
          \bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /\bp_io:timeout_0\.Q * 
          \bp_io:timeout_1\.Q * /\bp_io:timeout_2\.Q * /bpd(0) * 
          sensor_data_0.Q 
        + \bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /\bp_io:timeout_0\.Q * 
          \bp_io:timeout_1\.Q * /\bp_io:timeout_2\.Q * bpd(0) * 
          /sensor_data_0.Q 

    sensor_data_0.C =
          clk 

    sensor_data_1.T =
          \bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /\bp_io:timeout_0\.Q * 
          \bp_io:timeout_1\.Q * /\bp_io:timeout_2\.Q * /bpd(1) * 
          sensor_data_1.Q 
        + \bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /\bp_io:timeout_0\.Q * 
          \bp_io:timeout_1\.Q * /\bp_io:timeout_2\.Q * bpd(1) * 
          /sensor_data_1.Q 

    sensor_data_1.C =
          clk 

    sensor_data_10.T =
          \bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /\bp_io:timeout_0\.Q * 
          \bp_io:timeout_1\.Q * /\bp_io:timeout_2\.Q * /bpd(10) * 
          sensor_data_10.Q 
        + \bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /\bp_io:timeout_0\.Q * 
          \bp_io:timeout_1\.Q * /\bp_io:timeout_2\.Q * bpd(10) * 
          /sensor_data_10.Q 

    sensor_data_10.C =
          clk 

    sensor_data_11.T =
          \bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /\bp_io:timeout_0\.Q * 
          \bp_io:timeout_1\.Q * /\bp_io:timeout_2\.Q * /bpd(11) * 
          sensor_data_11.Q 
        + \bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /\bp_io:timeout_0\.Q * 
          \bp_io:timeout_1\.Q * /\bp_io:timeout_2\.Q * bpd(11) * 
          /sensor_data_11.Q 

    sensor_data_11.C =
          clk 

    sensor_data_12.T =
          \bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /\bp_io:timeout_0\.Q * 
          \bp_io:timeout_1\.Q * /\bp_io:timeout_2\.Q * /bpd(12) * 
          sensor_data_12.Q 
        + \bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /\bp_io:timeout_0\.Q * 
          \bp_io:timeout_1\.Q * /\bp_io:timeout_2\.Q * bpd(12) * 
          /sensor_data_12.Q 

    sensor_data_12.C =
          clk 

    sensor_data_13.T =
          \bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /\bp_io:timeout_0\.Q * 
          \bp_io:timeout_1\.Q * /\bp_io:timeout_2\.Q * /bpd(13) * 
          sensor_data_13.Q 
        + \bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /\bp_io:timeout_0\.Q * 
          \bp_io:timeout_1\.Q * /\bp_io:timeout_2\.Q * bpd(13) * 
          /sensor_data_13.Q 

    sensor_data_13.C =
          clk 

    sensor_data_14.T =
          \bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /\bp_io:timeout_0\.Q * 
          \bp_io:timeout_1\.Q * /\bp_io:timeout_2\.Q * /bpd(14) * 
          sensor_data_14.Q 
        + \bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /\bp_io:timeout_0\.Q * 
          \bp_io:timeout_1\.Q * /\bp_io:timeout_2\.Q * bpd(14) * 
          /sensor_data_14.Q 

    sensor_data_14.C =
          clk 

    sensor_data_15.T =
          \sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q * sensor_data_15.Q * 
          sensor_to_bp_read_ack.Q * sinphase_zeros 
        + \sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q * /sensor_data_15.Q * 
          sensor_to_bp_read_ack.Q * /sinphase_zeros 

    sensor_data_15.C =
          clk 

    sensor_data_2.T =
          \bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /\bp_io:timeout_0\.Q * 
          \bp_io:timeout_1\.Q * /\bp_io:timeout_2\.Q * /bpd(2) * 
          sensor_data_2.Q 
        + \bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /\bp_io:timeout_0\.Q * 
          \bp_io:timeout_1\.Q * /\bp_io:timeout_2\.Q * bpd(2) * 
          /sensor_data_2.Q 

    sensor_data_2.C =
          clk 

    sensor_data_3.T =
          \bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /\bp_io:timeout_0\.Q * 
          \bp_io:timeout_1\.Q * /\bp_io:timeout_2\.Q * /bpd(3) * 
          sensor_data_3.Q 
        + \bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /\bp_io:timeout_0\.Q * 
          \bp_io:timeout_1\.Q * /\bp_io:timeout_2\.Q * bpd(3) * 
          /sensor_data_3.Q 

    sensor_data_3.C =
          clk 

    sensor_data_4.T =
          \bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /\bp_io:timeout_0\.Q * 
          \bp_io:timeout_1\.Q * /\bp_io:timeout_2\.Q * /bpd(4) * 
          sensor_data_4.Q 
        + \bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /\bp_io:timeout_0\.Q * 
          \bp_io:timeout_1\.Q * /\bp_io:timeout_2\.Q * bpd(4) * 
          /sensor_data_4.Q 

    sensor_data_4.C =
          clk 

    sensor_data_5.T =
          \bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /\bp_io:timeout_0\.Q * 
          \bp_io:timeout_1\.Q * /\bp_io:timeout_2\.Q * /bpd(5) * 
          sensor_data_5.Q 
        + \bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /\bp_io:timeout_0\.Q * 
          \bp_io:timeout_1\.Q * /\bp_io:timeout_2\.Q * bpd(5) * 
          /sensor_data_5.Q 

    sensor_data_5.C =
          clk 

    sensor_data_6.T =
          \bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /\bp_io:timeout_0\.Q * 
          \bp_io:timeout_1\.Q * /\bp_io:timeout_2\.Q * /bpd(6) * 
          sensor_data_6.Q 
        + \bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /\bp_io:timeout_0\.Q * 
          \bp_io:timeout_1\.Q * /\bp_io:timeout_2\.Q * bpd(6) * 
          /sensor_data_6.Q 

    sensor_data_6.C =
          clk 

    sensor_data_7.T =
          \bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /\bp_io:timeout_0\.Q * 
          \bp_io:timeout_1\.Q * /\bp_io:timeout_2\.Q * /bpd(7) * 
          sensor_data_7.Q 
        + \bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /\bp_io:timeout_0\.Q * 
          \bp_io:timeout_1\.Q * /\bp_io:timeout_2\.Q * bpd(7) * 
          /sensor_data_7.Q 

    sensor_data_7.C =
          clk 

    sensor_data_8.T =
          \bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /\bp_io:timeout_0\.Q * 
          \bp_io:timeout_1\.Q * /\bp_io:timeout_2\.Q * /bpd(8) * 
          sensor_data_8.Q 
        + \bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /\bp_io:timeout_0\.Q * 
          \bp_io:timeout_1\.Q * /\bp_io:timeout_2\.Q * bpd(8) * 
          /sensor_data_8.Q 

    sensor_data_8.C =
          clk 

    sensor_data_9.T =
          \bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /\bp_io:timeout_0\.Q * 
          \bp_io:timeout_1\.Q * /\bp_io:timeout_2\.Q * /bpd(9) * 
          sensor_data_9.Q 
        + \bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q * /\bp_io:timeout_0\.Q * 
          \bp_io:timeout_1\.Q * /\bp_io:timeout_2\.Q * bpd(9) * 
          /sensor_data_9.Q 

    sensor_data_9.C =
          clk 

    sensor_to_bp_read_ack.D =
          \bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:timeout_0\.Q * \bp_io:timeout_1\.Q * 
          /\bp_io:timeout_2\.Q 
        + \bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_1\.Q * 
          \bp_io:bp_access_stateSBV_2\.Q 

    sensor_to_bp_read_ack.C =
          clk 

    sensor_to_bp_read_req.D =
          \sp_read:counter_read_stateSBV_1\.Q * 
          /\sp_read:counter_read_stateSBV_2\.Q * 
          \sp_read:counter_read_stateSBV_3\.Q * /sensor_to_bp_read_ack.Q 

    sensor_to_bp_read_req.C =
          clk 

    sensor_to_ibus_req.D =
          \sp_read:counter_read_stateSBV_1\.Q * 
          \sp_read:counter_read_stateSBV_2\.Q * loopback_state.Q 
        + \sp_read:counter_read_stateSBV_1\.Q * 
          \sp_read:counter_read_stateSBV_2\.Q * 
          /\sp_read:counter_read_stateSBV_3\.Q 
        + \sp_read:counter_read_stateSBV_1\.Q * 
          \sp_read:counter_read_stateSBV_2\.Q * /to_pc_ack.Q 

    sensor_to_ibus_req.C =
          clk 

    this_chip_selected.D =
          /\ibus_reader:il_read_stateSBV_0\.Q * 
          /\ibus_reader:il_read_stateSBV_1\.Q * 
          \ibus_reader:il_read_stateSBV_2\.Q * /bpctrl(10).Q * 
          bpctrl(11).Q * /bpctrl(7).Q * /bpctrl(8).Q * data_from_pc_15.Q 
        + \ibus_reader:il_read_stateSBV_1\.Q * this_chip_selected.Q 
        + \ibus_reader:il_read_stateSBV_0\.Q * this_chip_selected.Q 
        + /\ibus_reader:il_read_stateSBV_2\.Q * this_chip_selected.Q 
        + /data_from_pc_15.Q * this_chip_selected.Q 

    this_chip_selected.AP =
          GND

    this_chip_selected.AR =
          reset.CMB 

    this_chip_selected.C =
          clk 

    to_pc_ack.D =
          /\ibus_writer:iu_writeSBV_0\.Q * from_pc_req.Q * 
          loopback_state.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * /loopback_state.Q * 
          sensor_to_ibus_req.Q 
        + /\ibus_writer:iu_writeSBV_0\.Q * \ibus_writer:iu_writeSBV_1\.Q 

    to_pc_ack.C =
          clk 

    tristate_stateSBV_0.D =
          this_chip_selected.Q 

    tristate_stateSBV_0.C =
          clk 

    write_to_bp_ack.D =
          /\bp_io:bp_access_stateSBV_0\.Q * \bp_io:bp_access_stateSBV_1\.Q * 
          \bp_io:bp_access_stateSBV_2\.Q * /\bp_io:timeout_0\.Q * 
          \bp_io:timeout_1\.Q * /\bp_io:timeout_2\.Q 
        + \bp_io:bp_access_stateSBV_0\.Q * /\bp_io:bp_access_stateSBV_1\.Q * 
          /\bp_io:bp_access_stateSBV_2\.Q 

    write_to_bp_ack.C =
          clk 


Completed Successfully  
----------------------------------------------------------------------------
PLD Compiler Software:        C37KFIT.EXE    22/DEC/2000  [v4.02 ] 6.2 IR 27

DESIGN RULE CHECK          (20:13:13)

Messages:
                 None.


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully  
----------------------------------------------------------------------------
PLD Compiler Software:        C37KFIT.EXE    22/DEC/2000  [v4.02 ] 6.2 IR 27

PARTITION LOGIC            (20:13:13)

Messages:
  Information: Initializing Logic Block structures.
  Information: Forming input seeds.
  Information: Checking for duplicate NODE logic.
  Information: Forming input seeds.
  Information: Assigning fixed logic to Logic Blocks.
  Information: Processing banked global preset, reset and output enable.
  Information: Separating output logic set to GND/VCC.
  Information: Validating Logic Block's with pre-placed signals.
  Information: Separating input register logic.
  Information: Assigning initializing equations to empty Logic Blocks.
  Information: Separating output combinatorial logic.
  Information: Separating disjoint output logic.
  Information: Separating output node logic.
  Information: Assigning floating outputs to Logic Blocks.
  Information: Compacting Logic Block interconnect.
  .+..+.................................+................................
  +......................................................................
  .......................................................................
  .................
  Information: Separating output logic with >= 16 pt's.
  Information: Assigning floating outputs to Logic Blocks.
  Information: Minimizing interconnect between Logic Blocks.
  .....+...............++....+...........+....+...............
Start=20:13:13  End=20:13:14
  Information: Separating disjoint output logic.
  Information: Separating output node logic.
  Information: Assigning floating outputs to Logic Blocks.
  Information: Assigning floating outputs to Logic Blocks.
  Information: Assigning floating outputs to Logic Blocks.
  Information: Minimizing interconnect between Logic Blocks.
  .++..++..+.+..+....+....+..+..+.............+.........+...............
Start=20:13:14  End=20:13:14
  Information: Assigning floating outputs to Logic Blocks.
  Information: Minimizing interconnect between Logic Blocks.
  ...............
Start=20:13:14  End=20:13:15
  Information: Condensing mcell usuage in Logic Blocks with high routing (1).
  ..+.+.+..+++.++.++.+..+.++...+
  Information: Assigning floating outputs to Logic Blocks.
  Information: Condensing mcell usuage in Logic Blocks with high routing (2).
  .+..+.++..++..+..+.+..++..
Start=20:13:15  End=20:13:20
  Information: Assigning floating outputs to Logic Blocks.
  Information: Reducing logic on list of signals still to be fit.
  
Start=20:13:20  End=20:13:20


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully  
----------------------------------------------------------------------------
PLD Compiler Software:        C37KFIT.EXE    22/DEC/2000  [v4.02 ] 6.2 IR 27

DESIGN SIGNAL PLACEMENT    (20:13:21)

Messages:
  Information: Fitting signals to Logic Block A.
  Information: Assigning Signals to Macrocells.
  Information: Improving Macrocell Assignment
  ................
  Information: Assigning Product Terms to Allocator
  Information: Combining '\bp_io:bp_access_stateSBV_1\' definition with input pin 'bpd(0)'.
  Information: Combining '\sp_read:counter_address_3\' definition with input pin 'bpd(3)'.
  Information: Combining '\sp_read:counter_address_4\' definition with input pin 'bpd(4)'.
  Information: Combining '\sp_read:counter_address_7\' definition with input pin 'bpd(2)'.
  Information: Combining 'sensor_data_1' definition with input pin 'bpd(5)'.
  Information: Combining 'sensor_data_4' definition with input pin 'bpd(6)'.
  Information: Combining 'sensor_data_5' definition with input pin 'bpd(1)'.
  Information: Combining 'tristate_stateSBV_0' definition with input pin 'bpd(7)'.
  Information: Fitting signals to Logic Block B.
  Information: Assigning Signals to Macrocells.
  Information: Improving Macrocell Assignment
  ................
  Information: Assigning Product Terms to Allocator
  Information: Fitting signals to Logic Block C.
  Information: Assigning Signals to Macrocells.
  Information: Improving Macrocell Assignment
  ................
  Information: Assigning Product Terms to Allocator
  Information: Fitting signals to Logic Block D.
  Information: Assigning Signals to Macrocells.
  Information: Improving Macrocell Assignment
  ................
  Information: Assigning Product Terms to Allocator
  Information: Fitting signals to Logic Block E.
  Information: Assigning Signals to Macrocells.
  Information: Improving Macrocell Assignment
  ................
  Information: Assigning Product Terms to Allocator
  Information: Fitting signals to Logic Block F.
  Information: Assigning Signals to Macrocells.
  Information: Improving Macrocell Assignment
  ................
  Information: Assigning Product Terms to Allocator
  Information: Fitting signals to Logic Block G.
  Information: Assigning Signals to Macrocells.
  Information: Improving Macrocell Assignment
  ..+................+..............................
  Information: Assigning Product Terms to Allocator
  Information: Assigning Signals to Macrocells.
  Information: Improving Macrocell Assignment
  ................
  Information: Assigning Product Terms to Allocator
  Information: Fitting signals to Logic Block H.
  Information: Assigning Signals to Macrocells.
  Information: Improving Macrocell Assignment
  ..+................+..............................
  Information: Assigning Product Terms to Allocator
  Information: Fitting signals to Logic Block I.
  Information: Assigning Signals to Macrocells.
  Information: Improving Macrocell Assignment
  ................
  Information: Assigning Product Terms to Allocator
  Information: Combining 'this_chip_selected' definition with input pin 'sinphase_zeros'.
  Information: Fitting signals to Logic Block J.
  Information: Assigning Signals to Macrocells.
  Information: Improving Macrocell Assignment
  .+.+.+..+............+.+..............................
  Information: Assigning Product Terms to Allocator
  Information: Assigning Signals to Macrocells.
  Information: Improving Macrocell Assignment
  ................
  Information: Assigning Product Terms to Allocator
  Information: Assigning Signals to Macrocells.
  Information: Improving Macrocell Assignment
  ..+................+..............................
  Information: Assigning Product Terms to Allocator
  Information: Assigning Signals to Macrocells.
  Information: Improving Macrocell Assignment
  ................
  Information: Assigning Product Terms to Allocator
  Information: Fitting signals to Logic Block K.
  Information: Assigning Signals to Macrocells.
  Information: Improving Macrocell Assignment
  ...+.+...+...........+..+............................
  Information: Assigning Product Terms to Allocator
  Information: Assigning Signals to Macrocells.
  Information: Improving Macrocell Assignment
  ................
  Information: Assigning Product Terms to Allocator
  Information: Assigning Signals to Macrocells.
  Information: Improving Macrocell Assignment
  ................
  Information: Assigning Product Terms to Allocator
  Information: Assigning Signals to Macrocells.
  Information: Improving Macrocell Assignment
  ................
  Information: Assigning Product Terms to Allocator
  Information: Fitting signals to Logic Block L.
  Information: Assigning Signals to Macrocells.
  Information: Improving Macrocell Assignment
  .+.+.+..............+.+.+.....+..........+.+...............+.+..........
  ...................
  Information: Assigning Product Terms to Allocator
  Information: Assigning Signals to Macrocells.
  Information: Improving Macrocell Assignment
  ................
  Information: Assigning Product Terms to Allocator
  Information: Assigning Signals to Macrocells.
  Information: Improving Macrocell Assignment
  ................
  Information: Assigning Product Terms to Allocator
  Information: Combining 'sensor_address_3' definition with input pin 'ao_to_pc_ack'.
  Information: Fitting signals to Logic Block M.
  Information: Assigning Signals to Macrocells.
  Information: Improving Macrocell Assignment
  ................
  Information: Assigning Product Terms to Allocator
  Information: Combining '\sp_read:delay_count_0\' definition with input pin 'd(1)'.
  Information: Combining '\sp_read:delay_count_5\' definition with input pin 'd(7)'.
  Information: Combining '\ibus_writer:iu_writeSBV_1\' definition with input pin 'd(4)'.
  Information: Combining 'S_1' definition with input pin 'd(5)'.
  Information: Fitting signals to Logic Block N.
  Information: Assigning Signals to Macrocells.
  Information: Improving Macrocell Assignment
  ................
  Information: Assigning Product Terms to Allocator
  Information: Assigning Signals to Macrocells.
  Information: Improving Macrocell Assignment
  ................
  Information: Assigning Product Terms to Allocator
  Information: Combining 'S_3' definition with input pin 'd(9)'.
  Information: Fitting signals to Logic Block O.
  Information: Assigning Signals to Macrocells.
  Information: Improving Macrocell Assignment
  ..+............+..................
  Information: Assigning Product Terms to Allocator
  Information: Fitting signals to Logic Block P.
  Information: Assigning Signals to Macrocells.
  Information: Improving Macrocell Assignment
  ................
  Information: Assigning Product Terms to Allocator
  Information: Routing signals to Logic Blocks.


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully  
----------------------------------------------------------------------------
PLD Compiler Software:        C37KFIT.EXE    22/DEC/2000  [v4.02 ] 6.2 IR 27

LOGIC BLOCK A PLACEMENT   (20:13:21)

Messages:


________________________________________________________________________________
          1111111111222222222233333333334444444444555555555566666666667777777777
01234567890123456789012345678901234567890123456789012345678901234567890123456789
________________________________________________________________________________
| 0 |(\bp_io:bp_access_stateSBV_1\)bpd(0)
XXXX++X+++++++++................................................................
| 1 |(sensor_data_7)
......++XX++++++++++++..........................................................
| 2 |(sensor_data_5)bpd(1)
..........XX++++++++++++++......................................................
| 3 |(sensor_data_2)
..............XX++++++++++++++..................................................
| 4 |(\sp_read:counter_address_7\)bpd(2)
..................XX++++++++++++++..............................................
| 5 |(\sp_read:counter_address_5\)
......................XX++++++++++++++..........................................
| 6 |(\sp_read:counter_address_3\)bpd(3)
..........................XX++++++++++++++......................................
| 7 |(\sp_read:counter_address_2\)
..............................XX++++++++++++++..................................
| 8 |(\sp_read:counter_address_4\)bpd(4)
..................................XX++++++++++++++..............................
| 9 |(\sp_read:counter_address_6\)
......................................XX++++++++++++++..........................
|10 |(sensor_data_1)bpd(5)
..........................................XX++++++++++++++......................
|11 |(sensor_data_3)
..............................................XX++++++++++++++..................
|12 |(sensor_data_4)bpd(6)
..................................................XX++++++++++++++..............
|13 |(sensor_data_6)
......................................................XX++++++++++++++..........
|14 |(tristate_stateSBV_0)bpd(7)
..........................................................X+++++++++++++++......
|15 |(\sp_read:counter_address_1\)
................................................................XX++++++++++++++
________________________________________________________________________________

Total count of outputs placed        =  16 
Total count of unique Product Terms  =  34 
Total Product Terms to be assigned   =  34 
Max Product Terms used / available   =  34 /  80   = 42.51 %


Control Signals for Logic Block A
---------------------------------
CLK pin19: <not used>
CLK pin22: <not used>
CLK pin99: clk
CLK pin102: <not used>
CLK PT      : AH : <not used>
PRESET      : AH : <not used>
RESET       : AH : <not used>
OE 0        : AH : <not used>
OE 1        : AH : <not used>
OE 2        : AH : <not used>
OE 3        : AH : <not used>



                              Logic Block A
                 ____________________________________________
                 |   |= >S_8.CMB                        |   |                 
                 |   |> not used:263                    |   |                 
                 |   |= >S_10.CMB                       |   |                 
                 |   |= >\bp_io:bp_a..                  |   |                 
                 |   |= >S_3.CMB                        |143|= (\bp_io:bp_access_stateSBV_1\)bpd(0) 
                 |   |= >S_16.CMB                       |   |                 
                 |   |= >bpd(4)         (sensor_data_7) =|   |                 
                 |   |= >sensor_data..                  |   |                 
                 |   |= >bpd(1)                         |144|= (sensor_data_5)bpd(1) 
                 |   |= >S_15.CMB                       |   |                 
                 |   |= >sensor_data..  (sensor_data_2) =|   |                 
                 |   |= >S_5.CMB                        |   |                 
                 |   |= >S_4.CMB                        |145|= (\sp_read:counter_address_7\)bpd(2) 
                 |   |= >this_chip_s..                  |   |                 
                 |   |= >bpd(7)         (\sp_read:counter_address_5\) =|   |                 
                 |   |= >bpd(3)                         |   |                 
                 |   |= >S_6.CMB                        |146|= (\sp_read:counter_address_3\)bpd(3) 
                 |   |= >\bp_io:time..                  |   |                 
                 |   |= >sensor_data..  (\sp_read:counter_address_2\) =|   |                 
                 |   |> not used:281                    |   |                 
                 |   |= >sensor_data..                  |147|= (\sp_read:counter_address_4\)bpd(4) 
                 |   |= >bpd(5)                         |   |                 
                 |   |= >sensor_data..  (\sp_read:counter_address_6\) =|   |                 
                 |   |= >sensor_data..                  |   |                 
                 |   |= >sensor_data..                  |148|= (sensor_data_1)bpd(5) 
                 |   |= >bpd(2)                         |   |                 
                 |   |= >S_12.CMB       (sensor_data_3) =|   |                 
                 |   |= >S_7.CMB                        |   |                 
                 |   |= >sensor_to_b..                  |149|= (sensor_data_4)bpd(6) 
                 |   |= >S_14.CMB                       |   |                 
                 |   |= >S_13.CMB       (sensor_data_6) =|   |                 
                 |   |> not used:293                    |   |                 
                 |   |= >\bp_io:bp_a..                  |150|= (tristate_stateSBV_0)bpd(7) 
                 |   |= >\bp_io:time..                  |   |                 
                 |   |= >S_11.CMB       (\sp_read:counter_address_1\) =|   |                 
                 |   |= >\bp_io:bp_a..                  |   |                 
                 |   |= >bpd(6)                         |   |                 
                 |   |= >S_9.CMB                        |   |                 
                 |   |= >\bp_io:time..                  |   |                 
                 ____________________________________________


  Information: Macrocell Utilization.

                     Description        Used     Max
                 ______________________________________
                 | I/O Macrocells     |    8  |    8  |
                 | Buried Macrocells  |    8  |    8  |
                 | PIM Input Connects |   36  |   36  |
                 ______________________________________
                                          52  /   52   = 100 %


----------------------------------------------------------------------------
PLD Compiler Software:        C37KFIT.EXE    22/DEC/2000  [v4.02 ] 6.2 IR 27

LOGIC BLOCK B PLACEMENT   (20:13:21)

Messages:


________________________________________________________________________________
          1111111111222222222233333333334444444444555555555566666666667777777777
01234567890123456789012345678901234567890123456789012345678901234567890123456789
________________________________________________________________________________
| 0 |[i/p]
++++++++++++++++................................................................
| 1 |UNUSED
......++++++++++++++++..........................................................
| 2 |[i/p]
..........++++++++++++++++......................................................
| 3 |(sensor_data_11)
..............XX++++++++++++++..................................................
| 4>|bpd(10)
..................XX++++++++++++++..............................................
| 5 |(sensor_data_12)
......................XX++++++++++++++..........................................
| 6>|bpd(11)
..........................XX++++++++++++++......................................
| 7 |(sensor_data_13)
..............................XX++++++++++++++..................................
| 8>|bpd(12)
..................................XX++++++++++++++..............................
| 9 |(sensor_data_14)
......................................XX++++++++++++++..........................
|10>|bpd(13)
..........................................XX++++++++++++++......................
|11 |(sensor_to_bp_read_ack)
..............................................XX++++++++++++++..................
|12>|bpd(14)
..................................................XX++++++++++++++..............
|13 |UNUSED
......................................................++++++++++++++++..........
|14>|bpd(15)
..........................................................XX++++++++++++++......
|15 |UNUSED
................................................................++++++++++++++++
________________________________________________________________________________

Total count of outputs placed        =  11 
Total count of unique Product Terms  =  22 
Total Product Terms to be assigned   =  22 
Max Product Terms used / available   =  22 /  80   = 27.51 %


Control Signals for Logic Block B
---------------------------------
CLK pin19: <not used>
CLK pin22: <not used>
CLK pin99: clk
CLK pin102: <not used>
CLK PT      : AH : <not used>
PRESET      : AH : <not used>
RESET       : AH : <not used>
OE 0        : AH : bpctrl(0).Q 
OE 1        : AH : bpctrl(0).Q 
OE 2        : AH : bpctrl(0).Q 
OE 3        : AH : bpctrl(0).Q 



                              Logic Block B
                 ____________________________________________
                 |   |= >bpd(14).Q                      |   |                 
                 |   |= >bpd(10).Q                      |   |                 
                 |   |= >ao_from_pc_..                  |   |                 
                 |   |= >d(1)                           |   |                 
                 |   |= >bpd(11).Q                      |152|= bpd(8)         
                 |   |= >bpd(11)                        |   |                 
                 |   |= >\bp_io:time..    not used:903 >|   |                 
                 |   |= >\ibus_reade..                  |   |                 
                 |   |= >bpd(12)                        |153|= bpd(9)         
                 |   |= >\bp_io:time..                  |   |                 
                 |   |= >bpd(13).Q      (sensor_data_11) =|   |                 
                 |   |= >bpctrl(0).Q                    |   |                 
                 |   |= >d(0)                           |154|= bpd(10)        
                 |   |= >d(4)                           |   |                 
                 |   |= >\bp_io:bp_a..  (sensor_data_12) =|   |                 
                 |   |= >\ibus_reade..                  |   |                 
                 |   |= >d(5)                           |155|= bpd(11)        
                 |   |= >\bp_io:time..                  |   |                 
                 |   |> not used:319    (sensor_data_13) =|   |                 
                 |   |= >sensor_data..                  |   |                 
                 |   |= >d(2)                           |156|= bpd(12)        
                 |   |= >bpd(13)                        |   |                 
                 |   |> not used:323    (sensor_data_14) =|   |                 
                 |   |= >bpd(14)                        |   |                 
                 |   |= >d(3)                           |157|= bpd(13)        
                 |   |= >\ibus_reade..                  |   |                 
                 |   |= >sensor_data..  (sensor_to_bp_read_ack) =|   |                 
                 |   |= >bpd(12).Q                      |   |                 
                 |   |> not used:329                    |158|= bpd(14)        
                 |   |= >\bp_io:bp_a..                  |   |                 
                 |   |> not used:331      not used:915 >|   |                 
                 |   |> not used:332                    |   |                 
                 |   |= >\bp_io:bp_a..                  |159|= bpd(15)        
                 |   |> not used:334                    |   |                 
                 |   |= >sensor_data..    not used:917 >|   |                 
                 |   |= >bpd(15).Q                      |   |                 
                 |   |= >sensor_data..                  |   |                 
                 |   |> not used:338                    |   |                 
                 |   |> not used:339                    |   |                 
                 ____________________________________________


  Information: Macrocell Utilization.

                     Description        Used     Max
                 ______________________________________
                 | I/O Macrocells     |    8  |    8  |
                 | Buried Macrocells  |    5  |    8  |
                 | PIM Input Connects |   31  |   36  |
                 ______________________________________
                                          44  /   52   = 84  %


----------------------------------------------------------------------------
PLD Compiler Software:        C37KFIT.EXE    22/DEC/2000  [v4.02 ] 6.2 IR 27

LOGIC BLOCK C PLACEMENT   (20:13:21)

Messages:


________________________________________________________________________________
          1111111111222222222233333333334444444444555555555566666666667777777777
01234567890123456789012345678901234567890123456789012345678901234567890123456789
________________________________________________________________________________
| 0 |(sensor_data_15)
XX++++++++++++++................................................................
| 1 |(\sp_read:reset_count_2\)
......XXX+++++++++++++..........................................................
| 2>|bpctrl_h_tristate
..........++++++++X+++++++......................................................
| 3 |(\ibus_writer:timeout_1\)
..............XXXX+XXXXX++++++..................................................
| 4>|bpd_l_tristate
..................X+++++++++++++++..............................................
| 5 |(S_16)
......................++XX++XX++XX++XX..........................................
| 6>|bpctrl_l_dir
..........................X+++++++++++++++......................................
| 7 |(\sp_read:counter_read_stateSBV_0\)
..............................XX++++++++XXXX++..................................
| 8 |(sensor_address_1)
..................................XX++XX++++++++++..............................
| 9 |(sensor_address_0)
......................................++++++XXXX++++++..........................
|10>|bpctrl_l_tristate
..........................................++++++++X+++++++......................
|11 |(\sp_read:counter_read_stateSBV_3\)
..............................................++XX+XXXXXXXXXXX..................
|12>|bpctrl_h_dir
..................................................X+++++++++++++++..............
|13 |(sensor_address_5)
......................................................+++++++++XXXX+++..........
|14>|bpd_l_dir
..........................................................++++X+++++++++++......
|15 |(sensor_address_4)
................................................................++++XX++++++++++
________________________________________________________________________________

Total count of outputs placed        =  16 
Total count of unique Product Terms  =  58 
Total Product Terms to be assigned   =  61 
Max Product Terms used / available   =  59 /  80   = 73.76 %


Control Signals for Logic Block C
---------------------------------
CLK pin19: <not used>
CLK pin22: <not used>
CLK pin99: clk
CLK pin102: <not used>
CLK PT      : AH : <not used>
PRESET      : AH : <not used>
RESET       : AH : <not used>
OE 0        : AH : <not used>
OE 1        : AH : <not used>
OE 2        : AH : <not used>
OE 3        : AH : <not used>



                              Logic Block C
                 ____________________________________________
                 |   |= >\ibus_write..                  |   |                 
                 |   |= >\sp_read:co..                  |   |                 
                 |   |= >\sp_read:co..                  |   |                 
                 |   |= >sensor_to_i..                  |   |                 
                 |   |= >\sp_read:cm..                  |  2|= (sensor_data_15) 
                 |   |= >ao_to_pc_ack                   |   |                 
                 |   |= >sinphase_ze..  (\sp_read:reset_count_2\) =|   |                 
                 |   |= >bpd_h_trist..                  |   |                 
                 |   |= >\sp_read:co..                  |  3|= bpctrl_h_tristate 
                 |   |= >sensor_addr..                  |   |                 
                 |   |= >\sp_read:re..  (\ibus_writer:timeout_1\) =|   |                 
                 |   |= >sensor_addr..                  |   |                 
                 |   |= >to_pc_ack.Q                    |  4|= bpd_l_tristate 
                 |   |= >\sp_read:co..                  |   |                 
                 |   |> not used:354            (S_16) =|   |                 
                 |   |= >\sp_read:co..                  |   |                 
                 |   |> not used:356                    |  5|= bpctrl_l_dir   
                 |   |= >\sp_read:co..                  |   |                 
                 |   |= >\sp_read:co..  (\sp_read:counter_read_stateSBV_0\) =|   |                 
                 |   |= >bp_start_ad..                  |   |                 
                 |   |= >\ibus_write..                  |  6|= (sensor_address_1) 
                 |   |= >bp_end_addr..                  |   |                 
                 |   |= >\sp_read:co..  (sensor_address_0) =|   |                 
                 |   |= >loopback_st..                  |   |                 
                 |   |= >sensor_addr..                  |  7|= bpctrl_l_tristate 
                 |   |= >\sp_read:re..                  |   |                 
                 |   |= >sensor_data..  (\sp_read:counter_read_stateSBV_3\) =|   |                 
                 |   |= >\ibus_write..                  |   |                 
                 |   |= >\ibus_write..                  |  8|= bpctrl_h_dir   
                 |   |= >\sp_read:ol..                  |   |                 
                 |   |= >\ibus_write..  (sensor_address_5) =|   |                 
                 |   |> not used:371                    |   |                 
                 |   |= >sensor_to_b..                  |  9|= bpd_l_dir      
                 |   |= >from_pc_req.Q                  |   |                 
                 |   |= >\ibus_write..  (sensor_address_4) =|   |                 
                 |   |= >sensor_addr..                  |   |                 
                 |   |= >\sp_read:re..                  |   |                 
                 |   |= >\sp_read:co..                  |   |                 
                 |   |= >bpctrl(0).Q                    |   |                 
                 ____________________________________________


  Information: Macrocell Utilization.

                     Description        Used     Max
                 ______________________________________
                 | I/O Macrocells     |    8  |    8  |
                 | Buried Macrocells  |    8  |    8  |
                 | PIM Input Connects |   36  |   36  |
                 ______________________________________
                                          52  /   52   = 100 %


----------------------------------------------------------------------------
PLD Compiler Software:        C37KFIT.EXE    22/DEC/2000  [v4.02 ] 6.2 IR 27

LOGIC BLOCK D PLACEMENT   (20:13:21)

Messages:


________________________________________________________________________________
          1111111111222222222233333333334444444444555555555566666666667777777777
01234567890123456789012345678901234567890123456789012345678901234567890123456789
________________________________________________________________________________
| 0>|bpctrl(0)
XXX+++++++++++++................................................................
| 1 |UNUSED
......++++++++++++++++..........................................................
| 2>|bpctrl(1)
..........X+++++++++++++++......................................................
| 3 |(sensor_data_0)
..............XX++++++++++++++..................................................
| 4>|bpctrl(2)
..................XX++++++++++++++..............................................
| 5 |(sensor_data_10)
......................XX++++++++++++++..........................................
| 6>|bpctrl(3)
..........................X+++++++++++++++......................................
| 7 |(sensor_data_8)
..............................XX++++++++++++++..................................
| 8>|bpctrl(4)
..................................XX++++++++++++++..............................
| 9 |(sensor_data_9)
......................................XX++++++++++++++..........................
|10>|bpctrl(5)
..........................................XX++++++++++++++......................
|11 |UNUSED
..............................................++++++++++++++++..................
|12>|bpctrl(6)
..................................................XX++++++++++++++..............
|13 |UNUSED
......................................................++++++++++++++++..........
|14>|bpctrl(7)
..........................................................XX++++++++++++++......
|15 |UNUSED
................................................................++++++++++++++++
________________________________________________________________________________

Total count of outputs placed        =  12 
Total count of unique Product Terms  =  23 
Total Product Terms to be assigned   =  23 
Max Product Terms used / available   =  23 /  80   = 28.76 %


Control Signals for Logic Block D
---------------------------------
CLK pin19: <not used>
CLK pin22: <not used>
CLK pin99: clk
CLK pin102: <not used>
CLK PT      : AH : <not used>
PRESET      : AH : <not used>
RESET       : AH : <not used>
OE 0        : AH : bpctrl(0).Q 
OE 1        : AH : <not used>
OE 2        : AH : bpctrl(0).Q 
OE 3        : AH : <not used>



                              Logic Block D
                 ____________________________________________
                 |   |= >loopback_st..                  |   |                 
                 |   |= >d(8)                           |   |                 
                 |   |= >ao_from_pc_..                  |   |                 
                 |   |= >\bp_io:bp_a..                  |   |                 
                 |   |= >bpd(0)                         | 11|= bpctrl(0)      
                 |   |= >bpctrl(6).Q                    |   |                 
                 |   |= >sinphase_ze..    not used:935 >|   |                 
                 |   |= >d(6)                           |   |                 
                 |   |= >sensor_data..                  | 12|= bpctrl(1)      
                 |   |= >bpctrl(7).Q                    |   |                 
                 |   |= >d(7)           (sensor_data_0) =|   |                 
                 |   |= >bpctrl(0).Q                    |   |                 
                 |   |= >bpctrl(4).Q                    | 13|= bpctrl(2)      
                 |   |= >\bp_io:time..                  |   |                 
                 |   |= >\bp_io:bp_a..  (sensor_data_10) =|   |                 
                 |   |= >\ibus_reade..                  |   |                 
                 |   |= >d(9)                           | 14|= bpctrl(3)      
                 |   |= >\bp_io:time..                  |   |                 
                 |   |= >bpd(8)         (sensor_data_8) =|   |                 
                 |   |= >sensor_data..                  |   |                 
                 |   |= >bpctrl(5).Q                    | 15|= bpctrl(4)      
                 |   |= >\sp_read:co..                  |   |                 
                 |   |= >bpd(9)         (sensor_data_9) =|   |                 
                 |   |= >sensor_data..                  |   |                 
                 |   |= >\bp_io:bp_a..                  | 16|= bpctrl(5)      
                 |   |= >bpd(10)                        |   |                 
                 |   |> not used:405      not used:945 >|   |                 
                 |   |> not used:406                    |   |                 
                 |   |> not used:407                    | 17|= bpctrl(6)      
                 |   |> not used:408                    |   |                 
                 |   |> not used:409      not used:947 >|   |                 
                 |   |> not used:410                    |   |                 
                 |   |> not used:411                    | 18|= bpctrl(7)      
                 |   |= >from_pc_req.Q                  |   |                 
                 |   |= >\ibus_reade..    not used:949 >|   |                 
                 |   |= >\ibus_reade..                  |   |                 
                 |   |= >sensor_data..                  |   |                 
                 |   |= >\sp_read:co..                  |   |                 
                 |   |= >\bp_io:time..                  |   |                 
                 ____________________________________________


  Information: Macrocell Utilization.

                     Description        Used     Max
                 ______________________________________
                 | I/O Macrocells     |    8  |    8  |
                 | Buried Macrocells  |    4  |    8  |
                 | PIM Input Connects |   32  |   36  |
                 ______________________________________
                                          44  /   52   = 84  %


----------------------------------------------------------------------------
PLD Compiler Software:        C37KFIT.EXE    22/DEC/2000  [v4.02 ] 6.2 IR 27

LOGIC BLOCK E PLACEMENT   (20:13:21)

Messages:


________________________________________________________________________________
          1111111111222222222233333333334444444444555555555566666666667777777777
01234567890123456789012345678901234567890123456789012345678901234567890123456789
________________________________________________________________________________
| 0>|bpctrl(8)
XX++++++++++++++................................................................
| 1 |(bp_start_address_6)
......XX++++++++++++++..........................................................
| 2 |(bp_start_address_4)
..........XX++++++++++++++......................................................
| 3 |(address_from_pc_1)
..............XX++++++++++++++..................................................
| 4>|bpctrl(10)
..................XX++++++++++++++..............................................
| 5 |(bp_end_address_2)
......................XX++++++++++++++..........................................
| 6>|bpctrl(11)
..........................XX++++++++++++++......................................
| 7 |(bp_end_address_4)
..............................XX++++++++++++++..................................
| 8 |(bp_end_address_5)
..................................XX++++++++++++++..............................
| 9 |(bp_end_address_6)
......................................XX++++++++++++++..........................
|10 |(bp_start_address_1)
..........................................XX++++++++++++++......................
|11 |(bp_start_address_2)
..............................................XX++++++++++++++..................
|12 |(bp_start_address_3)
..................................................XX++++++++++++++..............
|13 |(bp_start_address_5)
......................................................XX++++++++++++++..........
|14 |(data_from_pc_13)
..........................................................XX++++++++++++++......
|15 |(data_from_pc_14)
................................................................XX++++++++++++++
________________________________________________________________________________

Total count of outputs placed        =  16 
Total count of unique Product Terms  =  32 
Total Product Terms to be assigned   =  32 
Max Product Terms used / available   =  32 /  80   = 40.1  %


Control Signals for Logic Block E
---------------------------------
CLK pin19: <not used>
CLK pin22: <not used>
CLK pin99: clk
CLK pin102: <not used>
CLK PT      : AH : <not used>
PRESET      : AH : GND
RESET       : AH : reset.CMB 
OE 0        : AH : bpctrl(0).Q 
OE 1        : AH : <not used>
OE 2        : AH : bpctrl(0).Q 
OE 3        : AH : <not used>



                              Logic Block E
                 ____________________________________________
                 |   |= >d(11)                          |   |                 
                 |   |= >bp_start_ad..                  |   |                 
                 |   |= >bp_end_addr..                  |   |                 
                 |   |= >reset.CMB                      |   |                 
                 |   |= >bpd(15).Q                      | 23|= bpctrl(8)      
                 |   |= >data_from_p..                  |   |                 
                 |   |= >bp_start_ad..  (bp_start_address_6) =|   |                 
                 |   |= >\ibus_reade..                  |   |                 
                 |   |= >bp_start_ad..                  | 24|= (bp_start_address_4) 
                 |   |= >bp_end_addr..                  |   |                 
                 |   |= >bpd(13).Q      (address_from_pc_1) =|   |                 
                 |   |= >bpctrl(0).Q                    |   |                 
                 |   |= >d(14)                          | 25|= bpctrl(10)     
                 |   |= >data_from_p..                  |   |                 
                 |   |= >bpctrl(11).Q   (bp_end_address_2) =|   |                 
                 |   |= >data_from_p..                  |   |                 
                 |   |= >bp_end_addr..                  | 26|= bpctrl(11)     
                 |   |= >bpctrl(8).Q                    |   |                 
                 |   |= >bpctrl(4).Q    (bp_end_address_4) =|   |                 
                 |   |= >d(13)                          |   |                 
                 |   |= >bp_start_ad..                  | 27|= (bp_end_address_5) 
                 |   |= >bp_start_ad..                  |   |                 
                 |   |= >bpd(14).Q      (bp_end_address_6) =|   |                 
                 |   |= >address_fro..                  |   |                 
                 |   |= >bpctrl(10).Q                   | 28|= (bp_start_address_1) 
                 |   |= >\ibus_reade..                  |   |                 
                 |   |= >address_fro..  (bp_start_address_2) =|   |                 
                 |   |= >bpd(12).Q                      |   |                 
                 |   |> not used:446                    | 29|= (bp_start_address_3) 
                 |   |> not used:447                    |   |                 
                 |   |= >ao_from_pc_..  (bp_start_address_5) =|   |                 
                 |   |= >d(10)                          |   |                 
                 |   |= >bpctrl(7).Q                    | 30|= (data_from_pc_13) 
                 |   |= >bp_end_addr..                  |   |                 
                 |   |= >\ibus_reade..  (data_from_pc_14) =|   |                 
                 |   |= >bp_start_ad..                  |   |                 
                 |   |= >d(12)                          |   |                 
                 |   |= >bpd(11).Q                      |   |                 
                 |   |> not used:456                    |   |                 
                 ____________________________________________


  Information: Macrocell Utilization.

                     Description        Used     Max
                 ______________________________________
                 | I/O Macrocells     |    8  |    8  |
                 | Buried Macrocells  |    8  |    8  |
                 | PIM Input Connects |   36  |   36  |
                 ______________________________________
                                          52  /   52   = 100 %


----------------------------------------------------------------------------
PLD Compiler Software:        C37KFIT.EXE    22/DEC/2000  [v4.02 ] 6.2 IR 27

LOGIC BLOCK F PLACEMENT   (20:13:21)

Messages:


________________________________________________________________________________
          1111111111222222222233333333334444444444555555555566666666667777777777
01234567890123456789012345678901234567890123456789012345678901234567890123456789
________________________________________________________________________________
| 0>|bpaddr(0)
XXXXXX++++++++++................................................................
| 1 |UNUSED
......++++++++++++++++..........................................................
| 2>|bpaddr(1)
..........XXXXXX++++++++++......................................................
| 3 |(\sp_read:counter_address_0\)
..............++XX++++++++++++..................................................
| 4>|bpaddr(2)
..................XXXXXX++++++++++..............................................
| 5 |UNUSED
......................++++++++++++++++..........................................
| 6>|bpaddr(3)
..........................XXXXXX++++++++++......................................
| 7 |UNUSED
..............................++++++++++++++++..................................
| 8>|bpaddr(4)
..................................XXXXXX++++++++++..............................
| 9 |UNUSED
......................................++++++++++++++++..........................
|10>|bpaddr(5)
..........................................XXXXXX++++++++++......................
|11 |UNUSED
..............................................++++++++++++++++..................
|12>|bpaddr(6)
..................................................XXXXXX++++++++++..............
|13 |UNUSED
......................................................++++++++++++++++..........
|14>|bpaddr(7)
..........................................................XXXXXX++++++++++......
|15 |UNUSED
................................................................++++++++++++++++
________________________________________________________________________________

Total count of outputs placed        =  9 
Total count of unique Product Terms  =  50 
Total Product Terms to be assigned   =  50 
Max Product Terms used / available   =  50 /  80   = 62.51 %


Control Signals for Logic Block F
---------------------------------
CLK pin19: <not used>
CLK pin22: <not used>
CLK pin99: clk
CLK pin102: <not used>
CLK PT      : AH : <not used>
PRESET      : AH : <not used>
RESET       : AH : <not used>
OE 0        : AH : <not used>
OE 1        : AH : <not used>
OE 2        : AH : <not used>
OE 3        : AH : <not used>



                              Logic Block F
                 ____________________________________________
                 |   |= >S_17.CMB                       |   |                 
                 |   |= >bpaddr(0).Q                    |   |                 
                 |   |= >address_fro..                  |   |                 
                 |   |= >\bp_io:bp_a..                  |   |                 
                 |   |= >sensor_addr..                  | 32|= bpaddr(0)      
                 |   |= >bpaddr(1).Q                    |   |                 
                 |   |= >\bp_io:bp_a..    not used:967 >|   |                 
                 |   |> not used:464                    |   |                 
                 |   |= >bpaddr(6).Q                    | 33|= bpaddr(1)      
                 |   |= >bpaddr(2).Q                    |   |                 
                 |   |> not used:467    (\sp_read:counter_address_0\) =|   |                 
                 |   |= >sensor_addr..                  |   |                 
                 |   |= >bpaddr(3).Q                    | 34|= bpaddr(2)      
                 |   |= >bpaddr(7).Q                    |   |                 
                 |   |= >address_fro..    not used:971 >|   |                 
                 |   |= >sensor_addr..                  |   |                 
                 |   |= >sensor_to_b..                  | 35|= bpaddr(3)      
                 |   |= >sensor_addr..                  |   |                 
                 |   |= >sensor_addr..    not used:973 >|   |                 
                 |   |= >bpaddr(5).Q                    |   |                 
                 |   |> not used:477                    | 36|= bpaddr(4)      
                 |   |= >sensor_addr..                  |   |                 
                 |   |= >address_fro..    not used:975 >|   |                 
                 |   |= >loopback_st..                  |   |                 
                 |   |= >\bp_io:bp_a..                  | 37|= bpaddr(5)      
                 |   |> not used:482                    |   |                 
                 |   |= >address_fro..    not used:977 >|   |                 
                 |   |= >address_fro..                  |   |                 
                 |   |> not used:485                    | 38|= bpaddr(6)      
                 |   |= >address_fro..                  |   |                 
                 |   |= >bpaddr(4).Q      not used:979 >|   |                 
                 |   |= >sensor_addr..                  |   |                 
                 |   |= >sensor_addr..                  | 39|= bpaddr(7)      
                 |   |= >from_pc_req.Q                  |   |                 
                 |   |> not used:491      not used:981 >|   |                 
                 |   |= >address_fro..                  |   |                 
                 |   |= >address_fro..                  |   |                 
                 |   |> not used:494                    |   |                 
                 |   |= >S_18.CMB                       |   |                 
                 ____________________________________________


  Information: Macrocell Utilization.

                     Description        Used     Max
                 ______________________________________
                 | I/O Macrocells     |    8  |    8  |
                 | Buried Macrocells  |    1  |    8  |
                 | PIM Input Connects |   32  |   36  |
                 ______________________________________
                                          41  /   52   = 78  %


----------------------------------------------------------------------------
PLD Compiler Software:        C37KFIT.EXE    22/DEC/2000  [v4.02 ] 6.2 IR 27

LOGIC BLOCK G PLACEMENT   (20:13:21)

Messages:


________________________________________________________________________________
          1111111111222222222233333333334444444444555555555566666666667777777777
01234567890123456789012345678901234567890123456789012345678901234567890123456789
________________________________________________________________________________
| 0>|bpd_h_dir
++X+++++++++++++................................................................
| 1 |(sensor_address_7)
......XXXX++++++++++++..........................................................
| 2>|bpd_h_tristate
..........XXXX++++X+++++++......................................................
| 3 |(\sp_read:counter_read_stateSBV_1\)
..............XXXX++XXXXXX++++..................................................
| 4>|bpaddr_tristate
..................XX++++++++++++++..............................................
| 5 |UNUSED
......................++++++++++++++++..........................................
| 6>|bpaddr_dir
..........................X+++++++++++++++......................................
| 7 |(sensor_to_ibus_req)
..............................XX+++X++++++++++..................................
| 8 |(sensor_to_bp_read_req)
..................................X+++++++++++++++..............................
| 9 |UNUSED
......................................++++++++++++++++..........................
|10>|led1
..........................................XX+++++++X++++++......................
|11 |(sensor_address_6)
..............................................XXXX++++++++++++..................
|12>|led2
..................................................X+++++++++++++++..............
|13 |(S_2)
......................................................XXXX+XXXXXXXXXXX..........
|14>|led3
..........................................................X+++++++++++++++......
|15 |UNUSED
................................................................++++++++++++++++
________________________________________________________________________________

Total count of outputs placed        =  13 
Total count of unique Product Terms  =  46 
Total Product Terms to be assigned   =  51 
Max Product Terms used / available   =  50 /  80   = 62.51 %


Control Signals for Logic Block G
---------------------------------
CLK pin19: <not used>
CLK pin22: <not used>
CLK pin99: clk
CLK pin102: <not used>
CLK PT      : AH : <not used>
PRESET      : AH : <not used>
RESET       : AH : <not used>
OE 0        : AH : <not used>
OE 1        : AH : <not used>
OE 2        : AH : <not used>
OE 3        : AH : <not used>



                              Logic Block G
                 ____________________________________________
                 |   |= >\sp_read:de..                  |   |                 
                 |   |= >\sp_read:co..                  |   |                 
                 |   |= >\sp_read:de..                  |   |                 
                 |   |= >\bp_io:bp_a..                  |   |                 
                 |   |= >\sp_read:co..                  | 42|= bpd_h_dir      
                 |   |= >\sp_read:co..                  |   |                 
                 |   |= >\sp_read:de..  (sensor_address_7) =|   |                 
                 |   |= >\sp_read:co..                  |   |                 
                 |   |= >\sp_read:co..                  | 43|= bpd_h_tristate 
                 |   |= >\sp_read:de..                  |   |                 
                 |   |= >\sp_read:co..  (\sp_read:counter_read_stateSBV_1\) =|   |                 
                 |   |= >\sp_read:co..                  |   |                 
                 |   |= >to_pc_ack.Q                    | 44|= bpaddr_tristate 
                 |   |= >\sp_read:cm..                  |   |                 
                 |   |= >\sp_read:de..    not used:987 >|   |                 
                 |   |= >\sp_read:de..                  |   |                 
                 |   |= >\sp_read:co..                  | 45|= bpaddr_dir     
                 |   |> not used:513                    |   |                 
                 |   |= >bpctrl(0).Q    (sensor_to_ibus_req) =|   |                 
                 |   |= >\sp_read:co..                  |   |                 
                 |   |= >\sp_read:de..                  | 46|= (sensor_to_bp_read_req) 
                 |   |= >\sp_read:co..                  |   |                 
                 |   |= >\sp_read:co..    not used:991 >|   |                 
                 |   |= >loopback_st..                  |   |                 
                 |   |= >from_pc_req.Q                  | 47|= led1           
                 |   |= >fast                           |   |                 
                 |   |= >\sp_read:co..  (sensor_address_6) =|   |                 
                 |   |> not used:523                    |   |                 
                 |   |= >sensor_to_b..                  | 48|= led2           
                 |   |= >\bp_io:bp_a..                  |   |                 
                 |   |> not used:526             (S_2) =|   |                 
                 |   |= >sensor_addr..                  |   |                 
                 |   |= >sensor_to_b..                  | 49|= led3           
                 |   |= >sensor_addr..                  |   |                 
                 |   |= >\sp_read:de..    not used:997 >|   |                 
                 |   |= >\bp_io:bp_a..                  |   |                 
                 |   |= >\sp_read:de..                  |   |                 
                 |   |= >\sp_read:de..                  |   |                 
                 |   |= >slow                           |   |                 
                 ____________________________________________


  Information: Macrocell Utilization.

                     Description        Used     Max
                 ______________________________________
                 | I/O Macrocells     |    8  |    8  |
                 | Buried Macrocells  |    5  |    8  |
                 | PIM Input Connects |   36  |   36  |
                 ______________________________________
                                          49  /   52   = 94  %


----------------------------------------------------------------------------
PLD Compiler Software:        C37KFIT.EXE    22/DEC/2000  [v4.02 ] 6.2 IR 27

LOGIC BLOCK H PLACEMENT   (20:13:21)

Messages:


________________________________________________________________________________
          1111111111222222222233333333334444444444555555555566666666667777777777
01234567890123456789012345678901234567890123456789012345678901234567890123456789
________________________________________________________________________________
| 0 |(\ibus_reader:timeout_0\)
XXXXXXXXXXXXXXX+................................................................
| 1 |(loopback_state)
......+++++++++X++++++..........................................................
| 2 |(\ibus_reader:il_read_stateSBV_0\)
..........++++++XXXXXXXXXX......................................................
| 3 |(address_from_pc_5)
..............++++++++++++++XX..................................................
| 4 |(address_from_pc_3)
..................++++++++XX++++++..............................................
| 5 |UNUSED
......................++++++++++++++++..........................................
| 6 |(address_from_pc_2)
..........................++++++XX++++++++......................................
| 7 |(\ibus_reader:timeout_3\)
..............................XX++XXXXXXXX++XX..................................
| 8 |(sensor_address_2)
..................................++++++++XX++++XX..............................
| 9 |(S_20)
......................................++++++++XX++X+++..........................
|10 |(from_pc_req)
..........................................+++++++++X++XX++......................
|11 |(address_from_pc_4)
..............................................++++++++++XX++++..................
|12 |(address_from_pc_6)
..................................................++XX++++++++++++..............
|13 |UNUSED
......................................................++++++++++++++++..........
|14 |UNUSED
..........................................................++++++++++++++++......
|15 |(\ibus_reader:timeout_2\)
................................................................XXXXXXXXXXXXXXX+
________________________________________________________________________________

Total count of outputs placed        =  13 
Total count of unique Product Terms  =  73 
Total Product Terms to be assigned   =  73 
Max Product Terms used / available   =  73 /  80   = 91.26 %


Control Signals for Logic Block H
---------------------------------
CLK pin19: <not used>
CLK pin22: <not used>
CLK pin99: clk
CLK pin102: <not used>
CLK PT      : AH : <not used>
PRESET      : AH : GND
RESET       : AH : reset.CMB 
OE 0        : AH : <not used>
OE 1        : AH : <not used>
OE 2        : AH : <not used>
OE 3        : AH : <not used>



                              Logic Block H
                 ____________________________________________
                 |   |= >bpd(14).Q                      |   |                 
                 |   |= >\sp_read:co..                  |   |                 
                 |   |= >\ibus_reade..                  |   |                 
                 |   |= >reset.CMB                      |   |                 
                 |   |= >\sp_read:co..                  | 51|= (\ibus_reader:timeout_0\) 
                 |   |= >\sp_read:co..                  |   |                 
                 |   |= >address_fro..  (loopback_state) =|   |                 
                 |   |= >bpctrl(10).Q                   |   |                 
                 |   |= >\ibus_reade..                  | 52|= (\ibus_reader:il_read_stateSBV_0\) 
                 |   |= >\sp_read:co..                  |   |                 
                 |   |= >\sp_read:co..  (address_from_pc_5) =|   |                 
                 |   |= >\ibus_reade..                  |   |                 
                 |   |= >write_to_bp..                  | 53|= (address_from_pc_3) 
                 |   |= >bpd(15).Q                      |   |                 
                 |   |= >bpctrl(7).Q     not used:1003 >|   |                 
                 |   |= >\ibus_reade..                  |   |                 
                 |   |= >\sp_read:co..                  | 54|= (address_from_pc_2) 
                 |   |= >bpctrl(8).Q                    |   |                 
                 |   |= >bpctrl(4).Q    (\ibus_reader:timeout_3\) =|   |                 
                 |   |= >address_fro..                  |   |                 
                 |   |= >bpd(13).Q                      | 55|= (sensor_address_2) 
                 |   |= >\ibus_reade..                  |   |                 
                 |   |= >sensor_addr..          (S_20) =|   |                 
                 |   |= >loopback_st..                  |   |                 
                 |   |> not used:559                    | 56|= (from_pc_req)  
                 |   |= >\ibus_reade..                  |   |                 
                 |   |= >\sp_read:co..  (address_from_pc_4) =|   |                 
                 |   |= >bpd(12).Q                      |   |                 
                 |   |= >to_pc_ack.Q                    | 57|= (address_from_pc_6) 
                 |   |= >\ibus_reade..                  |   |                 
                 |   |= >ao_from_pc_..   not used:1011 >|   |                 
                 |   |= >bpctrl(11).Q                   |   |                 
                 |   |= >data_from_p..                  | 58|* not used       
                 |   |> not used:568                    |   |                 
                 |   |= >\ibus_reade..  (\ibus_reader:timeout_2\) =|   |                 
                 |   |= >address_fro..                  |   |                 
                 |   |= >address_fro..                  |   |                 
                 |   |= >address_fro..                  |   |                 
                 |   |> not used:573                    |   |                 
                 ____________________________________________


  Information: Macrocell Utilization.

                     Description        Used     Max
                 ______________________________________
                 | I/O Macrocells     |    7  |    8  |
                 | Buried Macrocells  |    6  |    8  |
                 | PIM Input Connects |   36  |   36  |
                 ______________________________________
                                          49  /   52   = 94  %


----------------------------------------------------------------------------
PLD Compiler Software:        C37KFIT.EXE    22/DEC/2000  [v4.02 ] 6.2 IR 27

LOGIC BLOCK I PLACEMENT   (20:13:21)

Messages:


________________________________________________________________________________
          1111111111222222222233333333334444444444555555555566666666667777777777
01234567890123456789012345678901234567890123456789012345678901234567890123456789
________________________________________________________________________________
| 0 |(S_19)
XXXXXXXXXXXXXXXX................................................................
| 1 |(bp_start_address_7)
......++++++++++XX++++..........................................................
| 2 |(bp_end_address_7)
..........++++++++++XX++++......................................................
| 3 |(bp_end_address_0)
..............++++XX++++++++++..................................................
| 4 |(address_from_pc_0)
..................++++XX++++++++++..............................................
| 5 |(\ibus_reader:timeout_1\)
......................++XX++++++++++++..........................................
| 6 |(this_chip_selected)sinphase_zeros
..........................XXXXX+++++++++++......................................
| 7 |(\ibus_reader:il_read_stateSBV_1\)
..............................XXXXX+XX++XX++++..................................
| 8 |(\ibus_reader:this_is_a_ctrl_transaction\)
..................................+X++++++XX++XX++..............................
| 9 |(\sp_read:counter_read_stateSBV_2\)
......................................XX++++++++++++++..........................
|10 |(address_from_pc_7)
..........................................++XX++++++++++++......................
|11 |(bp_end_address_1)
..............................................++XX++++++++++++..................
|12 |(bp_end_address_3)
..................................................XX++++++++++++++..............
|13 |(bp_start_address_0)
......................................................XX++++++++++++++..........
|14 |(data_from_pc_15)
..........................................................XX++++++++++++++......
|15 |(\ibus_reader:il_read_stateSBV_2\)
................................................................XXXXXXXXXXXX++X+
________________________________________________________________________________

Total count of outputs placed        =  16 
Total count of unique Product Terms  =  68 
Total Product Terms to be assigned   =  70 
Max Product Terms used / available   =  69 /  80   = 86.26 %


Control Signals for Logic Block I
---------------------------------
CLK pin19: <not used>
CLK pin22: <not used>
CLK pin99: clk
CLK pin102: <not used>
CLK PT      : AH : <not used>
PRESET      : AH : GND
RESET       : AH : reset.CMB 
OE 0        : AH : <not used>
OE 1        : AH : <not used>
OE 2        : AH : <not used>
OE 3        : AH : <not used>



                              Logic Block I
                 ____________________________________________
                 |   |= >bp_end_addr..                  |   |                 
                 |   |= >S_20.CMB                       |   |                 
                 |   |= >address_fro..                  |   |                 
                 |   |= >bp_start_ad..                  |   |                 
                 |   |= >\ibus_reade..                  | 63|= (S_19)         
                 |   |= >S_19.CMB                       |   |                 
                 |   |> not used:580    (bp_start_address_7) =|   |                 
                 |   |= >bpctrl(10).Q                   |   |                 
                 |   |= >\ibus_reade..                  | 64|= (bp_end_address_7) 
                 |   |= >bp_end_addr..                  |   |                 
                 |   |= >bpctrl(11).Q   (bp_end_address_0) =|   |                 
                 |   |= >\ibus_reade..                  |   |                 
                 |   |= >S_2.CMB                        | 65|= (address_from_pc_0) 
                 |   |= >this_chip_s..                  |   |                 
                 |   |= >bpctrl(7).Q    (\ibus_reader:timeout_1\) =|   |                 
                 |   |= >S_1.CMB                        |   |                 
                 |   |= >ao_from_pc_..                  | 66|= (this_chip_selected)sinphase_zeros 
                 |   |= >bpctrl(8).Q                    |   |                 
                 |   |= >bp_start_ad..  (\ibus_reader:il_read_stateSBV_1\) =|   |                 
                 |   |= >address_fro..                  |   |                 
                 |   |= >bpctrl(5).Q                    | 67|= (\ibus_reader:this_is_a_ctrl_transaction\) 
                 |   |= >bp_end_addr..                  |   |                 
                 |   |= >address_fro..  (\sp_read:counter_read_stateSBV_2\) =|   |                 
                 |   |= >bpctrl(6).Q                    |   |                 
                 |   |= >bpd(10).Q                      | 68|= (address_from_pc_7) 
                 |   |= >d(15)                          |   |                 
                 |   |= >reset.CMB      (bp_end_address_1) =|   |                 
                 |   |= >bp_end_addr..                  |   |                 
                 |   |= >to_pc_ack.Q                    | 69|= (bp_end_address_3) 
                 |   |= >\ibus_reade..                  |   |                 
                 |   |= >write_to_bp..  (bp_start_address_0) =|   |                 
                 |   |= >\ibus_reade..                  |   |                 
                 |   |= >data_from_p..                  | 70|= (data_from_pc_15) 
                 |   |= >loopback_st..                  |   |                 
                 |   |= >reset.CMB      (\ibus_reader:il_read_stateSBV_2\) =|   |                 
                 |   |= >data_from_p..                  |   |                 
                 |   |= >\ibus_reade..                  |   |                 
                 |   |> not used:611                    |   |                 
                 |   |> not used:612                    |   |                 
                 ____________________________________________


  Information: Macrocell Utilization.

                     Description        Used     Max
                 ______________________________________
                 | I/O Macrocells     |    8  |    8  |
                 | Buried Macrocells  |    8  |    8  |
                 | PIM Input Connects |   36  |   36  |
                 ______________________________________
                                          52  /   52   = 100 %


----------------------------------------------------------------------------
PLD Compiler Software:        C37KFIT.EXE    22/DEC/2000  [v4.02 ] 6.2 IR 27

LOGIC BLOCK J PLACEMENT   (20:13:21)

Messages:


________________________________________________________________________________
          1111111111222222222233333333334444444444555555555566666666667777777777
01234567890123456789012345678901234567890123456789012345678901234567890123456789
________________________________________________________________________________
| 0 |(\sp_read:delay_count_8\)
XXXXXXXXXXXXXXXX................................................................
| 1 |UNUSED
......++++++++++++++++..........................................................
| 2 |UNUSED
..........++++++++++++++++......................................................
| 3 |(S_7)
..............++XXXXXXXXXXXX++..................................................
| 4 |UNUSED
..................++++++++++++++++..............................................
| 5 |UNUSED
......................++++++++++++++++..........................................
| 6 |UNUSED
..........................++++++++++++++++......................................
| 7 |(S_15)
..............................XXXXXXXXXXXXXXXX..................................
| 8 |UNUSED
..................................++++++++++++++++..............................
| 9 |UNUSED
......................................++++++++++++++++..........................
|10 |UNUSED
..........................................++++++++++++++++......................
|11 |(\sp_read:delay_count_9\)
..............................................XXXXXXXXXXXXXXXX..................
|12>|reset
..................................................++++++++++++X+++..............
|13 |UNUSED
......................................................++++++++++++++++..........
|14 |UNUSED
..........................................................++++++++++++++++......
|15 |(\sp_read:delay_count_2\)
................................................................XXXXXXXXXXXXXXX+
________________________________________________________________________________

Total count of outputs placed        =  6 
Total count of unique Product Terms  =  76 
Total Product Terms to be assigned   =  76 
Max Product Terms used / available   =  76 /  80   = 95.1  %


Control Signals for Logic Block J
---------------------------------
CLK pin19: <not used>
CLK pin22: <not used>
CLK pin99: clk
CLK pin102: <not used>
CLK PT      : AH : <not used>
PRESET      : AH : <not used>
RESET       : AH : <not used>
OE 0        : AH : <not used>
OE 1        : AH : <not used>
OE 2        : AH : <not used>
OE 3        : AH : <not used>



                              Logic Block J
                 ____________________________________________
                 |   |= >bp_end_addr..                  |   |                 
                 |   |= >\sp_read:co..                  |   |                 
                 |   |= >\sp_read:de..                  |   |                 
                 |   |= >bp_start_ad..                  |   |                 
                 |   |= >\sp_read:co..                  | 72|= (\sp_read:delay_count_8\) 
                 |   |= >\sp_read:co..                  |   |                 
                 |   |= >sinphase_ze..   not used:1031 >|   |                 
                 |   |= >\sp_read:co..                  |   |                 
                 |   |= >\sp_read:co..                  | 73|* not used       
                 |   |= >\sp_read:de..                  |   |                 
                 |   |= >\sp_read:co..           (S_7) =|   |                 
                 |   |> not used:624                    |   |                 
                 |   |= >bp_end_addr..                  | 74|* not used       
                 |   |= >\sp_read:co..                  |   |                 
                 |   |= >\sp_read:de..   not used:1035 >|   |                 
                 |   |= >\sp_read:de..                  |   |                 
                 |   |= >\sp_read:co..                  | 75|* not used       
                 |   |> not used:630                    |   |                 
                 |   |= >bp_end_addr..          (S_15) =|   |                 
                 |   |> not used:632                    |   |                 
                 |   |= >bp_end_addr..                  | 76|* not used       
                 |   |= >bp_end_addr..                  |   |                 
                 |   |= >\sp_read:co..   not used:1039 >|   |                 
                 |   |= >\sp_read:ol..                  |   |                 
                 |   |= >bp_start_ad..                  | 77|* not used       
                 |   |= >fast                           |   |                 
                 |   |= >\sp_read:co..  (\sp_read:delay_count_9\) =|   |                 
                 |   |= >bp_end_addr..                  |   |                 
                 |   |= >\sp_read:de..                  | 78|= reset          
                 |   |= >bp_end_addr..                  |   |                 
                 |   |= >bp_end_addr..   not used:1043 >|   |                 
                 |   |> not used:644                    |   |                 
                 |   |= >\sp_read:de..                  | 79|* not used       
                 |   |= >\sp_read:de..                  |   |                 
                 |   |= >\sp_read:de..  (\sp_read:delay_count_2\) =|   |                 
                 |   |> not used:648                    |   |                 
                 |   |= >\sp_read:de..                  |   |                 
                 |   |= >\sp_read:de..                  |   |                 
                 |   |= >slow                           |   |                 
                 ____________________________________________


  Information: Macrocell Utilization.

                     Description        Used     Max
                 ______________________________________
                 | I/O Macrocells     |    2  |    8  |
                 | Buried Macrocells  |    4  |    8  |
                 | PIM Input Connects |   34  |   36  |
                 ______________________________________
                                          40  /   52   = 76  %


----------------------------------------------------------------------------
PLD Compiler Software:        C37KFIT.EXE    22/DEC/2000  [v4.02 ] 6.2 IR 27

LOGIC BLOCK K PLACEMENT   (20:13:21)

Messages:


________________________________________________________________________________
          1111111111222222222233333333334444444444555555555566666666667777777777
01234567890123456789012345678901234567890123456789012345678901234567890123456789
________________________________________________________________________________
| 0 |(S_6)
XXXXX+XXXXXXXXXX................................................................
| 1 |(S_8)
......XXXXXXXXXXXXXX++..........................................................
| 2 |(\sp_read:reset_count_1\)
..........++++++++++XX++++......................................................
| 3 |(S_18)
..............++++++++XXXXX+XX..................................................
| 4 |UNUSED
..................++++++++++++++++..............................................
| 5 |(S_14)
......................+++++X++XXXXXXXX..........................................
| 6 |UNUSED
..........................++++++++++++++++......................................
| 7 |UNUSED
..............................++++++++++++++++..................................
| 8 |(S_4)
..................................++++XXXXXXXXXX++..............................
| 9 |UNUSED
......................................++++++++++++++++..........................
|10 |(S_10)
..........................................X+++++XXXXXXX+XX......................
|11 |UNUSED
..............................................++++++++++++++++..................
|12 |UNUSED
..................................................++++++++++++++++..............
|13 |(S_12)
......................................................+X++XXXXXXXXX+++..........
|14 |UNUSED
..........................................................++++++++++++++++......
|15 |(S_5)
................................................................+++XXXXXXXXXXXXX
________________________________________________________________________________

Total count of outputs placed        =  9 
Total count of unique Product Terms  =  79 
Total Product Terms to be assigned   =  90 
Max Product Terms used / available   =  79 /  80   = 98.76 %


Control Signals for Logic Block K
---------------------------------
CLK pin19: <not used>
CLK pin22: <not used>
CLK pin99: clk
CLK pin102: <not used>
CLK PT      : AH : <not used>
PRESET      : AH : <not used>
RESET       : AH : <not used>
OE 0        : AH : <not used>
OE 1        : AH : <not used>
OE 2        : AH : <not used>
OE 3        : AH : <not used>



                              Logic Block K
                 ____________________________________________
                 |   |= >bp_end_addr..                  |   |                 
                 |   |= >bp_end_addr..                  |   |                 
                 |   |= >\sp_read:co..                  |   |                 
                 |   |= >bp_start_ad..                  |   |                 
                 |   |= >\sp_read:ol..                  | 82|= (S_6)          
                 |   |= >\sp_read:co..                  |   |                 
                 |   |= >sinphase_ze..           (S_8) =|   |                 
                 |   |= >bp_start_ad..                  |   |                 
                 |   |= >\sp_read:co..                  | 83|= (\sp_read:reset_count_1\) 
                 |   |= >\sp_read:co..                  |   |                 
                 |   |= >\sp_read:co..          (S_18) =|   |                 
                 |   |= >\sp_read:co..                  |   |                 
                 |   |= >bp_end_addr..                  | 84|* not used       
                 |   |= >\sp_read:co..                  |   |                 
                 |   |> not used:666            (S_14) =|   |                 
                 |   |= >\sp_read:co..                  |   |                 
                 |   |= >\sp_read:co..                  | 85|* not used       
                 |   |> not used:669                    |   |                 
                 |   |= >bp_end_addr..   not used:1053 >|   |                 
                 |   |= >\sp_read:co..                  |   |                 
                 |   |= >bp_end_addr..                  | 86|= (S_4)          
                 |   |= >\sp_read:co..                  |   |                 
                 |   |= >\sp_read:co..   not used:1055 >|   |                 
                 |   |= >bp_start_ad..                  |   |                 
                 |   |= >bp_start_ad..                  | 87|= (S_10)         
                 |   |= >\sp_read:re..                  |   |                 
                 |   |> not used:678     not used:1057 >|   |                 
                 |   |= >bp_end_addr..                  |   |                 
                 |   |> not used:680                    | 88|* not used       
                 |   |= >bp_end_addr..                  |   |                 
                 |   |= >bp_end_addr..          (S_12) =|   |                 
                 |   |> not used:683                    |   |                 
                 |   |> not used:684                    | 89|* not used       
                 |   |> not used:685                    |   |                 
                 |   |> not used:686             (S_5) =|   |                 
                 |   |= >bp_start_ad..                  |   |                 
                 |   |= >\sp_read:re..                  |   |                 
                 |   |= >bp_start_ad..                  |   |                 
                 |   |= >bp_start_ad..                  |   |                 
                 ____________________________________________


  Information: Macrocell Utilization.

                     Description        Used     Max
                 ______________________________________
                 | I/O Macrocells     |    4  |    8  |
                 | Buried Macrocells  |    5  |    8  |
                 | PIM Input Connects |   31  |   36  |
                 ______________________________________
                                          40  /   52   = 76  %


----------------------------------------------------------------------------
PLD Compiler Software:        C37KFIT.EXE    22/DEC/2000  [v4.02 ] 6.2 IR 27

LOGIC BLOCK L PLACEMENT   (20:13:21)

Messages:


________________________________________________________________________________
          1111111111222222222233333333334444444444555555555566666666667777777777
01234567890123456789012345678901234567890123456789012345678901234567890123456789
________________________________________________________________________________
| 0 |(S_13)
XXXXXXXXXXXXXXXX................................................................
| 1 |(il_tristate)
......++++++++++XX++++..........................................................
| 2 |(sensor_address_3)ao_to_pc_ack
..........++++++++++++++XX......................................................
| 3 |(\sp_read:delay_count_3\)
..............++++XXXXXX++XXXX..................................................
| 4>|ao_to_pc_strobe
..................++++++++++++++XX..............................................
| 5 |(\sp_read:reset_count_0\)
......................++++++++X+++++++..........................................
| 6>|ao_from_pc_ack
..........................+++++X++++++++++......................................
| 7 |(\sp_read:delay_count_4\)
..............................++++XXXXXXXXX+XX..................................
| 8 |[i/p]
..................................++++++++++++++++..............................
| 9 |UNUSED
......................................++++++++++++++++..........................
|10 |UNUSED
..........................................++++++++++++++++......................
|11 |(S_11)
..............................................XXXXXXXXXXXXXXXX..................
|12 |UNUSED
..................................................++++++++++++++++..............
|13 |UNUSED
......................................................++++++++++++++++..........
|14 |[i/p]
..........................................................++++++++++++++++......
|15 |(S_17)
................................................................XXXXXXXXXXXXXXXX
________________________________________________________________________________

Total count of outputs placed        =  10 
Total count of unique Product Terms  =  77 
Total Product Terms to be assigned   =  77 
Max Product Terms used / available   =  77 /  80   = 96.26 %


Control Signals for Logic Block L
---------------------------------
CLK pin19: <not used>
CLK pin22: <not used>
CLK pin99: clk
CLK pin102: <not used>
CLK PT      : AH : <not used>
PRESET      : AH : <not used>
RESET       : AH : <not used>
OE 0        : AH : /il_tristate.Q 
OE 1        : AH : <not used>
OE 2        : AH : /il_tristate.Q 
OE 3        : AH : <not used>



                              Logic Block L
                 ____________________________________________
                 |   |= >\sp_read:de..                  |   |                 
                 |   |= >\sp_read:co..                  |   |                 
                 |   |= >\sp_read:de..                  |   |                 
                 |   |= >bp_start_ad..                  |   |                 
                 |   |= >\sp_read:co..                  | 91|= (S_13)         
                 |   |= >bp_start_ad..                  |   |                 
                 |   |= >sinphase_ze..   (il_tristate) =|   |                 
                 |   |= >\ibus_reade..                  |   |                 
                 |   |= >\sp_read:co..                  | 92|= (sensor_address_3)ao_to_pc_ack 
                 |   |= >\sp_read:co..                  |   |                 
                 |   |= >\sp_read:re..  (\sp_read:delay_count_3\) =|   |                 
                 |   |> not used:702                    |   |                 
                 |   |= >bp_end_addr..                  | 93|= ao_to_pc_strobe 
                 |   |= >this_chip_s..                  |   |                 
                 |   |= >\sp_read:de..  (\sp_read:reset_count_0\) =|   |                 
                 |   |= >\sp_read:de..                  |   |                 
                 |   |= >bp_end_addr..                  | 94|= ao_from_pc_ack 
                 |   |= >\sp_read:co..                  |   |                 
                 |   |= >\sp_read:co..  (\sp_read:delay_count_4\) =|   |                 
                 |   |= >sensor_addr..                  |   |                 
                 |   |= >ao_to_pc_ack                   | 95|= ao_from_pc_strobe 
                 |   |= >bp_end_addr..                  |   |                 
                 |   |= >\sp_read:co..   not used:1071 >|   |                 
                 |   |= >\sp_read:ol..                  |   |                 
                 |   |> not used:715                    | 96|* not used       
                 |   |= >\ibus_write..                  |   |                 
                 |   |= >\sp_read:co..          (S_11) =|   |                 
                 |   |= >bp_end_addr..                  |   |                 
                 |   |= >\ibus_write..                  | 97|* not used       
                 |   |= >bp_end_addr..                  |   |                 
                 |   |= >bp_end_addr..   not used:1075 >|   |                 
                 |   |= >bp_end_addr..                  |   |                 
                 |   |= >il_tristate.Q                  | 98|= d(0)           
                 |   |> not used:724                    |   |                 
                 |   |= >bp_end_addr..          (S_17) =|   |                 
                 |   |= >\ibus_reade..                  |   |                 
                 |   |= >\sp_read:de..                  |   |                 
                 |   |= >tristate_st..                  |   |                 
                 |   |= >bp_start_ad..                  |   |                 
                 ____________________________________________


  Information: Macrocell Utilization.

                     Description        Used     Max
                 ______________________________________
                 | I/O Macrocells     |    6  |    8  |
                 | Buried Macrocells  |    6  |    8  |
                 | PIM Input Connects |   36  |   36  |
                 ______________________________________
                                          48  /   52   = 92  %


----------------------------------------------------------------------------
PLD Compiler Software:        C37KFIT.EXE    22/DEC/2000  [v4.02 ] 6.2 IR 27

LOGIC BLOCK M PLACEMENT   (20:13:21)

Messages:


________________________________________________________________________________
          1111111111222222222233333333334444444444555555555566666666667777777777
01234567890123456789012345678901234567890123456789012345678901234567890123456789
________________________________________________________________________________
| 0 |(\sp_read:delay_count_0\)d(1)
XXXXXXXXXXXXXXX+................................................................
| 1 |UNUSED
......++++++++++++++++..........................................................
| 2 |[i/p]
..........++++++++++++++++......................................................
| 3 |(\sp_read:delay_count_6\)
..............+XXXXXXXXXXXXX++..................................................
| 4 |[i/p]
..................++++++++++++++++..............................................
| 5 |UNUSED
......................++++++++++++++++..........................................
| 6 |(\ibus_writer:iu_writeSBV_1\)d(4)
..........................++XXXX++++++++++......................................
| 7 |(\sp_read:delay_count_7\)
..............................++XXXXXXXXXXXXXX..................................
| 8 |(S_1)d(5)
..................................++++++++++++XX++..............................
| 9 |UNUSED
......................................++++++++++++++++..........................
|10 |[i/p]
..........................................++++++++++++++++......................
|11 |UNUSED
..............................................++++++++++++++++..................
|12 |(\sp_read:delay_count_5\)d(7)
..................................................XXXXXXXXXXXX++++..............
|13 |UNUSED
......................................................++++++++++++++++..........
|14 |[i/p]
..........................................................++++++++++++++++......
|15 |(\sp_read:delay_count_1\)
................................................................XXXXXXXXXXXXXXX+
________________________________________________________________________________

Total count of outputs placed        =  7 
Total count of unique Product Terms  =  75 
Total Product Terms to be assigned   =  75 
Max Product Terms used / available   =  75 /  80   = 93.76 %


Control Signals for Logic Block M
---------------------------------
CLK pin19: <not used>
CLK pin22: <not used>
CLK pin99: clk
CLK pin102: <not used>
CLK PT      : AH : <not used>
PRESET      : AH : <not used>
RESET       : AH : <not used>
OE 0        : AH : <not used>
OE 1        : AH : <not used>
OE 2        : AH : <not used>
OE 3        : AH : <not used>



                              Logic Block M
                 ____________________________________________
                 |   |= >\sp_read:de..                  |   |                 
                 |   |= >\sp_read:co..                  |   |                 
                 |   |= >\sp_read:de..                  |   |                 
                 |   |= >sensor_to_i..                  |   |                 
                 |   |= >\sp_read:ol..                  |103|= (\sp_read:delay_count_0\)d(1) 
                 |   |= >ao_to_pc_ack                   |   |                 
                 |   |= >sinphase_ze..   not used:1079 >|   |                 
                 |   |= >\ibus_write..                  |   |                 
                 |   |= >\sp_read:co..                  |104|= d(2)           
                 |   |= >\sp_read:de..                  |   |                 
                 |   |= >\ibus_write..  (\sp_read:delay_count_6\) =|   |                 
                 |   |> not used:741                    |   |                 
                 |   |= >bp_end_addr..                  |105|= d(3)           
                 |   |= >bp_end_addr..                  |   |                 
                 |   |= >\sp_read:de..   not used:1083 >|   |                 
                 |   |= >\sp_read:de..                  |   |                 
                 |   |= >bp_end_addr..                  |106|= (\ibus_writer:iu_writeSBV_1\)d(4) 
                 |   |= >\ibus_write..                  |   |                 
                 |   |= >bp_end_addr..  (\sp_read:delay_count_7\) =|   |                 
                 |   |> not used:749                    |   |                 
                 |   |= >bp_end_addr..                  |107|= (S_1)d(5)      
                 |   |= >\sp_read:de..                  |   |                 
                 |   |= >\sp_read:co..   not used:1087 >|   |                 
                 |   |= >loopback_st..                  |   |                 
                 |   |= >\ibus_write..                  |108|= d(6)           
                 |   |= >\ibus_write..                  |   |                 
                 |   |= >\sp_read:co..   not used:1089 >|   |                 
                 |   |> not used:757                    |   |                 
                 |   |= >bp_end_addr..                  |109|= (\sp_read:delay_count_5\)d(7) 
                 |   |= >bp_end_addr..                  |   |                 
                 |   |= >\ibus_write..   not used:1091 >|   |                 
                 |   |= >bp_end_addr..                  |   |                 
                 |   |> not used:762                    |110|= d(8)           
                 |   |= >from_pc_req.Q                  |   |                 
                 |   |= >\sp_read:de..  (\sp_read:delay_count_1\) =|   |                 
                 |   |> not used:765                    |   |                 
                 |   |= >\sp_read:de..                  |   |                 
                 |   |= >\sp_read:de..                  |   |                 
                 |   |= >\sp_read:de..                  |   |                 
                 ____________________________________________


  Information: Macrocell Utilization.

                     Description        Used     Max
                 ______________________________________
                 | I/O Macrocells     |    8  |    8  |
                 | Buried Macrocells  |    3  |    8  |
                 | PIM Input Connects |   34  |   36  |
                 ______________________________________
                                          45  /   52   = 86  %


----------------------------------------------------------------------------
PLD Compiler Software:        C37KFIT.EXE    22/DEC/2000  [v4.02 ] 6.2 IR 27

LOGIC BLOCK N PLACEMENT   (20:13:21)

Messages:


________________________________________________________________________________
          1111111111222222222233333333334444444444555555555566666666667777777777
01234567890123456789012345678901234567890123456789012345678901234567890123456789
________________________________________________________________________________
| 0 |(S_3)d(9)
XXXXXXXXXXXXXXXX................................................................
| 1 |(\ibus_writer:iu_writeSBV_0\)
......++++++++++XXX+XX..........................................................
| 2 |[i/p]
..........++++++++++++++++......................................................
| 3 |UNUSED
..............++++++++++++++++..................................................
| 4 |[i/p]
..................++++++++++++++++..............................................
| 5 |(\ibus_writer:timeout_0\)
......................XXXXXXXX++++++++..........................................
| 6 |[i/p]
..........................++++++++++++++++......................................
| 7 |(S_9)
..............................XXXXXXXXXXXXXXXX..................................
| 8 |UNUSED
..................................++++++++++++++++..............................
| 9 |(\ibus_writer:timeout_2\)
......................................++++++++XXXXXXXX..........................
|10 |[i/p]
..........................................++++++++++++++++......................
|11 |(\ibus_writer:timeout_3\)
..............................................++++++++XXXXX+XX..................
|12 |[i/p]
..................................................++++++++++++++++..............
|13 |UNUSED
......................................................++++++++++++++++..........
|14 |[i/p]
..........................................................++++++++++++++++......
|15 |(\sp_read:cmp_vv_us_MODGEN_10\)
................................................................XXXXXXXXXXXXXXXX
________________________________________________________________________________

Total count of outputs placed        =  7 
Total count of unique Product Terms  =  76 
Total Product Terms to be assigned   =  76 
Max Product Terms used / available   =  76 /  80   = 95.1  %


Control Signals for Logic Block N
---------------------------------
CLK pin19: <not used>
CLK pin22: <not used>
CLK pin99: clk
CLK pin102: <not used>
CLK PT      : AH : <not used>
PRESET      : AH : <not used>
RESET       : AH : <not used>
OE 0        : AH : <not used>
OE 1        : AH : <not used>
OE 2        : AH : <not used>
OE 3        : AH : <not used>



                              Logic Block N
                 ____________________________________________
                 |   |= >loopback_st..                  |   |                 
                 |   |= >\sp_read:co..                  |   |                 
                 |   |= >\sp_read:co..                  |   |                 
                 |   |= >sensor_to_i..                  |   |                 
                 |   |= >\sp_read:co..                  |112|= (S_3)d(9)      
                 |   |= >\sp_read:co..                  |   |                 
                 |   |= >sinphase_ze..  (\ibus_writer:iu_writeSBV_0\) =|   |                 
                 |   |= >\ibus_write..                  |   |                 
                 |   |= >\sp_read:co..                  |113|= d(10)          
                 |   |= >\sp_read:co..                  |   |                 
                 |   |= >\ibus_write..   not used:1097 >|   |                 
                 |   |= >\sp_read:co..                  |   |                 
                 |   |= >bp_end_addr..                  |114|= d(11)          
                 |   |= >bp_end_addr..                  |   |                 
                 |   |> not used:783    (\ibus_writer:timeout_0\) =|   |                 
                 |   |= >\sp_read:co..                  |   |                 
                 |   |= >bp_end_addr..                  |115|= d(12)          
                 |   |= >\ibus_write..                  |   |                 
                 |   |= >bp_end_addr..           (S_9) =|   |                 
                 |   |= >\sp_read:co..                  |   |                 
                 |   |= >ao_to_pc_ack                   |116|* not used       
                 |   |= >bp_end_addr..                  |   |                 
                 |   |= >\sp_read:co..  (\ibus_writer:timeout_2\) =|   |                 
                 |   |= >\sp_read:ol..                  |   |                 
                 |   |= >\ibus_write..                  |117|= d(13)          
                 |   |= >\ibus_write..                  |   |                 
                 |   |= >\sp_read:co..  (\ibus_writer:timeout_3\) =|   |                 
                 |   |= >bp_end_addr..                  |   |                 
                 |   |= >bp_end_addr..                  |118|= d(14)          
                 |   |= >bp_start_ad..                  |   |                 
                 |   |= >\ibus_write..   not used:1107 >|   |                 
                 |   |= >bp_end_addr..                  |   |                 
                 |   |> not used:801                    |119|= d(15)          
                 |   |= >from_pc_req.Q                  |   |                 
                 |   |> not used:803    (\sp_read:cmp_vv_us_MODGEN_10\) =|   |                 
                 |   |> not used:804                    |   |                 
                 |   |> not used:805                    |   |                 
                 |   |= >bp_start_ad..                  |   |                 
                 |   |= >\sp_read:co..                  |   |                 
                 ____________________________________________


  Information: Macrocell Utilization.

                     Description        Used     Max
                 ______________________________________
                 | I/O Macrocells     |    7  |    8  |
                 | Buried Macrocells  |    6  |    8  |
                 | PIM Input Connects |   34  |   36  |
                 ______________________________________
                                          47  /   52   = 90  %


----------------------------------------------------------------------------
PLD Compiler Software:        C37KFIT.EXE    22/DEC/2000  [v4.02 ] 6.2 IR 27

LOGIC BLOCK O PLACEMENT   (20:13:21)

Messages:


________________________________________________________________________________
          1111111111222222222233333333334444444444555555555566666666667777777777
01234567890123456789012345678901234567890123456789012345678901234567890123456789
________________________________________________________________________________
| 0>|d(16)
XXXX++++++++++++................................................................
| 1 |(\bp_io:timeout_1\)
......XXXX+++++XXXXX++..........................................................
| 2>|d(17)
..........XXXX++++++++++++......................................................
| 3 |(write_to_bp_ack)
..............X+++++++X+++++++..................................................
| 4>|d(18)
..................++XX++XX++++++++..............................................
| 5 |(\bp_io:bp_access_stateSBV_0\)
......................XX++++XXXXXX++++..........................................
| 6>|d(19)
..........................XX++++++++++XX++......................................
| 7 |(\bp_io:bp_access_stateSBV_2\)
..............................XX++++XX++XX++XX..................................
| 8>|d(20)
..................................XX++++++++++++XX..............................
| 9 |(\bp_io:timeout_2\)
......................................++++XX++XX++++XX..........................
|10>|d(21)
..........................................++++++++XX++++XX......................
|11 |(to_pc_ack)
..............................................++++++++X+++++XX..................
|12>|d(22)
..................................................+++++X++XX++X+++..............
|13 |UNUSED
......................................................++++++++++++++++..........
|14>|d(23)
..........................................................+++++XXXX+++++++......
|15 |(\bp_io:timeout_0\)
................................................................+++XXXXXXXXXXXXX
________________________________________________________________________________

Total count of outputs placed        =  15 
Total count of unique Product Terms  =  77 
Total Product Terms to be assigned   =  81 
Max Product Terms used / available   =  78 /  80   = 97.51 %


Control Signals for Logic Block O
---------------------------------
CLK pin19: <not used>
CLK pin22: <not used>
CLK pin99: clk
CLK pin102: <not used>
CLK PT      : AH : <not used>
PRESET      : AH : <not used>
RESET       : AH : <not used>
OE 0        : AH : <not used>
OE 1        : AH : <not used>
OE 2        : AH : <not used>
OE 3        : AH : <not used>



                              Logic Block O
                 ____________________________________________
                 |   |= >sensor_data..                  |   |                 
                 |   |= >bpd(10).Q                      |   |                 
                 |   |= >from_pc_req.Q                  |   |                 
                 |   |= >sensor_to_i..                  |   |                 
                 |   |= >sensor_to_b..                  |122|= d(16)          
                 |   |= >sensor_data..                  |   |                 
                 |   |= >\bp_io:bp_a..  (\bp_io:timeout_1\) =|   |                 
                 |   |= >sensor_data..                  |   |                 
                 |   |= >sensor_data..                  |123|= d(17)          
                 |   |= >\bp_io:time..                  |   |                 
                 |   |= >d(17).Q        (write_to_bp_ack) =|   |                 
                 |   |= >sensor_data..                  |   |                 
                 |   |= >bpctrl(4).Q                    |124|= d(18)          
                 |   |= >\bp_io:time..                  |   |                 
                 |   |= >bpd(11).Q      (\bp_io:bp_access_stateSBV_0\) =|   |                 
                 |   |= >d(20).Q                        |   |                 
                 |   |= >\bp_io:bp_a..                  |125|= d(19)          
                 |   |= >bpd(12).Q                      |   |                 
                 |   |= >d(21).Q        (\bp_io:bp_access_stateSBV_2\) =|   |                 
                 |   |> not used:827                    |   |                 
                 |   |= >bpd(13).Q                      |126|= d(20)          
                 |   |> not used:829                    |   |                 
                 |   |= >sensor_data..  (\bp_io:timeout_2\) =|   |                 
                 |   |= >loopback_st..                  |   |                 
                 |   |= >d(23).Q                        |127|= d(21)          
                 |   |= >\ibus_write..                  |   |                 
                 |   |= >\bp_io:time..     (to_pc_ack) =|   |                 
                 |   |= >d(22).Q                        |   |                 
                 |   |= >\ibus_write..                  |128|= d(22)          
                 |   |= >sensor_data..                  |   |                 
                 |   |= >d(18).Q         not used:1123 >|   |                 
                 |   |= >bpd(14).Q                      |   |                 
                 |   |= >\bp_io:bp_a..                  |129|= d(23)          
                 |   |= >d(19).Q                        |   |                 
                 |   |= >sensor_data..  (\bp_io:timeout_0\) =|   |                 
                 |   |= >bpd(15).Q                      |   |                 
                 |   |> not used:844                    |   |                 
                 |   |= >d(16).Q                        |   |                 
                 |   |= >bpctrl(5).Q                    |   |                 
                 ____________________________________________


  Information: Macrocell Utilization.

                     Description        Used     Max
                 ______________________________________
                 | I/O Macrocells     |    8  |    8  |
                 | Buried Macrocells  |    7  |    8  |
                 | PIM Input Connects |   36  |   36  |
                 ______________________________________
                                          51  /   52   = 98  %


----------------------------------------------------------------------------
PLD Compiler Software:        C37KFIT.EXE    22/DEC/2000  [v4.02 ] 6.2 IR 27

LOGIC BLOCK P PLACEMENT   (20:13:21)

Messages:


________________________________________________________________________________
          1111111111222222222233333333334444444444555555555566666666667777777777
01234567890123456789012345678901234567890123456789012345678901234567890123456789
________________________________________________________________________________
| 0>|d(24)
XXXX++++++++++++................................................................
| 1 |UNUSED
......++++++++++++++++..........................................................
| 2>|d(25)
..........XXXX++++++++++++......................................................
| 3 |(\sp_read:old_phase\)
..............X+++++++++++++++..................................................
| 4>|d(26)
..................XXXX++++++++++++..............................................
| 5 |UNUSED
......................++++++++++++++++..........................................
| 6>|d(27)
..........................XXXX++++++++++++......................................
| 7 |UNUSED
..............................++++++++++++++++..................................
| 8>|d(28)
..................................XXXX++++++++++++..............................
| 9 |UNUSED
......................................++++++++++++++++..........................
|10>|d(29)
..........................................XXXX++++++++++++......................
|11 |UNUSED
..............................................++++++++++++++++..................
|12>|d(30)
..................................................XXXX++++++++++++..............
|13 |UNUSED
......................................................++++++++++++++++..........
|14>|d(31)
..........................................................XXXX++++++++++++......
|15 |UNUSED
................................................................++++++++++++++++
________________________________________________________________________________

Total count of outputs placed        =  9 
Total count of unique Product Terms  =  33 
Total Product Terms to be assigned   =  33 
Max Product Terms used / available   =  33 /  80   = 41.26 %


Control Signals for Logic Block P
---------------------------------
CLK pin19: <not used>
CLK pin22: <not used>
CLK pin99: clk
CLK pin102: <not used>
CLK PT      : AH : <not used>
PRESET      : AH : fast * (this_chip_selected)sinphase_zeros * /slow 
RESET       : AH : fast * /(this_chip_selected)sinphase_zeros * /slow 
OE 0        : AH : <not used>
OE 1        : AH : <not used>
OE 2        : AH : <not used>
OE 3        : AH : <not used>



                              Logic Block P
                 ____________________________________________
                 |   |= >\ibus_write..                  |   |                 
                 |   |= >fast                           |   |                 
                 |   |= >d(25).Q                        |   |                 
                 |   |= >sensor_data..                  |   |                 
                 |   |> not used:851                    |131|= d(24)          
                 |   |= >bpctrl(6).Q                    |   |                 
                 |   |= >d(26).Q         not used:1127 >|   |                 
                 |   |= >bpctrl(10).Q                   |   |                 
                 |   |= >sensor_data..                  |132|= d(25)          
                 |   |= >sensor_data..                  |   |                 
                 |   |= >bpctrl(11).Q   (\sp_read:old_phase\) =|   |                 
                 |   |= >sensor_data..                  |   |                 
                 |   |= >d(28).Q                        |133|= d(26)          
                 |   |= >slow                           |   |                 
                 |   |= >bpctrl(7).Q     not used:1131 >|   |                 
                 |   |= >d(27).Q                        |   |                 
                 |   |= >sensor_data..                  |134|= d(27)          
                 |   |= >bpctrl(8).Q                    |   |                 
                 |   |> not used:865     not used:1133 >|   |                 
                 |   |= >sensor_data..                  |   |                 
                 |   |= >d(29).Q                        |135|= d(28)          
                 |   |> not used:868                    |   |                 
                 |   |> not used:869     not used:1135 >|   |                 
                 |   |= >d(30).Q                        |   |                 
                 |   |= >from_pc_req.Q                  |136|= d(29)          
                 |   |= >data_from_p..                  |   |                 
                 |   |= >sensor_data..   not used:1137 >|   |                 
                 |   |= >sensor_to_i..                  |   |                 
                 |   |= >\ibus_write..                  |137|= d(30)          
                 |   |= >data_from_p..                  |   |                 
                 |   |> not used:877     not used:1139 >|   |                 
                 |   |= >data_from_p..                  |   |                 
                 |   |= >d(31).Q                        |138|= d(31)          
                 |   |= >loopback_st..                  |   |                 
                 |   |= >sensor_data..   not used:1141 >|   |                 
                 |   |= >sinphase_ze..                  |   |                 
                 |   |> not used:883                    |   |                 
                 |   |= >d(24).Q                        |   |                 
                 |   |> not used:885                    |   |                 
                 ____________________________________________


  Information: Macrocell Utilization.

                     Description        Used     Max
                 ______________________________________
                 | I/O Macrocells     |    8  |    8  |
                 | Buried Macrocells  |    1  |    8  |
                 | PIM Input Connects |   32  |   36  |
                 ______________________________________
                                          41  /   52   = 78  %


----------------------------------------------------------------------------
PLD Compiler Software:        C37KFIT.EXE    22/DEC/2000  [v4.02 ] 6.2 IR 27

PINOUT INFORMATION   (20:13:21)


Device:  cy37256p160
Package: cy37256p160-125ac

                     1  :  GND
                     2  :  (sensor_data_15)
                >    3  :  bpctrl_h_tristate
                >    4  :  bpd_l_tristate
                >    5  :  bpctrl_l_dir
                     6  :  (sensor_address_1)
                >    7  :  bpctrl_l_tristate
                >    8  :  bpctrl_h_dir
                >    9  :  bpd_l_dir
                    10  :  GND
                >   11  :  bpctrl(0)
                >   12  :  bpctrl(1)
                >   13  :  bpctrl(2)
                >   14  :  bpctrl(3)
                >   15  :  bpctrl(4)
                >   16  :  bpctrl(5)
                >   17  :  bpctrl(6)
                >   18  :  bpctrl(7)
                >   19  :  slow
                    20  :  VCC
                    21  :  GND
                >   22  :  fast
                >   23  :  bpctrl(8)
                    24  :  (bp_start_address_4)
                >   25  :  bpctrl(10)
                >   26  :  bpctrl(11)
                    27  :  (bp_end_address_5)
                    28  :  (bp_start_address_1)
                    29  :  (bp_start_address_3)
                    30  :  (data_from_pc_13)
                    31  :  GND
                >   32  :  bpaddr(0)
                >   33  :  bpaddr(1)
                >   34  :  bpaddr(2)
                >   35  :  bpaddr(3)
                >   36  :  bpaddr(4)
                >   37  :  bpaddr(5)
                >   38  :  bpaddr(6)
                >   39  :  bpaddr(7)
                    40  :  VCC
                    41  :  GND
                >   42  :  bpd_h_dir
                >   43  :  bpd_h_tristate
                >   44  :  bpaddr_tristate
                >   45  :  bpaddr_dir
                    46  :  (sensor_to_bp_read_req)
                >   47  :  led1
                >   48  :  led2
                >   49  :  led3
                    50  :  GND
                    51  :  (\ibus_reader:timeout_0\)
                    52  :  (\ibus_reader:il_read_stateSBV_0\)
                    53  :  (address_from_pc_3)
                    54  :  (address_from_pc_2)
                    55  :  (sensor_address_2)
                    56  :  (from_pc_req)
                    57  :  (address_from_pc_6)
                    58  :  Not Used
                    59  :  Not Used
                    60  :  VCC
                    61  :  GND
                    62  :  VCC
                    63  :  (S_19)
                    64  :  (bp_end_address_7)
                    65  :  (address_from_pc_0)
                >   66  :  (this_chip_selected)sinphase_zeros
                    67  :  (\ibus_reader:this_is_a_ctrl_transaction\)
                    68  :  (address_from_pc_7)
                    69  :  (bp_end_address_3)
                    70  :  (data_from_pc_15)
                    71  :  GND
                    72  :  (\sp_read:delay_count_8\)
                    73  :  Not Used
                    74  :  Not Used
                    75  :  Not Used
                    76  :  Not Used
                    77  :  Not Used
                >   78  :  reset
                    79  :  Not Used
                    80  :  VCC
                    81  :  GND
                    82  :  (S_6)
                    83  :  (\sp_read:reset_count_1\)
                    84  :  Not Used
                    85  :  Not Used
                    86  :  (S_4)
                    87  :  (S_10)
                    88  :  Not Used
                    89  :  Not Used
                    90  :  GND
                    91  :  (S_13)
                >   92  :  (sensor_address_3)ao_to_pc_ack
                >   93  :  ao_to_pc_strobe
                >   94  :  ao_from_pc_ack
                >   95  :  ao_from_pc_strobe
                    96  :  Not Used
                    97  :  Not Used
                >   98  :  d(0)
                >   99  :  clk
                   100  :  VCC
                   101  :  GND
                   102  :  Not Used
                >  103  :  (\sp_read:delay_count_0\)d(1)
                >  104  :  d(2)
                >  105  :  d(3)
                >  106  :  (\ibus_writer:iu_writeSBV_1\)d(4)
                >  107  :  (S_1)d(5)
                >  108  :  d(6)
                >  109  :  (\sp_read:delay_count_5\)d(7)
                >  110  :  d(8)
                   111  :  GND
                >  112  :  (S_3)d(9)
                >  113  :  d(10)
                >  114  :  d(11)
                >  115  :  d(12)
                   116  :  Not Used
                >  117  :  d(13)
                >  118  :  d(14)
                >  119  :  d(15)
                   120  :  VCC
                   121  :  GND
                >  122  :  d(16)
                >  123  :  d(17)
                >  124  :  d(18)
                >  125  :  d(19)
                >  126  :  d(20)
                >  127  :  d(21)
                >  128  :  d(22)
                >  129  :  d(23)
                   130  :  GND
                >  131  :  d(24)
                >  132  :  d(25)
                >  133  :  d(26)
                >  134  :  d(27)
                >  135  :  d(28)
                >  136  :  d(29)
                >  137  :  d(30)
                >  138  :  d(31)
                   139  :  Not Used
                   140  :  VCC
                   141  :  GND
                   142  :  VCC
                >  143  :  (\bp_io:bp_access_stateSBV_1\)bpd(0)
                >  144  :  (sensor_data_5)bpd(1)
                >  145  :  (\sp_read:counter_address_7\)bpd(2)
                >  146  :  (\sp_read:counter_address_3\)bpd(3)
                >  147  :  (\sp_read:counter_address_4\)bpd(4)
                >  148  :  (sensor_data_1)bpd(5)
                >  149  :  (sensor_data_4)bpd(6)
                >  150  :  (tristate_stateSBV_0)bpd(7)
                   151  :  GND
                >  152  :  bpd(8)
                >  153  :  bpd(9)
                >  154  :  bpd(10)
                >  155  :  bpd(11)
                >  156  :  bpd(12)
                >  157  :  bpd(13)
                >  158  :  bpd(14)
                >  159  :  bpd(15)
                   160  :  VCC

----------------------------------------------------------------------------
PLD Compiler Software:        C37KFIT.EXE    22/DEC/2000  [v4.02 ] 6.2 IR 27

RESOURCE UTILIZATION (20:13:21)



  Information: Macrocell Utilization.

                     Description        Used     Max
                 ______________________________________
                 | Dedicated Inputs   |    0  |    1  |
                 | Clock/Inputs       |    3  |    4  |
                 | I/O Macrocells     |  114  |  128  |
                 | Buried Macrocells  |   85  |  128  |
                 | PIM Input Connects |  548  |  624  |
                 ______________________________________
                                         750  /  885   = 84  %



                                      Required     Max (Available)
          CLOCK/LATCH ENABLE signals     1           20
          Input REG/LATCH signals        0          133
          Input PIN signals              3            5
          Input PINs using I/O cells    14           14
          Output PIN signals            72          114


          Total PIN signals             89          133
          Macrocells Used              185          256
          Unique Product Terms         882         1280



----------------------------------------------------------------------------
PLD Compiler Software:        C37KFIT.EXE    22/DEC/2000  [v4.02 ] 6.2 IR 27

PRESET/RESET AND OUTPUT ENABLE COMBINATIONS

PRESET: NONE-COMBINATORIAL
RESET : NONE-COMBINATORIAL
CLOCK PT : NULL
Total unique inputs =  192 
count of output equations =  132 
==>OE: bpctrl(0).Q 
   Used by Logic Blocks: BDE
   count of OE equations =  13 
==>OE: GND or VCC
   count of OE equations =  118 
==>OE: /il_tristate.Q 
   Used by Logic Blocks: L
   count of OE equations =  1 


PRESET: NONE-COMBINATORIAL
RESET : NONE-COMBINATORIAL
CLOCK PT : NULL
Total unique inputs =  58 
count of output equations =  33 
==>OE: GND or VCC
   count of OE equations =  33 


PRESET: GND
RESET : reset.CMB 
CLOCK PT : NULL
Used by Logic Blocks: EHI
Total unique inputs =  41 
count of output equations =  19 
==>OE: GND or VCC
   count of OE equations =  19 


PRESET: fast * (this_chip_selected)sinphase_zeros * /slow 
RESET : fast * /(this_chip_selected)sinphase_zeros * /slow 
CLOCK PT : NULL
Used by Logic Blocks: P
Total unique inputs =  3 
count of output equations =  1 
==>OE: GND or VCC
   count of OE equations =  1 

----------------------------------------------------------------------------
PLD Compiler Software:        C37KFIT.EXE    22/DEC/2000  [v4.02 ] 6.2 IR 27

JEDEC ASSEMBLE             (20:13:21)

Messages:
  Information: Processing JEDEC for Logic Block 1.
  Information: Processing JEDEC for Logic Block 2.
  Information: Processing JEDEC for Logic Block 3.
  Information: Processing JEDEC for Logic Block 4.
  Information: Processing JEDEC for Logic Block 5.
  Information: Processing JEDEC for Logic Block 6.
  Information: Processing JEDEC for Logic Block 7.
  Information: Processing JEDEC for Logic Block 8.
  Information: Processing JEDEC for Logic Block 9.
  Information: Processing JEDEC for Logic Block 10.
  Information: Processing JEDEC for Logic Block 11.
  Information: Processing JEDEC for Logic Block 12.
  Information: Processing JEDEC for Logic Block 13.
  Information: Processing JEDEC for Logic Block 14.
  Information: Processing JEDEC for Logic Block 15.
  Information: Processing JEDEC for Logic Block 16.
  Information: JEDEC output file 'pc_remote_bus.pin' created.
  Information: JEDEC output file 'pc_remote_bus.jed' created.


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully at 20:13:21
----------------------------------------------------------------------------
PLD Compiler Software:        C37KFIT.EXE    22/DEC/2000  [v4.02 ] 6.2 IR 27

TIMING PATH ANALYSIS       (20:13:21) using Package: cy37256p160-125ac

Messages:

----------------------------------------------------------------------------
Signal Name | Delay Type  |   tmax   | Path Description
----------------------------------------------------------------------------
reg::(sensor_data_15)[2]
inp::sinphase_zeros
---->sinphase_zeros
              tS              4.0 ns     1 pass
inp::\sp_read:counter_read_stateSBV_1\.Q
              tSCS            8.0 ns     1 pass
out::sensor_data_15
              tCO             6.5 ns   
----------------------------------------------------------------------------
cmb::bpctrl_h_tristate[3]
inp::bpd_h_tristate.Q
              tCO             12.5 ns    1 pass
----------------------------------------------------------------------------
cmb::bpd_l_tristate[4]
inp::bpd_h_tristate.Q
              tCO             12.5 ns    1 pass
----------------------------------------------------------------------------
cmb::bpctrl_l_dir[5]
----------------------------------------------------------------------------
reg::(sensor_address_1)[6]
inp::\sp_read:counter_address_1\.Q
              tSCS            8.0 ns     1 pass
out::sensor_address_1
              tCO             6.5 ns   
----------------------------------------------------------------------------
cmb::bpctrl_l_tristate[7]
----------------------------------------------------------------------------
cmb::bpctrl_h_dir[8]
----------------------------------------------------------------------------
cmb::bpd_l_dir[9]
inp::bpctrl(0).Q
              tCO             12.5 ns    1 pass
----------------------------------------------------------------------------
reg::bpctrl(0)[11]
inp::\bp_io:bp_access_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
out::bpd_h_dir
              tCO             12.5 ns    1 pass
----------------------------------------------------------------------------
cmb::bpctrl(1)[12]
inp::sinphase_zeros
---->sinphase_zeros
              tPD             8.5 ns     1 pass
----------------------------------------------------------------------------
reg::bpctrl(2)[13]
inp::\bp_io:bp_access_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
out::bpctrl(2)
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::bpctrl(3)[14]
inp::\sp_read:counter_read_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
out::bpctrl(3)
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::bpctrl(4)[15]
inp::ao_from_pc_strobe
              tS              4.0 ns     1 pass
inp::\ibus_reader:il_read_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
out::bpctrl(4)
              tCO             6.5 ns   
inp::bpctrl(0).Q
              tER             16.5 ns    1 pass
----------------------------------------------------------------------------
reg::bpctrl(5)[16]
inp::ao_from_pc_strobe
              tS              4.0 ns     1 pass
inp::\ibus_reader:il_read_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
out::bpctrl(5)
              tCO             6.5 ns   
inp::bpctrl(0).Q
              tER             16.5 ns    1 pass
----------------------------------------------------------------------------
reg::bpctrl(6)[17]
inp::ao_from_pc_strobe
              tS              4.0 ns     1 pass
inp::\ibus_reader:il_read_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
out::bpctrl(6)
              tCO             6.5 ns   
inp::bpctrl(0).Q
              tER             16.5 ns    1 pass
----------------------------------------------------------------------------
reg::bpctrl(7)[18]
inp::ao_from_pc_strobe
              tS              4.0 ns     1 pass
inp::\ibus_reader:il_read_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
out::bpctrl(7)
              tCO             6.5 ns   
inp::bpctrl(0).Q
              tER             16.5 ns    1 pass
----------------------------------------------------------------------------
reg::bpctrl(8)[23]
inp::ao_from_pc_strobe
              tS              4.0 ns     1 pass
inp::\ibus_reader:il_read_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
out::bpctrl(8)
              tCO             6.5 ns   
inp::bpctrl(0).Q
              tER             16.5 ns    1 pass
----------------------------------------------------------------------------
reg::(bp_start_address_4)[24]
inp::\ibus_reader:il_read_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::bp_start_address_4
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::bpctrl(10)[25]
inp::ao_from_pc_strobe
              tS              4.0 ns     1 pass
inp::\ibus_reader:il_read_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
out::bpctrl(10)
              tCO             6.5 ns   
inp::bpctrl(0).Q
              tER             16.5 ns    1 pass
----------------------------------------------------------------------------
reg::bpctrl(11)[26]
inp::ao_from_pc_strobe
              tS              4.0 ns     1 pass
inp::\ibus_reader:il_read_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
out::bpctrl(11)
              tCO             6.5 ns   
inp::bpctrl(0).Q
              tER             16.5 ns    1 pass
----------------------------------------------------------------------------
reg::(bp_end_address_5)[27]
inp::\ibus_reader:il_read_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::bp_end_address_5
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(bp_start_address_1)[28]
inp::\ibus_reader:il_read_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::bp_start_address_1
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(bp_start_address_3)[29]
inp::\ibus_reader:il_read_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::bp_start_address_3
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(data_from_pc_13)[30]
inp::ao_from_pc_strobe
              tS              4.0 ns     1 pass
inp::\ibus_reader:il_read_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
out::data_from_pc_13
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::bpaddr(0)[32]
inp::\bp_io:bp_access_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
out::bpaddr(0)
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::bpaddr(1)[33]
inp::\bp_io:bp_access_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
out::bpaddr(1)
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::bpaddr(2)[34]
inp::\bp_io:bp_access_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
out::bpaddr(2)
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::bpaddr(3)[35]
inp::\bp_io:bp_access_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
out::bpaddr(3)
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::bpaddr(4)[36]
inp::\bp_io:bp_access_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
out::bpaddr(4)
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::bpaddr(5)[37]
inp::\bp_io:bp_access_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
out::bpaddr(5)
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::bpaddr(6)[38]
inp::\bp_io:bp_access_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
out::bpaddr(6)
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::bpaddr(7)[39]
inp::\bp_io:bp_access_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
out::bpaddr(7)
              tCO             6.5 ns   
----------------------------------------------------------------------------
cmb::bpd_h_dir[42]
inp::bpctrl(0).Q
              tCO             12.5 ns    1 pass
----------------------------------------------------------------------------
reg::bpd_h_tristate[43]
inp::\bp_io:bp_access_stateSBV_1\.Q
              tSCS            8.0 ns     1 pass
out::bpctrl_h_tristate
              tCO             12.5 ns    1 pass
----------------------------------------------------------------------------
reg::bpaddr_tristate[44]
inp::\bp_io:bp_access_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
out::bpaddr_tristate
              tCO             6.5 ns   
----------------------------------------------------------------------------
cmb::bpaddr_dir[45]
----------------------------------------------------------------------------
reg::(sensor_to_bp_read_req)[46]
inp::\sp_read:counter_read_stateSBV_1\.Q
              tSCS            8.0 ns     1 pass
out::sensor_to_bp_read_req
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::led1[47]
inp::\bp_io:bp_access_stateSBV_1\.Q
              tSCS            8.0 ns     1 pass
out::led1
              tCO             6.5 ns   
----------------------------------------------------------------------------
cmb::led2[48]
inp::fast
              tPD             10.0 ns    1 pass
----------------------------------------------------------------------------
cmb::led3[49]
inp::slow
              tPD             10.0 ns    1 pass
----------------------------------------------------------------------------
reg::(\ibus_reader:timeout_0\)[51]
inp::ao_from_pc_strobe
              tS              4.0 ns     1 pass
inp::\ibus_reader:il_read_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
out::\ibus_reader:timeout_0\
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(\ibus_reader:il_read_stateSBV_0\)[52]
inp::ao_from_pc_strobe
              tS              4.0 ns     1 pass
inp::\ibus_reader:il_read_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
out::\ibus_reader:il_read_stateSBV_0\
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(address_from_pc_3)[53]
inp::\ibus_reader:il_read_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
out::address_from_pc_3
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(address_from_pc_2)[54]
inp::\ibus_reader:il_read_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
out::address_from_pc_2
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(sensor_address_2)[55]
inp::\sp_read:counter_address_2\.Q
              tSCS            8.0 ns     1 pass
out::sensor_address_2
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(from_pc_req)[56]
inp::\ibus_reader:il_read_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
out::from_pc_req
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(address_from_pc_6)[57]
inp::\ibus_reader:il_read_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
out::address_from_pc_6
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(bp_end_address_7)[64]
inp::\ibus_reader:il_read_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::bp_end_address_7
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(address_from_pc_0)[65]
inp::\ibus_reader:il_read_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
out::address_from_pc_0
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(this_chip_selected)sinphase_zeros[66]
inp::\ibus_reader:il_read_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::this_chip_selected
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(\ibus_reader:this_is_a_ctrl_transaction\)[67]
inp::\ibus_reader:il_read_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::\ibus_reader:this_is_a_ctrl_transaction\
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(address_from_pc_7)[68]
inp::\ibus_reader:il_read_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
out::address_from_pc_7
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(bp_end_address_3)[69]
inp::\ibus_reader:il_read_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::bp_end_address_3
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(data_from_pc_15)[70]
inp::ao_from_pc_strobe
              tS              4.0 ns     1 pass
inp::\ibus_reader:il_read_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
out::data_from_pc_15
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(\sp_read:delay_count_8\)[72]
inp::sinphase_zeros
---->sinphase_zeros
              tS              4.0 ns     1 pass
inp::\sp_read:counter_read_stateSBV_1\.Q
              tSCS            8.0 ns     1 pass
out::\sp_read:delay_count_8\
              tCO             6.5 ns   
----------------------------------------------------------------------------
cmb::reset[78]
inp::fast
              tPD             10.0 ns    1 pass
----------------------------------------------------------------------------
reg::(\sp_read:reset_count_1\)[83]
inp::\sp_read:counter_read_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
out::\sp_read:reset_count_1\
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(sensor_address_3)ao_to_pc_ack[92]
inp::\sp_read:counter_address_3\.Q
              tSCS            8.0 ns     1 pass
out::sensor_address_3
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::ao_to_pc_strobe[93]
inp::ao_to_pc_ack
---->ao_to_pc_ack
              tS              4.0 ns     1 pass
inp::\ibus_writer:iu_writeSBV_0\.Q
              tSCS            8.0 ns     1 pass
out::ao_to_pc_strobe
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::ao_from_pc_ack[94]
inp::\ibus_reader:il_read_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
out::ao_from_pc_ack
              tCO             6.5 ns   
inp::il_tristate.Q
              tER             16.5 ns    1 pass
----------------------------------------------------------------------------
reg::(\sp_read:delay_count_0\)d(1)[103]
inp::sinphase_zeros
---->sinphase_zeros
              tS              4.0 ns     1 pass
inp::\sp_read:counter_read_stateSBV_1\.Q
              tSCS            8.0 ns     1 pass
out::\sp_read:delay_count_0\
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(\ibus_writer:iu_writeSBV_1\)d(4)[106]
inp::ao_to_pc_ack
---->ao_to_pc_ack
              tS              4.0 ns     1 pass
inp::\ibus_writer:iu_writeSBV_0\.Q
              tSCS            8.0 ns     1 pass
out::\ibus_writer:iu_writeSBV_1\
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(\sp_read:delay_count_5\)d(7)[109]
inp::sinphase_zeros
---->sinphase_zeros
              tS              4.0 ns     1 pass
inp::\sp_read:counter_read_stateSBV_1\.Q
              tSCS            8.0 ns     1 pass
out::\sp_read:delay_count_5\
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::d(16)[122]
inp::\ibus_writer:iu_writeSBV_0\.Q
              tSCS            8.0 ns     1 pass
out::d(16)
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::d(17)[123]
inp::\ibus_writer:iu_writeSBV_0\.Q
              tSCS            8.0 ns     1 pass
out::d(17)
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::d(18)[124]
inp::\ibus_writer:iu_writeSBV_0\.Q
              tSCS            8.0 ns     1 pass
out::d(18)
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::d(19)[125]
inp::\ibus_writer:iu_writeSBV_0\.Q
              tSCS            8.0 ns     1 pass
out::d(19)
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::d(20)[126]
inp::\ibus_writer:iu_writeSBV_0\.Q
              tSCS            8.0 ns     1 pass
out::d(20)
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::d(21)[127]
inp::\ibus_writer:iu_writeSBV_0\.Q
              tSCS            8.0 ns     1 pass
out::d(21)
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::d(22)[128]
inp::\ibus_writer:iu_writeSBV_0\.Q
              tSCS            8.0 ns     1 pass
out::d(22)
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::d(23)[129]
inp::\ibus_writer:iu_writeSBV_0\.Q
              tSCS            8.0 ns     1 pass
out::d(23)
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::d(24)[131]
inp::\ibus_writer:iu_writeSBV_0\.Q
              tSCS            8.0 ns     1 pass
out::d(24)
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::d(25)[132]
inp::\ibus_writer:iu_writeSBV_0\.Q
              tSCS            8.0 ns     1 pass
out::d(25)
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::d(26)[133]
inp::\ibus_writer:iu_writeSBV_0\.Q
              tSCS            8.0 ns     1 pass
out::d(26)
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::d(27)[134]
inp::\ibus_writer:iu_writeSBV_0\.Q
              tSCS            8.0 ns     1 pass
out::d(27)
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::d(28)[135]
inp::\ibus_writer:iu_writeSBV_0\.Q
              tSCS            8.0 ns     1 pass
out::d(28)
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::d(29)[136]
inp::\ibus_writer:iu_writeSBV_0\.Q
              tSCS            8.0 ns     1 pass
out::d(29)
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::d(30)[137]
inp::\ibus_writer:iu_writeSBV_0\.Q
              tSCS            8.0 ns     1 pass
out::d(30)
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::d(31)[138]
inp::\ibus_writer:iu_writeSBV_0\.Q
              tSCS            8.0 ns     1 pass
out::d(31)
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(\bp_io:bp_access_stateSBV_1\)bpd(0)[143]
inp::\bp_io:bp_access_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
out::\bp_io:bp_access_stateSBV_1\
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(sensor_data_5)bpd(1)[144]
inp::bpd(5)
---->bpd(5)
              tS              4.0 ns     1 pass
inp::\bp_io:bp_access_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
out::sensor_data_5
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(\sp_read:counter_address_7\)bpd(2)[145]
inp::sinphase_zeros
---->sinphase_zeros
---->S_4
              tS              10.0 ns    2 passes
inp::\sp_read:counter_address_0\.Q
---->S_4
              tSCS            14.0 ns    2 passes
out::\sp_read:counter_address_7\
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(\sp_read:counter_address_3\)bpd(3)[146]
inp::sinphase_zeros
---->sinphase_zeros
---->S_12
              tS              10.0 ns    2 passes
inp::\sp_read:counter_read_stateSBV_0\.Q
---->S_12
              tSCS            14.0 ns    2 passes
out::\sp_read:counter_address_3\
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(\sp_read:counter_address_4\)bpd(4)[147]
inp::sinphase_zeros
---->sinphase_zeros
---->S_9
              tS              10.0 ns    2 passes
inp::\sp_read:counter_address_4\.Q
---->S_9
              tSCS            14.0 ns    2 passes
out::\sp_read:counter_address_4\
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(sensor_data_1)bpd(5)[148]
inp::bpd(1)
---->bpd(1)
              tS              4.0 ns     1 pass
inp::\bp_io:bp_access_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
out::sensor_data_1
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(sensor_data_4)bpd(6)[149]
inp::bpd(4)
---->bpd(4)
              tS              4.0 ns     1 pass
inp::\bp_io:bp_access_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
out::sensor_data_4
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(tristate_stateSBV_0)bpd(7)[150]
inp::this_chip_selected.Q
              tSCS            8.0 ns     1 pass
out::tristate_stateSBV_0
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::bpd(10)[154]
inp::ao_from_pc_strobe
              tS              4.0 ns     1 pass
inp::\ibus_reader:il_read_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
out::bpd(10)
              tCO             6.5 ns   
inp::bpctrl(0).Q
              tER             16.5 ns    1 pass
----------------------------------------------------------------------------
reg::bpd(11)[155]
inp::ao_from_pc_strobe
              tS              4.0 ns     1 pass
inp::\ibus_reader:il_read_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
out::bpd(11)
              tCO             6.5 ns   
inp::bpctrl(0).Q
              tER             16.5 ns    1 pass
----------------------------------------------------------------------------
reg::bpd(12)[156]
inp::ao_from_pc_strobe
              tS              4.0 ns     1 pass
inp::\ibus_reader:il_read_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
out::bpd(12)
              tCO             6.5 ns   
inp::bpctrl(0).Q
              tER             16.5 ns    1 pass
----------------------------------------------------------------------------
reg::bpd(13)[157]
inp::ao_from_pc_strobe
              tS              4.0 ns     1 pass
inp::\ibus_reader:il_read_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
out::bpd(13)
              tCO             6.5 ns   
inp::bpctrl(0).Q
              tER             16.5 ns    1 pass
----------------------------------------------------------------------------
reg::bpd(14)[158]
inp::ao_from_pc_strobe
              tS              4.0 ns     1 pass
inp::\ibus_reader:il_read_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
out::bpd(14)
              tCO             6.5 ns   
inp::bpctrl(0).Q
              tER             16.5 ns    1 pass
----------------------------------------------------------------------------
reg::bpd(15)[159]
inp::ao_from_pc_strobe
              tS              4.0 ns     1 pass
inp::\ibus_reader:il_read_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
out::bpd(15)
              tCO             6.5 ns   
inp::bpctrl(0).Q
              tER             16.5 ns    1 pass
----------------------------------------------------------------------------
reg::(sensor_data_7)[887]
inp::bpd(7)
---->bpd(7)
              tS              4.0 ns     1 pass
inp::\bp_io:bp_access_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
out::sensor_data_7
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(sensor_data_2)[889]
inp::bpd(2)
---->bpd(2)
              tS              4.0 ns     1 pass
inp::\bp_io:bp_access_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
out::sensor_data_2
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(\sp_read:counter_address_5\)[891]
inp::sinphase_zeros
---->sinphase_zeros
---->S_8
              tS              10.0 ns    2 passes
inp::\sp_read:counter_read_stateSBV_2\.Q
---->S_8
              tSCS            14.0 ns    2 passes
out::\sp_read:counter_address_5\
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(\sp_read:counter_address_2\)[893]
inp::sinphase_zeros
---->sinphase_zeros
---->S_14
              tS              10.0 ns    2 passes
inp::\sp_read:counter_read_stateSBV_0\.Q
---->S_14
              tSCS            14.0 ns    2 passes
out::\sp_read:counter_address_2\
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(\sp_read:counter_address_6\)[895]
inp::sinphase_zeros
---->sinphase_zeros
---->S_6
              tS              10.0 ns    2 passes
inp::\sp_read:counter_read_stateSBV_2\.Q
---->S_6
              tSCS            14.0 ns    2 passes
out::\sp_read:counter_address_6\
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(sensor_data_3)[897]
inp::bpd(3)
---->bpd(3)
              tS              4.0 ns     1 pass
inp::\bp_io:bp_access_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
out::sensor_data_3
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(sensor_data_6)[899]
inp::bpd(6)
---->bpd(6)
              tS              4.0 ns     1 pass
inp::\bp_io:bp_access_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
out::sensor_data_6
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(\sp_read:counter_address_1\)[901]
inp::sinphase_zeros
---->sinphase_zeros
---->S_16
              tS              10.0 ns    2 passes
inp::\sp_read:counter_read_stateSBV_0\.Q
---->S_16
              tSCS            14.0 ns    2 passes
out::\sp_read:counter_address_1\
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(sensor_data_11)[905]
inp::bpd(11)
              tS              4.0 ns     1 pass
inp::\bp_io:bp_access_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
out::sensor_data_11
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(sensor_data_12)[907]
inp::bpd(12)
              tS              4.0 ns     1 pass
inp::\bp_io:bp_access_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
out::sensor_data_12
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(sensor_data_13)[909]
inp::bpd(13)
              tS              4.0 ns     1 pass
inp::\bp_io:bp_access_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
out::sensor_data_13
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(sensor_data_14)[911]
inp::bpd(14)
              tS              4.0 ns     1 pass
inp::\bp_io:bp_access_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
out::sensor_data_14
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(sensor_to_bp_read_ack)[913]
inp::\bp_io:bp_access_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
out::sensor_to_bp_read_ack
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(\sp_read:reset_count_2\)[919]
inp::\sp_read:counter_read_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
out::\sp_read:reset_count_2\
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(\ibus_writer:timeout_1\)[921]
inp::ao_to_pc_ack
---->ao_to_pc_ack
              tS              4.0 ns     1 pass
inp::\ibus_writer:iu_writeSBV_0\.Q
              tSCS            8.0 ns     1 pass
out::\ibus_writer:timeout_1\
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(\sp_read:counter_read_stateSBV_0\)[925]
inp::\sp_read:counter_address_0\.Q
---->\sp_read:cmp_vv_us_MODGEN_10\
              tSCS            14.0 ns    2 passes
out::\sp_read:counter_read_stateSBV_0\
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(sensor_address_0)[927]
inp::\sp_read:counter_address_0\.Q
              tSCS            8.0 ns     1 pass
out::sensor_address_0
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(\sp_read:counter_read_stateSBV_3\)[929]
inp::sinphase_zeros
---->sinphase_zeros
              tS              4.0 ns     1 pass
inp::\sp_read:counter_address_0\.Q
---->\sp_read:cmp_vv_us_MODGEN_10\
              tSCS            14.0 ns    2 passes
out::\sp_read:counter_read_stateSBV_3\
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(sensor_address_5)[931]
inp::\sp_read:counter_address_3\.Q
              tSCS            8.0 ns     1 pass
out::sensor_address_5
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(sensor_address_4)[933]
inp::\sp_read:counter_address_3\.Q
              tSCS            8.0 ns     1 pass
out::sensor_address_4
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(sensor_data_0)[937]
inp::bpd(0)
---->bpd(0)
              tS              4.0 ns     1 pass
inp::\bp_io:bp_access_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
out::sensor_data_0
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(sensor_data_10)[939]
inp::bpd(10)
              tS              4.0 ns     1 pass
inp::\bp_io:bp_access_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
out::sensor_data_10
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(sensor_data_8)[941]
inp::bpd(8)
              tS              4.0 ns     1 pass
inp::\bp_io:bp_access_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
out::sensor_data_8
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(sensor_data_9)[943]
inp::bpd(9)
              tS              4.0 ns     1 pass
inp::\bp_io:bp_access_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
out::sensor_data_9
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(bp_start_address_6)[951]
inp::\ibus_reader:il_read_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::bp_start_address_6
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(address_from_pc_1)[953]
inp::\ibus_reader:il_read_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
out::address_from_pc_1
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(bp_end_address_2)[955]
inp::\ibus_reader:il_read_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::bp_end_address_2
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(bp_end_address_4)[957]
inp::\ibus_reader:il_read_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::bp_end_address_4
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(bp_end_address_6)[959]
inp::\ibus_reader:il_read_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::bp_end_address_6
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(bp_start_address_2)[961]
inp::\ibus_reader:il_read_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::bp_start_address_2
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(bp_start_address_5)[963]
inp::\ibus_reader:il_read_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::bp_start_address_5
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(data_from_pc_14)[965]
inp::ao_from_pc_strobe
              tS              4.0 ns     1 pass
inp::\ibus_reader:il_read_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
out::data_from_pc_14
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(\sp_read:counter_address_0\)[969]
inp::sinphase_zeros
---->sinphase_zeros
---->S_18
              tS              10.0 ns    2 passes
inp::\sp_read:counter_read_stateSBV_0\.Q
---->S_18
              tSCS            14.0 ns    2 passes
out::\sp_read:counter_address_0\
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(sensor_address_7)[983]
inp::\sp_read:counter_address_3\.Q
              tSCS            8.0 ns     1 pass
out::sensor_address_7
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(\sp_read:counter_read_stateSBV_1\)[985]
inp::\sp_read:counter_address_0\.Q
---->\sp_read:cmp_vv_us_MODGEN_10\
              tSCS            14.0 ns    2 passes
out::\sp_read:counter_read_stateSBV_1\
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(sensor_to_ibus_req)[989]
inp::\sp_read:counter_read_stateSBV_1\.Q
              tSCS            8.0 ns     1 pass
out::sensor_to_ibus_req
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(sensor_address_6)[993]
inp::\sp_read:counter_address_3\.Q
              tSCS            8.0 ns     1 pass
out::sensor_address_6
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(loopback_state)[999]
inp::\ibus_reader:il_read_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::loopback_state
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(address_from_pc_5)[1001]
inp::\ibus_reader:il_read_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
out::address_from_pc_5
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(\ibus_reader:timeout_3\)[1005]
inp::ao_from_pc_strobe
              tS              4.0 ns     1 pass
inp::\ibus_reader:il_read_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
out::\ibus_reader:timeout_3\
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(address_from_pc_4)[1009]
inp::\ibus_reader:il_read_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
out::address_from_pc_4
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(\ibus_reader:timeout_2\)[1013]
inp::ao_from_pc_strobe
              tS              4.0 ns     1 pass
inp::\ibus_reader:il_read_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
out::\ibus_reader:timeout_2\
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(bp_start_address_7)[1015]
inp::\ibus_reader:il_read_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::bp_start_address_7
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(bp_end_address_0)[1017]
inp::\ibus_reader:il_read_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::bp_end_address_0
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(\ibus_reader:timeout_1\)[1019]
inp::ao_from_pc_strobe
---->S_20
              tS              10.0 ns    2 passes
inp::\ibus_reader:il_read_stateSBV_1\.Q
---->S_20
              tSCS            14.0 ns    2 passes
out::\ibus_reader:timeout_1\
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(\ibus_reader:il_read_stateSBV_1\)[1021]
inp::ao_from_pc_strobe
              tS              4.0 ns     1 pass
inp::\ibus_reader:il_read_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
out::\ibus_reader:il_read_stateSBV_1\
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(\sp_read:counter_read_stateSBV_2\)[1023]
inp::sinphase_zeros
              tS              10.0 ns    2 passes
inp::\sp_read:counter_address_0\.Q
---->\sp_read:cmp_vv_us_MODGEN_10\
---->S_2
              tSCS            20.0 ns    3 passes
out::\sp_read:counter_read_stateSBV_2\
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(bp_end_address_1)[1025]
inp::\ibus_reader:il_read_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::bp_end_address_1
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(bp_start_address_0)[1027]
inp::\ibus_reader:il_read_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
inp::fast
---->reset
              tRO             21.0 ns    2 passes
out::bp_start_address_0
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(\ibus_reader:il_read_stateSBV_2\)[1029]
inp::ao_from_pc_strobe
              tS              4.0 ns     1 pass
inp::\ibus_reader:il_read_stateSBV_1\.Q
              tSCS            8.0 ns     1 pass
out::\ibus_reader:il_read_stateSBV_2\
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(\sp_read:delay_count_9\)[1041]
inp::sinphase_zeros
---->sinphase_zeros
              tS              4.0 ns     1 pass
inp::\sp_read:counter_read_stateSBV_1\.Q
              tSCS            8.0 ns     1 pass
out::\sp_read:delay_count_9\
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(\sp_read:delay_count_2\)[1045]
inp::sinphase_zeros
---->sinphase_zeros
              tS              4.0 ns     1 pass
inp::\sp_read:counter_read_stateSBV_1\.Q
              tSCS            8.0 ns     1 pass
out::\sp_read:delay_count_2\
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(il_tristate)[1063]
inp::il_tristate.Q
              tSCS            8.0 ns     1 pass
out::il_tristate
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(\sp_read:delay_count_3\)[1065]
inp::sinphase_zeros
---->sinphase_zeros
              tS              4.0 ns     1 pass
inp::\sp_read:counter_read_stateSBV_1\.Q
              tSCS            8.0 ns     1 pass
out::\sp_read:delay_count_3\
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(\sp_read:reset_count_0\)[1067]
inp::\sp_read:counter_read_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
out::\sp_read:reset_count_0\
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(\sp_read:delay_count_4\)[1069]
inp::sinphase_zeros
---->sinphase_zeros
              tS              4.0 ns     1 pass
inp::\sp_read:counter_read_stateSBV_1\.Q
              tSCS            8.0 ns     1 pass
out::\sp_read:delay_count_4\
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(\sp_read:delay_count_6\)[1081]
inp::sinphase_zeros
---->sinphase_zeros
              tS              4.0 ns     1 pass
inp::\sp_read:counter_read_stateSBV_1\.Q
              tSCS            8.0 ns     1 pass
out::\sp_read:delay_count_6\
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(\sp_read:delay_count_7\)[1085]
inp::sinphase_zeros
---->sinphase_zeros
              tS              4.0 ns     1 pass
inp::\sp_read:counter_read_stateSBV_1\.Q
              tSCS            8.0 ns     1 pass
out::\sp_read:delay_count_7\
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(\sp_read:delay_count_1\)[1093]
inp::sinphase_zeros
---->sinphase_zeros
              tS              4.0 ns     1 pass
inp::\sp_read:counter_read_stateSBV_1\.Q
              tSCS            8.0 ns     1 pass
out::\sp_read:delay_count_1\
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(\ibus_writer:iu_writeSBV_0\)[1095]
inp::ao_to_pc_ack
---->ao_to_pc_ack
              tS              4.0 ns     1 pass
inp::\ibus_writer:iu_writeSBV_0\.Q
              tSCS            8.0 ns     1 pass
out::\ibus_writer:iu_writeSBV_0\
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(\ibus_writer:timeout_0\)[1099]
inp::ao_to_pc_ack
---->ao_to_pc_ack
              tS              4.0 ns     1 pass
inp::\ibus_writer:iu_writeSBV_0\.Q
              tSCS            8.0 ns     1 pass
out::\ibus_writer:timeout_0\
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(\ibus_writer:timeout_2\)[1103]
inp::ao_to_pc_ack
---->ao_to_pc_ack
              tS              4.0 ns     1 pass
inp::\ibus_writer:iu_writeSBV_0\.Q
              tSCS            8.0 ns     1 pass
out::\ibus_writer:timeout_2\
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(\ibus_writer:timeout_3\)[1105]
inp::ao_to_pc_ack
---->ao_to_pc_ack
              tS              4.0 ns     1 pass
inp::\ibus_writer:iu_writeSBV_0\.Q
              tSCS            8.0 ns     1 pass
out::\ibus_writer:timeout_3\
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(\bp_io:timeout_1\)[1111]
inp::\bp_io:bp_access_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
out::\bp_io:timeout_1\
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(write_to_bp_ack)[1113]
inp::\bp_io:bp_access_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
out::write_to_bp_ack
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(\bp_io:bp_access_stateSBV_0\)[1115]
inp::\bp_io:bp_access_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
out::\bp_io:bp_access_stateSBV_0\
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(\bp_io:bp_access_stateSBV_2\)[1117]
inp::\bp_io:bp_access_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
out::\bp_io:bp_access_stateSBV_2\
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(\bp_io:timeout_2\)[1119]
inp::\bp_io:bp_access_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
out::\bp_io:timeout_2\
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(to_pc_ack)[1121]
inp::\ibus_writer:iu_writeSBV_0\.Q
              tSCS            8.0 ns     1 pass
out::to_pc_ack
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(\bp_io:timeout_0\)[1125]
inp::\bp_io:bp_access_stateSBV_0\.Q
              tSCS            8.0 ns     1 pass
out::\bp_io:timeout_0\
              tCO             6.5 ns   
----------------------------------------------------------------------------
reg::(\sp_read:old_phase\)[1129]
inp::sinphase_zeros
---->sinphase_zeros
              tS              4.0 ns     1 pass
inp::fast
              tPO             15.0 ns    1 pass
inp::fast
              tRO             15.0 ns    1 pass
out::\sp_read:old_phase\
              tCO             6.5 ns   
----------------------------------------------------------------------------

Worst Case Path Summary
-----------------------

                    tPD = 10.0 ns for led2 
                     tS = 10.0 ns for \sp_read:counter_address_7\.D 
                   tSCS = 20.0 ns for \sp_read:counter_read_stateSBV_2\.T  using clock signal clk
                    tCO = 12.5 ns for bpctrl_h_tristate 
                    tPO = 15.0 ns for \sp_read:old_phase\.AP 
                    tRO = 21.0 ns for bp_start_address_4.AR 
                    tER = 16.5 ns for bpctrl(4).OE 



Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully  
